2021-05-26 19:09:36 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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// Copyright (c) 2016-2017 Hisilicon Limited.
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#ifndef __HCLGE_MDIO_H
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#define __HCLGE_MDIO_H
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int hclge_mac_mdio_config(struct hclge_dev *hdev);
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int hclge_mac_connect_phy(struct hnae3_handle *handle);
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void hclge_mac_disconnect_phy(struct hnae3_handle *handle);
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void hclge_mac_start_phy(struct hclge_dev *hdev);
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void hclge_mac_stop_phy(struct hclge_dev *hdev);
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2021-07-12 19:01:19 +00:00
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u16 hclge_read_phy_reg(struct hclge_dev *hdev, u16 reg_addr);
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int hclge_write_phy_reg(struct hclge_dev *hdev, u16 reg_addr, u16 val);
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2021-05-26 19:09:36 +00:00
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#endif
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