2021-05-26 19:09:36 +00:00
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2020 - Google Inc
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* Author: Andrew Scull <ascull@google.com>
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*/
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#include <hyp/switch.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_host.h>
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#include <asm/kvm_hyp.h>
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#include <asm/kvm_mmu.h>
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2021-09-23 16:59:15 +00:00
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#include <kvm/arm_hypercalls.h>
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2021-05-26 19:09:36 +00:00
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2021-09-23 16:59:15 +00:00
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static void handle_host_hcall(unsigned long func_id,
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struct kvm_cpu_context *host_ctxt)
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2021-07-12 19:01:19 +00:00
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{
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2021-09-23 16:59:15 +00:00
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unsigned long ret = 0;
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2021-07-12 19:01:19 +00:00
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2021-09-23 16:59:15 +00:00
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switch (func_id) {
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case KVM_HOST_SMCCC_FUNC(__kvm_vcpu_run): {
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unsigned long r1 = host_ctxt->regs.regs[1];
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struct kvm_vcpu *vcpu = (struct kvm_vcpu *)r1;
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2021-07-12 19:01:19 +00:00
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2021-09-23 16:59:15 +00:00
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ret = __kvm_vcpu_run(kern_hyp_va(vcpu));
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break;
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}
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case KVM_HOST_SMCCC_FUNC(__kvm_flush_vm_context):
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__kvm_flush_vm_context();
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break;
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case KVM_HOST_SMCCC_FUNC(__kvm_tlb_flush_vmid_ipa): {
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unsigned long r1 = host_ctxt->regs.regs[1];
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struct kvm_s2_mmu *mmu = (struct kvm_s2_mmu *)r1;
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phys_addr_t ipa = host_ctxt->regs.regs[2];
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int level = host_ctxt->regs.regs[3];
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2021-09-23 16:59:15 +00:00
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__kvm_tlb_flush_vmid_ipa(kern_hyp_va(mmu), ipa, level);
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break;
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}
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case KVM_HOST_SMCCC_FUNC(__kvm_tlb_flush_vmid): {
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unsigned long r1 = host_ctxt->regs.regs[1];
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struct kvm_s2_mmu *mmu = (struct kvm_s2_mmu *)r1;
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2021-09-23 16:59:15 +00:00
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__kvm_tlb_flush_vmid(kern_hyp_va(mmu));
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break;
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}
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case KVM_HOST_SMCCC_FUNC(__kvm_flush_cpu_context): {
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unsigned long r1 = host_ctxt->regs.regs[1];
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struct kvm_s2_mmu *mmu = (struct kvm_s2_mmu *)r1;
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2021-09-23 16:59:15 +00:00
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__kvm_flush_cpu_context(kern_hyp_va(mmu));
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break;
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}
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case KVM_HOST_SMCCC_FUNC(__kvm_timer_set_cntvoff): {
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u64 cntvoff = host_ctxt->regs.regs[1];
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2021-09-23 16:59:15 +00:00
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__kvm_timer_set_cntvoff(cntvoff);
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break;
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}
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case KVM_HOST_SMCCC_FUNC(__kvm_enable_ssbs):
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__kvm_enable_ssbs();
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break;
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case KVM_HOST_SMCCC_FUNC(__vgic_v3_get_ich_vtr_el2):
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ret = __vgic_v3_get_ich_vtr_el2();
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break;
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case KVM_HOST_SMCCC_FUNC(__vgic_v3_read_vmcr):
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ret = __vgic_v3_read_vmcr();
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break;
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case KVM_HOST_SMCCC_FUNC(__vgic_v3_write_vmcr): {
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u32 vmcr = host_ctxt->regs.regs[1];
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__vgic_v3_write_vmcr(vmcr);
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break;
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}
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case KVM_HOST_SMCCC_FUNC(__vgic_v3_init_lrs):
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__vgic_v3_init_lrs();
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break;
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case KVM_HOST_SMCCC_FUNC(__kvm_get_mdcr_el2):
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ret = __kvm_get_mdcr_el2();
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break;
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case KVM_HOST_SMCCC_FUNC(__vgic_v3_save_aprs): {
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unsigned long r1 = host_ctxt->regs.regs[1];
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struct vgic_v3_cpu_if *cpu_if = (struct vgic_v3_cpu_if *)r1;
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2021-09-23 16:59:15 +00:00
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__vgic_v3_save_aprs(kern_hyp_va(cpu_if));
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break;
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}
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case KVM_HOST_SMCCC_FUNC(__vgic_v3_restore_aprs): {
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unsigned long r1 = host_ctxt->regs.regs[1];
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struct vgic_v3_cpu_if *cpu_if = (struct vgic_v3_cpu_if *)r1;
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2021-09-23 16:59:15 +00:00
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__vgic_v3_restore_aprs(kern_hyp_va(cpu_if));
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break;
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}
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default:
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/* Invalid host HVC. */
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host_ctxt->regs.regs[0] = SMCCC_RET_NOT_SUPPORTED;
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return;
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}
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2021-09-23 16:59:15 +00:00
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host_ctxt->regs.regs[0] = SMCCC_RET_SUCCESS;
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host_ctxt->regs.regs[1] = ret;
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}
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void handle_trap(struct kvm_cpu_context *host_ctxt)
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{
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u64 esr = read_sysreg_el2(SYS_ESR);
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unsigned long func_id;
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if (ESR_ELx_EC(esr) != ESR_ELx_EC_HVC64)
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hyp_panic();
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func_id = host_ctxt->regs.regs[0];
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handle_host_hcall(func_id, host_ctxt);
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}
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