2021-05-26 19:09:36 +00:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2019 SiFive
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*/
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#ifndef _ASM_RISCV_SET_MEMORY_H
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#define _ASM_RISCV_SET_MEMORY_H
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#ifndef __ASSEMBLY__
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/*
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* Functions to change memory attributes.
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*/
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#ifdef CONFIG_MMU
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int set_memory_ro(unsigned long addr, int numpages);
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int set_memory_rw(unsigned long addr, int numpages);
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int set_memory_x(unsigned long addr, int numpages);
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int set_memory_nx(unsigned long addr, int numpages);
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#else
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static inline int set_memory_ro(unsigned long addr, int numpages) { return 0; }
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static inline int set_memory_rw(unsigned long addr, int numpages) { return 0; }
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static inline int set_memory_x(unsigned long addr, int numpages) { return 0; }
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static inline int set_memory_nx(unsigned long addr, int numpages) { return 0; }
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2021-07-12 19:01:19 +00:00
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#endif
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2021-05-26 19:09:36 +00:00
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int set_direct_map_invalid_noflush(struct page *page);
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int set_direct_map_default_noflush(struct page *page);
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#endif /* __ASSEMBLY__ */
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2021-09-23 16:59:15 +00:00
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#ifdef CONFIG_ARCH_HAS_STRICT_KERNEL_RWX
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2021-05-26 19:09:36 +00:00
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#ifdef CONFIG_64BIT
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#define SECTION_ALIGN (1 << 21)
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#else
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#define SECTION_ALIGN (1 << 22)
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#endif
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2021-09-23 16:59:15 +00:00
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#else /* !CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */
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2021-05-26 19:09:36 +00:00
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#define SECTION_ALIGN L1_CACHE_BYTES
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2021-09-23 16:59:15 +00:00
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#endif /* CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */
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2021-05-26 19:09:36 +00:00
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#endif /* _ASM_RISCV_SET_MEMORY_H */
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