2021-05-27 00:09:36 +05:00
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/* SPDX-License-Identifier: MIT */
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#ifndef __NV50_BAR_H__
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#define __NV50_BAR_H__
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#define nv50_bar(p) container_of((p), struct nv50_bar, base)
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#include "priv.h"
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struct nv50_bar {
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struct nvkm_bar base;
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u32 pgd_addr;
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struct nvkm_gpuobj *mem;
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struct nvkm_gpuobj *pad;
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struct nvkm_gpuobj *pgd;
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struct nvkm_vmm *bar1_vmm;
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struct nvkm_gpuobj *bar1;
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struct nvkm_vmm *bar2_vmm;
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struct nvkm_gpuobj *bar2;
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};
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2021-10-02 21:09:28 +05:00
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int nv50_bar_new_(const struct nvkm_bar_func *, struct nvkm_device *, enum nvkm_subdev_type,
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2021-05-27 00:09:36 +05:00
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int, u32 pgd_addr, struct nvkm_bar **);
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void *nv50_bar_dtor(struct nvkm_bar *);
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int nv50_bar_oneinit(struct nvkm_bar *);
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void nv50_bar_init(struct nvkm_bar *);
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void nv50_bar_bar1_init(struct nvkm_bar *);
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void nv50_bar_bar1_wait(struct nvkm_bar *);
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struct nvkm_vmm *nv50_bar_bar1_vmm(struct nvkm_bar *);
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void nv50_bar_bar2_init(struct nvkm_bar *);
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struct nvkm_vmm *nv50_bar_bar2_vmm(struct nvkm_bar *);
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#endif
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