2022-03-05 16:17:59 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2021-10-27 13:46:41 +00:00
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#ifndef _DT_BINDINGS_SAMSUNG_I2S_H
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#define _DT_BINDINGS_SAMSUNG_I2S_H
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2022-03-05 16:17:59 +00:00
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#define CLK_I2S_CDCLK 0 /* the CDCLK (CODECLKO) gate clock */
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#define CLK_I2S_RCLK_SRC 1 /* the RCLKSRC mux clock (corresponding to
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* RCLKSRC bit in IISMOD register)
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*/
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#define CLK_I2S_RCLK_PSR 2 /* the RCLK prescaler divider clock
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* (corresponding to the IISPSR register)
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*/
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2021-10-27 13:46:41 +00:00
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#endif /* _DT_BINDINGS_SAMSUNG_I2S_H */
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