"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"PublicDescription":"Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"BriefDescription":"Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region",
"BriefDescription":"Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache.",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"PublicDescription":"Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue":"101",
"TakenAlone":"1",
"UMask":"0x1"
},
{
"BriefDescription":"Number of times an RTM execution successfully committed",
"CollectPEBSRecord":"2",
"Counter":"0,1,2,3,4,5,6,7",
"EventCode":"0xc9",
"EventName":"RTM_RETIRED.COMMIT",
"PEBScounters":"0,1,2,3,4,5,6,7",
"PublicDescription":"Counts the number of times RTM commit succeeded.",
"SampleAfterValue":"100003",
"UMask":"0x2"
},
{
"BriefDescription":"Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
"PublicDescription":"Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
"PublicDescription":"Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
"BriefDescription":"Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"PublicDescription":"Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"PublicDescription":"Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.",
"PublicDescription":"Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue":"1009",
"TakenAlone":"1",
"UMask":"0x1"
},
{
"BriefDescription":"Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
"CollectPEBSRecord":"2",
"Counter":"0,1,2,3",
"EventCode":"0x54",
"EventName":"TX_MEM.HLE_ELISION_BUFFER_FULL",
"PEBScounters":"0,1,2,3",
"PublicDescription":"Counts the number of times we could not allocate Lock Buffer.",
"SampleAfterValue":"100003",
"Speculative":"1",
"UMask":"0x40"
},
{
"BriefDescription":"Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
"PublicDescription":"Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.",
"PublicDescription":"Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
"PublicDescription":"Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue":"2003",
"TakenAlone":"1",
"UMask":"0x1"
},
{
"BriefDescription":"Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
"PublicDescription":"Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.",
"BriefDescription":"Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that was not supplied by the L3 cache.",
"CollectPEBSRecord":"2",
"Counter":"0,1,2,3",
"EventCode":"0xB7, 0xBB",
"EventName":"OCR.HWPF_L1D_AND_SWPF.L3_MISS",
"MSRIndex":"0x1a6,0x1a7",
"MSRValue":"0x3FFFC00400",
"Offcore":"1",
"PEBScounters":"0,1,2,3",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue":"100003",
"Speculative":"1",
"UMask":"0x1"
},
{
"BriefDescription":"Counts demand instruction fetches and L1 instruction cache prefetches that was not supplied by the L3 cache.",
"CollectPEBSRecord":"2",
"Counter":"0,1,2,3",
"EventCode":"0xB7, 0xBB",
"EventName":"OCR.DEMAND_CODE_RD.L3_MISS",
"MSRIndex":"0x1a6,0x1a7",
"MSRValue":"0x3FFFC00004",
"Offcore":"1",
"PEBScounters":"0,1,2,3",
"PublicDescription":"Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue":"100003",
"Speculative":"1",
"UMask":"0x1"
},
{
"BriefDescription":"Number of times an RTM execution aborted.",
"BriefDescription":"Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
"PublicDescription":"Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
"SampleAfterValue":"100003",
"UMask":"0x20"
},
{
"BriefDescription":"Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
