Qortal/Brooklyn
3
0
Fork 1
mirror of https://github.com/Qortal/Brooklyn.git synced 2025-01-30 14:52:17 +00:00
Code Issues Projects Releases Wiki Activity

redo

Browse Source
This commit is contained in:
Raziel K. Crowe 2022-09-09 14:11:12 +05:00
parent 9c4c3c24a5
commit 4da0de7e0f
98 changed files with 3910 additions and 96509 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

BIN
Security Algo Accelerator/docs/Cortex_A72_MPCore_Cryptography_Technical_Reference_Manual-r1p0-00rel0.pdf
View File

Binary file not shown.

246
Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aes.sv
View File

@ -1,246 +0,0 @@
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_aes
(
input wire clk,
input wire reset,
input wire ival_v1_q,
input wire aesd_v1_q,
input wire aese_v1_q,
input wire aesd_or_e_v1_q,
input wire aesmc_v1_q,
input wire aesimc_v1_q,
input wire aesdimc_v1_q,
input wire aesemc_v1_q,
input wire [127:0] opa_v1,
input wire [127:0] opb_v1,
output wire [127:0] aesout_v2
);
wire [15:0] aes_shf_v1;
wire [127:0] aesd_out_v2;
wire [15:0] aesd_shf_v1;
wire [127:0] aesd_v1;
reg aesdimc_h_v2_q;
reg aesdimc_l_v2_q;
wire [127:0] aesdimc_out_v2;
wire [127:0] aese_out_v2;
wire [15:0] aese_shf_v1;
wire [127:0] aese_v1;
wire [127:0] aesed_lut_in_v1;
wire [127:0] aesed_lut_out_v1;
reg aesemc_h_v2_q;
reg aesemc_l_v2_q;
wire [127:0] aesemc_out_v2;
reg aesimc_h_v2_q;
reg aesimc_l_v2_q;
wire [127:0] aesimc_out_v2;
reg aesmc_h_v2_q;
reg aesmc_l_v2_q;
wire [127:0] aesmc_out_v2;
wire block_opa_passthrough;
wire [127:0] opa_aes_nxt_v1;
reg [127:0] opa_aes_v2_q;
wire [127:0] qx_v1;
reg sel_aesd_h_v2_q;
reg sel_aesd_l_v2_q;
wire sel_aesd_v1;
reg sel_aese_h_v2_q;
reg sel_aese_l_v2_q;
wire sel_aese_v1;
assign sel_aesd_v1 = aesd_v1_q & ~aesdimc_v1_q;
assign sel_aese_v1 = aese_v1_q & ~aesemc_v1_q;
assign block_opa_passthrough = aesd_or_e_v1_q;
always_ff @(posedge clk or posedge reset)
begin: u_aesmc_h_v2_q_grp
if (reset == 1'b1) begin
aesmc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
aesmc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
aesimc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
aesimc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
aesdimc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
aesdimc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
aesemc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
aesemc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sel_aesd_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sel_aesd_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sel_aese_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sel_aese_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
end
`ifdef HERCULESAE_XPROP_FLOP
else if (reset == 1'b0 && ival_v1_q == 1'b1) begin
aesmc_h_v2_q <= `HERCULESAE_DFF_DELAY aesmc_v1_q;
aesmc_l_v2_q <= `HERCULESAE_DFF_DELAY aesmc_v1_q;
aesimc_h_v2_q <= `HERCULESAE_DFF_DELAY aesimc_v1_q;
aesimc_l_v2_q <= `HERCULESAE_DFF_DELAY aesimc_v1_q;
aesdimc_h_v2_q <= `HERCULESAE_DFF_DELAY aesdimc_v1_q;
aesdimc_l_v2_q <= `HERCULESAE_DFF_DELAY aesdimc_v1_q;
aesemc_h_v2_q <= `HERCULESAE_DFF_DELAY aesemc_v1_q;
aesemc_l_v2_q <= `HERCULESAE_DFF_DELAY aesemc_v1_q;
sel_aesd_h_v2_q <= `HERCULESAE_DFF_DELAY sel_aesd_v1;
sel_aesd_l_v2_q <= `HERCULESAE_DFF_DELAY sel_aesd_v1;
sel_aese_h_v2_q <= `HERCULESAE_DFF_DELAY sel_aese_v1;
sel_aese_l_v2_q <= `HERCULESAE_DFF_DELAY sel_aese_v1;
end
else if (reset == 1'b0 && ival_v1_q == 1'b0)
begin
end
else begin
aesmc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
aesmc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
aesimc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
aesimc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
aesdimc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
aesdimc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
aesemc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
aesemc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sel_aesd_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sel_aesd_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sel_aese_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sel_aese_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
end
`else
else if (ival_v1_q == 1'b1) begin
aesmc_h_v2_q <= `HERCULESAE_DFF_DELAY aesmc_v1_q;
aesmc_l_v2_q <= `HERCULESAE_DFF_DELAY aesmc_v1_q;
aesimc_h_v2_q <= `HERCULESAE_DFF_DELAY aesimc_v1_q;
aesimc_l_v2_q <= `HERCULESAE_DFF_DELAY aesimc_v1_q;
aesdimc_h_v2_q <= `HERCULESAE_DFF_DELAY aesdimc_v1_q;
aesdimc_l_v2_q <= `HERCULESAE_DFF_DELAY aesdimc_v1_q;
aesemc_h_v2_q <= `HERCULESAE_DFF_DELAY aesemc_v1_q;
aesemc_l_v2_q <= `HERCULESAE_DFF_DELAY aesemc_v1_q;
sel_aesd_h_v2_q <= `HERCULESAE_DFF_DELAY sel_aesd_v1;
sel_aesd_l_v2_q <= `HERCULESAE_DFF_DELAY sel_aesd_v1;
sel_aese_h_v2_q <= `HERCULESAE_DFF_DELAY sel_aese_v1;
sel_aese_l_v2_q <= `HERCULESAE_DFF_DELAY sel_aese_v1;
end
`endif
end
assign qx_v1[127:0] = {128{aesd_or_e_v1_q}} & (opb_v1[127:0] ^ opa_v1[127:0]);
herculesae_vx_aese1 u_aese1(
.q (qx_v1[127:0]),
.aese_out (aese_v1[127:0]),
.aese_shf (aese_shf_v1[15:0]));
herculesae_vx_aesd1 u_aesd1(
.q (qx_v1[127:0]),
.aesd_out (aesd_v1[127:0]),
.aesd_shf (aesd_shf_v1[15:0]));
assign aes_shf_v1[15:0] = {16{aese_v1_q}} & aese_shf_v1[15:0] |
{16{aesd_v1_q}} & aesd_shf_v1[15:0];
assign aesed_lut_in_v1[127:0] = ({128{aese_v1_q}} & aese_v1[127:0]) | ({128{aesd_v1_q}} & aesd_v1[127:0]);
herculesae_vx_aesed2_lut u_aesed2_lut_v1(
.lut_in (aesed_lut_in_v1[127:0]),
.lut_out (aesed_lut_out_v1[127:0]));
assign opa_aes_nxt_v1[127:0] = ({128{aesd_or_e_v1_q}} & aesed_lut_out_v1[127:0])
| ({128{~block_opa_passthrough}} & opa_v1[127:0]);
always_ff @(posedge clk or posedge reset)
begin: u_opa_aes_v2_q_127_0
if (reset == 1'b1)
opa_aes_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}};
`ifdef HERCULESAE_XPROP_FLOP
else if (reset == 1'b0 && ival_v1_q == 1'b1)
opa_aes_v2_q[127:0] <= `HERCULESAE_DFF_DELAY opa_aes_nxt_v1[127:0];
else if (reset == 1'b0 && ival_v1_q == 1'b0)
begin
end
else
opa_aes_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}};
`else
else if (ival_v1_q == 1'b1)
opa_aes_v2_q[127:0] <= `HERCULESAE_DFF_DELAY opa_aes_nxt_v1[127:0];
`endif
end
herculesae_vx_aesmc u_aesmc(
.d_in (opa_aes_v2_q[127:0]),
.mc (aesmc_out_v2[127:0]));
herculesae_vx_aesimc u_aesimc(
.d_in (opa_aes_v2_q[127:0]),
.imc (aesimc_out_v2[127:0]));
herculesae_vx_aesed2 u_aesed2(
.clk (clk),
.reset (reset),
.ival_v1_q (ival_v1_q),
.aes_din_v1 (aesed_lut_out_v1[127:0]),
.aes_shf_v1 (aes_shf_v1[15:0]),
.aesd_out (aesd_out_v2[127:0]),
.aese_out (aese_out_v2[127:0]),
.aesemc_out (aesemc_out_v2[127:0]),
.aesdimc_out (aesdimc_out_v2[127:0]));
assign aesout_v2[127:64] = ({64{sel_aesd_h_v2_q}} & aesd_out_v2[127:64])
| ({64{sel_aese_h_v2_q}} & aese_out_v2[127:64])
| ({64{aesmc_h_v2_q}} & aesmc_out_v2[127:64])
| ({64{aesemc_h_v2_q}} & aesemc_out_v2[127:64])
| ({64{aesimc_h_v2_q}} & aesimc_out_v2[127:64])
| ({64{aesdimc_h_v2_q}} & aesdimc_out_v2[127:64]);
assign aesout_v2[63:0] = ({64{sel_aesd_l_v2_q}} & aesd_out_v2[63:0])
| ({64{sel_aese_l_v2_q}} & aese_out_v2[63:0])
| ({64{aesmc_l_v2_q}} & aesmc_out_v2[63:0])
| ({64{aesemc_l_v2_q}} & aesemc_out_v2[63:0])
| ({64{aesimc_l_v2_q}} & aesimc_out_v2[63:0])
| ({64{aesdimc_l_v2_q}} & aesdimc_out_v2[63:0]);
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

307
Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aesd1.sv
View File

@ -1,307 +0,0 @@
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_aesd1
(
input wire [127:0] q,
output wire [127:0] aesd_out,
output wire [15:0] aesd_shf
);
wire [127:0] aesd_noshf;
wire [7:0] s00;
wire [7:0] s01;
wire [7:0] s02;
wire [7:0] s03;
wire [7:0] s10;
wire [7:0] s11;
wire [7:0] s12;
wire [7:0] s13;
wire [7:0] s20;
wire [7:0] s21;
wire [7:0] s22;
wire [7:0] s23;
wire [7:0] s30;
wire [7:0] s31;
wire [7:0] s32;
wire [7:0] s33;
wire [7:0] sp00;
wire [7:0] sp01;
wire [7:0] sp02;
wire [7:0] sp03;
wire [7:0] sp10;
wire [7:0] sp11;
wire [7:0] sp12;
wire [7:0] sp13;
wire [7:0] sp20;
wire [7:0] sp21;
wire [7:0] sp22;
wire [7:0] sp23;
wire [7:0] sp30;
wire [7:0] sp31;
wire [7:0] sp32;
wire [7:0] sp33;
assign s33[7:0] = q[127:120];
assign s23[7:0] = q[119:112];
assign s13[7:0] = q[111:104];
assign s03[7:0] = q[103:96];
assign s32[7:0] = q[95:88];
assign s22[7:0] = q[87:80];
assign s12[7:0] = q[79:72];
assign s02[7:0] = q[71:64];
assign s31[7:0] = q[63:56];
assign s21[7:0] = q[55:48];
assign s11[7:0] = q[47:40];
assign s01[7:0] = q[39:32];
assign s30[7:0] = q[31:24];
assign s20[7:0] = q[23:16];
assign s10[7:0] = q[15:8];
assign s00[7:0] = q[7:0];
assign sp00[7:0] = s00[7:0];
assign sp01[7:0] = s01[7:0];
assign sp02[7:0] = s02[7:0];
assign sp03[7:0] = s03[7:0];
assign sp10[7:0] = s13[7:0];
assign sp11[7:0] = s10[7:0];
assign sp12[7:0] = s11[7:0];
assign sp13[7:0] = s12[7:0];
assign sp20[7:0] = s22[7:0];
assign sp21[7:0] = s23[7:0];
assign sp22[7:0] = s20[7:0];
assign sp23[7:0] = s21[7:0];
assign sp30[7:0] = s31[7:0];
assign sp31[7:0] = s32[7:0];
assign sp32[7:0] = s33[7:0];
assign sp33[7:0] = s30[7:0];
assign aesd_noshf[0] = sp00[2] ^ sp00[5] ^ sp00[7] ^ 1'b1;
assign aesd_noshf[1] = sp00[0] ^ sp00[3] ^ sp00[6] ^ 1'b0;
assign aesd_noshf[2] = sp00[1] ^ sp00[4] ^ sp00[7] ^ 1'b1;
assign aesd_noshf[3] = sp00[0] ^ sp00[2] ^ sp00[5] ^ 1'b0;
assign aesd_noshf[4] = sp00[1] ^ sp00[3] ^ sp00[6] ^ 1'b0;
assign aesd_noshf[5] = sp00[2] ^ sp00[4] ^ sp00[7] ^ 1'b0;
assign aesd_noshf[6] = sp00[0] ^ sp00[3] ^ sp00[5] ^ 1'b0;
assign aesd_noshf[7] = sp00[1] ^ sp00[4] ^ sp00[6] ^ 1'b0;
assign aesd_noshf[32] = sp01[2] ^ sp01[5] ^ sp01[7] ^ 1'b1;
assign aesd_noshf[33] = sp01[0] ^ sp01[3] ^ sp01[6] ^ 1'b0;
assign aesd_noshf[34] = sp01[1] ^ sp01[4] ^ sp01[7] ^ 1'b1;
assign aesd_noshf[35] = sp01[0] ^ sp01[2] ^ sp01[5] ^ 1'b0;
assign aesd_noshf[36] = sp01[1] ^ sp01[3] ^ sp01[6] ^ 1'b0;
assign aesd_noshf[37] = sp01[2] ^ sp01[4] ^ sp01[7] ^ 1'b0;
assign aesd_noshf[38] = sp01[0] ^ sp01[3] ^ sp01[5] ^ 1'b0;
assign aesd_noshf[39] = sp01[1] ^ sp01[4] ^ sp01[6] ^ 1'b0;
assign aesd_noshf[64] = sp02[2] ^ sp02[5] ^ sp02[7] ^ 1'b1;
assign aesd_noshf[65] = sp02[0] ^ sp02[3] ^ sp02[6] ^ 1'b0;
assign aesd_noshf[66] = sp02[1] ^ sp02[4] ^ sp02[7] ^ 1'b1;
assign aesd_noshf[67] = sp02[0] ^ sp02[2] ^ sp02[5] ^ 1'b0;
assign aesd_noshf[68] = sp02[1] ^ sp02[3] ^ sp02[6] ^ 1'b0;
assign aesd_noshf[69] = sp02[2] ^ sp02[4] ^ sp02[7] ^ 1'b0;
assign aesd_noshf[70] = sp02[0] ^ sp02[3] ^ sp02[5] ^ 1'b0;
assign aesd_noshf[71] = sp02[1] ^ sp02[4] ^ sp02[6] ^ 1'b0;
assign aesd_noshf[96] = sp03[2] ^ sp03[5] ^ sp03[7] ^ 1'b1;
assign aesd_noshf[97] = sp03[0] ^ sp03[3] ^ sp03[6] ^ 1'b0;
assign aesd_noshf[98] = sp03[1] ^ sp03[4] ^ sp03[7] ^ 1'b1;
assign aesd_noshf[99] = sp03[0] ^ sp03[2] ^ sp03[5] ^ 1'b0;
assign aesd_noshf[100] = sp03[1] ^ sp03[3] ^ sp03[6] ^ 1'b0;
assign aesd_noshf[101] = sp03[2] ^ sp03[4] ^ sp03[7] ^ 1'b0;
assign aesd_noshf[102] = sp03[0] ^ sp03[3] ^ sp03[5] ^ 1'b0;
assign aesd_noshf[103] = sp03[1] ^ sp03[4] ^ sp03[6] ^ 1'b0;
assign aesd_noshf[8] = sp10[2] ^ sp10[5] ^ sp10[7] ^ 1'b1;
assign aesd_noshf[9] = sp10[0] ^ sp10[3] ^ sp10[6] ^ 1'b0;
assign aesd_noshf[10] = sp10[1] ^ sp10[4] ^ sp10[7] ^ 1'b1;
assign aesd_noshf[11] = sp10[0] ^ sp10[2] ^ sp10[5] ^ 1'b0;
assign aesd_noshf[12] = sp10[1] ^ sp10[3] ^ sp10[6] ^ 1'b0;
assign aesd_noshf[13] = sp10[2] ^ sp10[4] ^ sp10[7] ^ 1'b0;
assign aesd_noshf[14] = sp10[0] ^ sp10[3] ^ sp10[5] ^ 1'b0;
assign aesd_noshf[15] = sp10[1] ^ sp10[4] ^ sp10[6] ^ 1'b0;
assign aesd_noshf[40] = sp11[2] ^ sp11[5] ^ sp11[7] ^ 1'b1;
assign aesd_noshf[41] = sp11[0] ^ sp11[3] ^ sp11[6] ^ 1'b0;
assign aesd_noshf[42] = sp11[1] ^ sp11[4] ^ sp11[7] ^ 1'b1;
assign aesd_noshf[43] = sp11[0] ^ sp11[2] ^ sp11[5] ^ 1'b0;
assign aesd_noshf[44] = sp11[1] ^ sp11[3] ^ sp11[6] ^ 1'b0;
assign aesd_noshf[45] = sp11[2] ^ sp11[4] ^ sp11[7] ^ 1'b0;
assign aesd_noshf[46] = sp11[0] ^ sp11[3] ^ sp11[5] ^ 1'b0;
assign aesd_noshf[47] = sp11[1] ^ sp11[4] ^ sp11[6] ^ 1'b0;
assign aesd_noshf[72] = sp12[2] ^ sp12[5] ^ sp12[7] ^ 1'b1;
assign aesd_noshf[73] = sp12[0] ^ sp12[3] ^ sp12[6] ^ 1'b0;
assign aesd_noshf[74] = sp12[1] ^ sp12[4] ^ sp12[7] ^ 1'b1;
assign aesd_noshf[75] = sp12[0] ^ sp12[2] ^ sp12[5] ^ 1'b0;
assign aesd_noshf[76] = sp12[1] ^ sp12[3] ^ sp12[6] ^ 1'b0;
assign aesd_noshf[77] = sp12[2] ^ sp12[4] ^ sp12[7] ^ 1'b0;
assign aesd_noshf[78] = sp12[0] ^ sp12[3] ^ sp12[5] ^ 1'b0;
assign aesd_noshf[79] = sp12[1] ^ sp12[4] ^ sp12[6] ^ 1'b0;
assign aesd_noshf[104] = sp13[2] ^ sp13[5] ^ sp13[7] ^ 1'b1;
assign aesd_noshf[105] = sp13[0] ^ sp13[3] ^ sp13[6] ^ 1'b0;
assign aesd_noshf[106] = sp13[1] ^ sp13[4] ^ sp13[7] ^ 1'b1;
assign aesd_noshf[107] = sp13[0] ^ sp13[2] ^ sp13[5] ^ 1'b0;
assign aesd_noshf[108] = sp13[1] ^ sp13[3] ^ sp13[6] ^ 1'b0;
assign aesd_noshf[109] = sp13[2] ^ sp13[4] ^ sp13[7] ^ 1'b0;
assign aesd_noshf[110] = sp13[0] ^ sp13[3] ^ sp13[5] ^ 1'b0;
assign aesd_noshf[111] = sp13[1] ^ sp13[4] ^ sp13[6] ^ 1'b0;
assign aesd_noshf[16] = sp20[2] ^ sp20[5] ^ sp20[7] ^ 1'b1;
assign aesd_noshf[17] = sp20[0] ^ sp20[3] ^ sp20[6] ^ 1'b0;
assign aesd_noshf[18] = sp20[1] ^ sp20[4] ^ sp20[7] ^ 1'b1;
assign aesd_noshf[19] = sp20[0] ^ sp20[2] ^ sp20[5] ^ 1'b0;
assign aesd_noshf[20] = sp20[1] ^ sp20[3] ^ sp20[6] ^ 1'b0;
assign aesd_noshf[21] = sp20[2] ^ sp20[4] ^ sp20[7] ^ 1'b0;
assign aesd_noshf[22] = sp20[0] ^ sp20[3] ^ sp20[5] ^ 1'b0;
assign aesd_noshf[23] = sp20[1] ^ sp20[4] ^ sp20[6] ^ 1'b0;
assign aesd_noshf[48] = sp21[2] ^ sp21[5] ^ sp21[7] ^ 1'b1;
assign aesd_noshf[49] = sp21[0] ^ sp21[3] ^ sp21[6] ^ 1'b0;
assign aesd_noshf[50] = sp21[1] ^ sp21[4] ^ sp21[7] ^ 1'b1;
assign aesd_noshf[51] = sp21[0] ^ sp21[2] ^ sp21[5] ^ 1'b0;
assign aesd_noshf[52] = sp21[1] ^ sp21[3] ^ sp21[6] ^ 1'b0;
assign aesd_noshf[53] = sp21[2] ^ sp21[4] ^ sp21[7] ^ 1'b0;
assign aesd_noshf[54] = sp21[0] ^ sp21[3] ^ sp21[5] ^ 1'b0;
assign aesd_noshf[55] = sp21[1] ^ sp21[4] ^ sp21[6] ^ 1'b0;
assign aesd_noshf[80] = sp22[2] ^ sp22[5] ^ sp22[7] ^ 1'b1;
assign aesd_noshf[81] = sp22[0] ^ sp22[3] ^ sp22[6] ^ 1'b0;
assign aesd_noshf[82] = sp22[1] ^ sp22[4] ^ sp22[7] ^ 1'b1;
assign aesd_noshf[83] = sp22[0] ^ sp22[2] ^ sp22[5] ^ 1'b0;
assign aesd_noshf[84] = sp22[1] ^ sp22[3] ^ sp22[6] ^ 1'b0;
assign aesd_noshf[85] = sp22[2] ^ sp22[4] ^ sp22[7] ^ 1'b0;
assign aesd_noshf[86] = sp22[0] ^ sp22[3] ^ sp22[5] ^ 1'b0;
assign aesd_noshf[87] = sp22[1] ^ sp22[4] ^ sp22[6] ^ 1'b0;
assign aesd_noshf[112] = sp23[2] ^ sp23[5] ^ sp23[7] ^ 1'b1;
assign aesd_noshf[113] = sp23[0] ^ sp23[3] ^ sp23[6] ^ 1'b0;
assign aesd_noshf[114] = sp23[1] ^ sp23[4] ^ sp23[7] ^ 1'b1;
assign aesd_noshf[115] = sp23[0] ^ sp23[2] ^ sp23[5] ^ 1'b0;
assign aesd_noshf[116] = sp23[1] ^ sp23[3] ^ sp23[6] ^ 1'b0;
assign aesd_noshf[117] = sp23[2] ^ sp23[4] ^ sp23[7] ^ 1'b0;
assign aesd_noshf[118] = sp23[0] ^ sp23[3] ^ sp23[5] ^ 1'b0;
assign aesd_noshf[119] = sp23[1] ^ sp23[4] ^ sp23[6] ^ 1'b0;
assign aesd_noshf[24] = sp30[2] ^ sp30[5] ^ sp30[7] ^ 1'b1;
assign aesd_noshf[25] = sp30[0] ^ sp30[3] ^ sp30[6] ^ 1'b0;
assign aesd_noshf[26] = sp30[1] ^ sp30[4] ^ sp30[7] ^ 1'b1;
assign aesd_noshf[27] = sp30[0] ^ sp30[2] ^ sp30[5] ^ 1'b0;
assign aesd_noshf[28] = sp30[1] ^ sp30[3] ^ sp30[6] ^ 1'b0;
assign aesd_noshf[29] = sp30[2] ^ sp30[4] ^ sp30[7] ^ 1'b0;
assign aesd_noshf[30] = sp30[0] ^ sp30[3] ^ sp30[5] ^ 1'b0;
assign aesd_noshf[31] = sp30[1] ^ sp30[4] ^ sp30[6] ^ 1'b0;
assign aesd_noshf[56] = sp31[2] ^ sp31[5] ^ sp31[7] ^ 1'b1;
assign aesd_noshf[57] = sp31[0] ^ sp31[3] ^ sp31[6] ^ 1'b0;
assign aesd_noshf[58] = sp31[1] ^ sp31[4] ^ sp31[7] ^ 1'b1;
assign aesd_noshf[59] = sp31[0] ^ sp31[2] ^ sp31[5] ^ 1'b0;
assign aesd_noshf[60] = sp31[1] ^ sp31[3] ^ sp31[6] ^ 1'b0;
assign aesd_noshf[61] = sp31[2] ^ sp31[4] ^ sp31[7] ^ 1'b0;
assign aesd_noshf[62] = sp31[0] ^ sp31[3] ^ sp31[5] ^ 1'b0;
assign aesd_noshf[63] = sp31[1] ^ sp31[4] ^ sp31[6] ^ 1'b0;
assign aesd_noshf[88] = sp32[2] ^ sp32[5] ^ sp32[7] ^ 1'b1;
assign aesd_noshf[89] = sp32[0] ^ sp32[3] ^ sp32[6] ^ 1'b0;
assign aesd_noshf[90] = sp32[1] ^ sp32[4] ^ sp32[7] ^ 1'b1;
assign aesd_noshf[91] = sp32[0] ^ sp32[2] ^ sp32[5] ^ 1'b0;
assign aesd_noshf[92] = sp32[1] ^ sp32[3] ^ sp32[6] ^ 1'b0;
assign aesd_noshf[93] = sp32[2] ^ sp32[4] ^ sp32[7] ^ 1'b0;
assign aesd_noshf[94] = sp32[0] ^ sp32[3] ^ sp32[5] ^ 1'b0;
assign aesd_noshf[95] = sp32[1] ^ sp32[4] ^ sp32[6] ^ 1'b0;
assign aesd_noshf[120] = sp33[2] ^ sp33[5] ^ sp33[7] ^ 1'b1;
assign aesd_noshf[121] = sp33[0] ^ sp33[3] ^ sp33[6] ^ 1'b0;
assign aesd_noshf[122] = sp33[1] ^ sp33[4] ^ sp33[7] ^ 1'b1;
assign aesd_noshf[123] = sp33[0] ^ sp33[2] ^ sp33[5] ^ 1'b0;
assign aesd_noshf[124] = sp33[1] ^ sp33[3] ^ sp33[6] ^ 1'b0;
assign aesd_noshf[125] = sp33[2] ^ sp33[4] ^ sp33[7] ^ 1'b0;
assign aesd_noshf[126] = sp33[0] ^ sp33[3] ^ sp33[5] ^ 1'b0;
assign aesd_noshf[127] = sp33[1] ^ sp33[4] ^ sp33[6] ^ 1'b0;
assign aesd_shf[15] = ~aesd_noshf[127];
assign aesd_shf[14] = ~aesd_noshf[119];
assign aesd_shf[13] = ~aesd_noshf[111];
assign aesd_shf[12] = ~aesd_noshf[103];
assign aesd_shf[11] = ~aesd_noshf[ 95];
assign aesd_shf[10] = ~aesd_noshf[ 87];
assign aesd_shf[ 9] = ~aesd_noshf[ 79];
assign aesd_shf[ 8] = ~aesd_noshf[ 71];
assign aesd_shf[ 7] = ~aesd_noshf[ 63];
assign aesd_shf[ 6] = ~aesd_noshf[ 55];
assign aesd_shf[ 5] = ~aesd_noshf[ 47];
assign aesd_shf[ 4] = ~aesd_noshf[ 39];
assign aesd_shf[ 3] = ~aesd_noshf[ 31];
assign aesd_shf[ 2] = ~aesd_noshf[ 23];
assign aesd_shf[ 1] = ~aesd_noshf[ 15];
assign aesd_shf[ 0] = ~aesd_noshf[ 7];
assign aesd_out[127:120] = {8{ aesd_shf[15]}} & {aesd_noshf[126:120], 1'b0} |
{8{~aesd_shf[15]}} & aesd_noshf[127:120];
assign aesd_out[119:112] = {8{ aesd_shf[14]}} & {aesd_noshf[118:112], 1'b0} |
{8{~aesd_shf[14]}} & aesd_noshf[119:112];
assign aesd_out[111:104] = {8{ aesd_shf[13]}} & {aesd_noshf[110:104], 1'b0} |
{8{~aesd_shf[13]}} & aesd_noshf[111:104];
assign aesd_out[103: 96] = {8{ aesd_shf[12]}} & {aesd_noshf[102: 96], 1'b0} |
{8{~aesd_shf[12]}} & aesd_noshf[103: 96];
assign aesd_out[ 95: 88] = {8{ aesd_shf[11]}} & {aesd_noshf[ 94: 88], 1'b0} |
{8{~aesd_shf[11]}} & aesd_noshf[ 95: 88];
assign aesd_out[ 87: 80] = {8{ aesd_shf[10]}} & {aesd_noshf[ 86: 80], 1'b0} |
{8{~aesd_shf[10]}} & aesd_noshf[ 87: 80];
assign aesd_out[ 79: 72] = {8{ aesd_shf[ 9]}} & {aesd_noshf[ 78: 72], 1'b0} |
{8{~aesd_shf[ 9]}} & aesd_noshf[ 79: 72];
assign aesd_out[ 71: 64] = {8{ aesd_shf[ 8]}} & {aesd_noshf[ 70: 64], 1'b0} |
{8{~aesd_shf[ 8]}} & aesd_noshf[ 71: 64];
assign aesd_out[ 63: 56] = {8{ aesd_shf[ 7]}} & {aesd_noshf[ 62: 56], 1'b0} |
{8{~aesd_shf[ 7]}} & aesd_noshf[ 63: 56];
assign aesd_out[ 55: 48] = {8{ aesd_shf[ 6]}} & {aesd_noshf[ 54: 48], 1'b0} |
{8{~aesd_shf[ 6]}} & aesd_noshf[ 55: 48];
assign aesd_out[ 47: 40] = {8{ aesd_shf[ 5]}} & {aesd_noshf[ 46: 40], 1'b0} |
{8{~aesd_shf[ 5]}} & aesd_noshf[ 47: 40];
assign aesd_out[ 39: 32] = {8{ aesd_shf[ 4]}} & {aesd_noshf[ 38: 32], 1'b0} |
{8{~aesd_shf[ 4]}} & aesd_noshf[ 39: 32];
assign aesd_out[ 31: 24] = {8{ aesd_shf[ 3]}} & {aesd_noshf[ 30: 24], 1'b0} |
{8{~aesd_shf[ 3]}} & aesd_noshf[ 31: 24];
assign aesd_out[ 23: 16] = {8{ aesd_shf[ 2]}} & {aesd_noshf[ 22: 16], 1'b0} |
{8{~aesd_shf[ 2]}} & aesd_noshf[ 23: 16];
assign aesd_out[ 15: 8] = {8{ aesd_shf[ 1]}} & {aesd_noshf[ 14: 8], 1'b0} |
{8{~aesd_shf[ 1]}} & aesd_noshf[ 15: 8];
assign aesd_out[ 7: 0] = {8{ aesd_shf[ 0]}} & {aesd_noshf[ 6: 0], 1'b0} |
{8{~aesd_shf[ 0]}} & aesd_noshf[ 7: 0];
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

158
Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aese1.sv
View File

@ -1,158 +0,0 @@
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_aese1
(
input wire [127:0] q,
output wire [127:0] aese_out,
output wire [15:0] aese_shf
);
wire [127:0] aese_noshf;
wire [7:0] s00;
wire [7:0] s01;
wire [7:0] s02;
wire [7:0] s03;
wire [7:0] s10;
wire [7:0] s11;
wire [7:0] s12;
wire [7:0] s13;
wire [7:0] s20;
wire [7:0] s21;
wire [7:0] s22;
wire [7:0] s23;
wire [7:0] s30;
wire [7:0] s31;
wire [7:0] s32;
wire [7:0] s33;
assign s33[7:0] = q[127:120];
assign s23[7:0] = q[119:112];
assign s13[7:0] = q[111:104];
assign s03[7:0] = q[103:96];
assign s32[7:0] = q[95:88];
assign s22[7:0] = q[87:80];
assign s12[7:0] = q[79:72];
assign s02[7:0] = q[71:64];
assign s31[7:0] = q[63:56];
assign s21[7:0] = q[55:48];
assign s11[7:0] = q[47:40];
assign s01[7:0] = q[39:32];
assign s30[7:0] = q[31:24];
assign s20[7:0] = q[23:16];
assign s10[7:0] = q[15:8];
assign s00[7:0] = q[7:0];
assign aese_noshf[7:0] = s00[7:0];
assign aese_noshf[39:32] = s01[7:0];
assign aese_noshf[71:64] = s02[7:0];
assign aese_noshf[103:96] = s03[7:0];
assign aese_noshf[15:8] = s11[7:0];
assign aese_noshf[47:40] = s12[7:0];
assign aese_noshf[79:72] = s13[7:0];
assign aese_noshf[111:104] = s10[7:0];
assign aese_noshf[23:16] = s22[7:0];
assign aese_noshf[55:48] = s23[7:0];
assign aese_noshf[87:80] = s20[7:0];
assign aese_noshf[119:112] = s21[7:0];
assign aese_noshf[31:24] = s33[7:0];
assign aese_noshf[63:56] = s30[7:0];
assign aese_noshf[95:88] = s31[7:0];
assign aese_noshf[127:120] = s32[7:0];
assign aese_shf[15] = ~aese_noshf[127];
assign aese_shf[14] = ~aese_noshf[119];
assign aese_shf[13] = ~aese_noshf[111];
assign aese_shf[12] = ~aese_noshf[103];
assign aese_shf[11] = ~aese_noshf[ 95];
assign aese_shf[10] = ~aese_noshf[ 87];
assign aese_shf[ 9] = ~aese_noshf[ 79];
assign aese_shf[ 8] = ~aese_noshf[ 71];
assign aese_shf[ 7] = ~aese_noshf[ 63];
assign aese_shf[ 6] = ~aese_noshf[ 55];
assign aese_shf[ 5] = ~aese_noshf[ 47];
assign aese_shf[ 4] = ~aese_noshf[ 39];
assign aese_shf[ 3] = ~aese_noshf[ 31];
assign aese_shf[ 2] = ~aese_noshf[ 23];
assign aese_shf[ 1] = ~aese_noshf[ 15];
assign aese_shf[ 0] = ~aese_noshf[ 7];
assign aese_out[127:120] = {8{ aese_shf[15]}} & {aese_noshf[126:120], 1'b0} |
{8{~aese_shf[15]}} & aese_noshf[127:120];
assign aese_out[119:112] = {8{ aese_shf[14]}} & {aese_noshf[118:112], 1'b0} |
{8{~aese_shf[14]}} & aese_noshf[119:112];
assign aese_out[111:104] = {8{ aese_shf[13]}} & {aese_noshf[110:104], 1'b0} |
{8{~aese_shf[13]}} & aese_noshf[111:104];
assign aese_out[103: 96] = {8{ aese_shf[12]}} & {aese_noshf[102: 96], 1'b0} |
{8{~aese_shf[12]}} & aese_noshf[103: 96];
assign aese_out[ 95: 88] = {8{ aese_shf[11]}} & {aese_noshf[ 94: 88], 1'b0} |
{8{~aese_shf[11]}} & aese_noshf[ 95: 88];
assign aese_out[ 87: 80] = {8{ aese_shf[10]}} & {aese_noshf[ 86: 80], 1'b0} |
{8{~aese_shf[10]}} & aese_noshf[ 87: 80];
assign aese_out[ 79: 72] = {8{ aese_shf[ 9]}} & {aese_noshf[ 78: 72], 1'b0} |
{8{~aese_shf[ 9]}} & aese_noshf[ 79: 72];
assign aese_out[ 71: 64] = {8{ aese_shf[ 8]}} & {aese_noshf[ 70: 64], 1'b0} |
{8{~aese_shf[ 8]}} & aese_noshf[ 71: 64];
assign aese_out[ 63: 56] = {8{ aese_shf[ 7]}} & {aese_noshf[ 62: 56], 1'b0} |
{8{~aese_shf[ 7]}} & aese_noshf[ 63: 56];
assign aese_out[ 55: 48] = {8{ aese_shf[ 6]}} & {aese_noshf[ 54: 48], 1'b0} |
{8{~aese_shf[ 6]}} & aese_noshf[ 55: 48];
assign aese_out[ 47: 40] = {8{ aese_shf[ 5]}} & {aese_noshf[ 46: 40], 1'b0} |
{8{~aese_shf[ 5]}} & aese_noshf[ 47: 40];
assign aese_out[ 39: 32] = {8{ aese_shf[ 4]}} & {aese_noshf[ 38: 32], 1'b0} |
{8{~aese_shf[ 4]}} & aese_noshf[ 39: 32];
assign aese_out[ 31: 24] = {8{ aese_shf[ 3]}} & {aese_noshf[ 30: 24], 1'b0} |
{8{~aese_shf[ 3]}} & aese_noshf[ 31: 24];
assign aese_out[ 23: 16] = {8{ aese_shf[ 2]}} & {aese_noshf[ 22: 16], 1'b0} |
{8{~aese_shf[ 2]}} & aese_noshf[ 23: 16];
assign aese_out[ 15: 8] = {8{ aese_shf[ 1]}} & {aese_noshf[ 14: 8], 1'b0} |
{8{~aese_shf[ 1]}} & aese_noshf[ 15: 8];
assign aese_out[ 7: 0] = {8{ aese_shf[ 0]}} & {aese_noshf[ 6: 0], 1'b0} |
{8{~aese_shf[ 0]}} & aese_noshf[ 7: 0];
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

610
Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aesed2.sv
View File

@ -1,610 +0,0 @@
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_aesed2
(
input wire clk,
input wire reset,
input wire ival_v1_q,
input wire [127:0] aes_din_v1,
input wire [15:0] aes_shf_v1,
output wire [127:0] aesd_out,
output wire [127:0] aese_out,
output wire [127:0] aesemc_out,
output wire [127:0] aesdimc_out
);
wire [127:0] aesimc_in;
wire [127:0] aesmc_in;
wire [7:0] b00_corr_v1;
wire [7:0] b00_redn_v1;
reg [7:0] b00_redn_v2_q;
wire [7:0] b00_shf_v1;
wire [7:0] b00_v1;
wire [7:0] b01_corr_v1;
wire [7:0] b01_redn_v1;
reg [7:0] b01_redn_v2_q;
wire [7:0] b01_shf_v1;
wire [7:0] b01_v1;
wire [7:0] b02_corr_v1;
wire [7:0] b02_redn_v1;
reg [7:0] b02_redn_v2_q;
wire [7:0] b02_shf_v1;
wire [7:0] b02_v1;
wire [7:0] b03_corr_v1;
wire [7:0] b03_redn_v1;
reg [7:0] b03_redn_v2_q;
wire [7:0] b03_shf_v1;
wire [7:0] b03_v1;
wire [7:0] b10_corr_v1;
wire [7:0] b10_redn_v1;
reg [7:0] b10_redn_v2_q;
wire [7:0] b10_shf_v1;
wire [7:0] b10_v1;
wire [7:0] b11_corr_v1;
wire [7:0] b11_redn_v1;
reg [7:0] b11_redn_v2_q;
wire [7:0] b11_shf_v1;
wire [7:0] b11_v1;
wire [7:0] b12_corr_v1;
wire [7:0] b12_redn_v1;
reg [7:0] b12_redn_v2_q;
wire [7:0] b12_shf_v1;
wire [7:0] b12_v1;
wire [7:0] b13_corr_v1;
wire [7:0] b13_redn_v1;
reg [7:0] b13_redn_v2_q;
wire [7:0] b13_shf_v1;
wire [7:0] b13_v1;
wire [7:0] b20_corr_v1;
wire [7:0] b20_redn_v1;
reg [7:0] b20_redn_v2_q;
wire [7:0] b20_shf_v1;
wire [7:0] b20_v1;
wire [7:0] b21_corr_v1;
wire [7:0] b21_redn_v1;
reg [7:0] b21_redn_v2_q;
wire [7:0] b21_shf_v1;
wire [7:0] b21_v1;
wire [7:0] b22_corr_v1;
wire [7:0] b22_redn_v1;
reg [7:0] b22_redn_v2_q;
wire [7:0] b22_shf_v1;
wire [7:0] b22_v1;
wire [7:0] b23_corr_v1;
wire [7:0] b23_redn_v1;
reg [7:0] b23_redn_v2_q;
wire [7:0] b23_shf_v1;
wire [7:0] b23_v1;
wire [7:0] b30_corr_v1;
wire [7:0] b30_redn_v1;
reg [7:0] b30_redn_v2_q;
wire [7:0] b30_shf_v1;
wire [7:0] b30_v1;
wire [7:0] b31_corr_v1;
wire [7:0] b31_redn_v1;
reg [7:0] b31_redn_v2_q;
wire [7:0] b31_shf_v1;
wire [7:0] b31_v1;
wire [7:0] b32_corr_v1;
wire [7:0] b32_redn_v1;
reg [7:0] b32_redn_v2_q;
wire [7:0] b32_shf_v1;
wire [7:0] b32_v1;
wire [7:0] b33_corr_v1;
wire [7:0] b33_redn_v1;
reg [7:0] b33_redn_v2_q;
wire [7:0] b33_shf_v1;
wire [7:0] b33_v1;
assign b33_v1[7:0] = aes_din_v1[127:120];
assign b23_v1[7:0] = aes_din_v1[119:112];
assign b13_v1[7:0] = aes_din_v1[111:104];
assign b03_v1[7:0] = aes_din_v1[103:96];
assign b32_v1[7:0] = aes_din_v1[95:88];
assign b22_v1[7:0] = aes_din_v1[87:80];
assign b12_v1[7:0] = aes_din_v1[79:72];
assign b02_v1[7:0] = aes_din_v1[71:64];
assign b31_v1[7:0] = aes_din_v1[63:56];
assign b21_v1[7:0] = aes_din_v1[55:48];
assign b11_v1[7:0] = aes_din_v1[47:40];
assign b01_v1[7:0] = aes_din_v1[39:32];
assign b30_v1[7:0] = aes_din_v1[31:24];
assign b20_v1[7:0] = aes_din_v1[23:16];
assign b10_v1[7:0] = aes_din_v1[15:8];
assign b00_v1[7:0] = aes_din_v1[7:0];
assign b33_shf_v1[7:0] = {8{ aes_shf_v1[15]}} & {b33_v1[6:0], 1'b0} |
{8{~aes_shf_v1[15]}} & {b33_v1[7:0]};
assign b23_shf_v1[7:0] = {8{ aes_shf_v1[14]}} & {b23_v1[6:0], 1'b0} |
{8{~aes_shf_v1[14]}} & {b23_v1[7:0]};
assign b13_shf_v1[7:0] = {8{ aes_shf_v1[13]}} & {b13_v1[6:0], 1'b0} |
{8{~aes_shf_v1[13]}} & {b13_v1[7:0]};
assign b03_shf_v1[7:0] = {8{ aes_shf_v1[12]}} & {b03_v1[6:0], 1'b0} |
{8{~aes_shf_v1[12]}} & {b03_v1[7:0]};
assign b32_shf_v1[7:0] = {8{ aes_shf_v1[11]}} & {b32_v1[6:0], 1'b0} |
{8{~aes_shf_v1[11]}} & {b32_v1[7:0]};
assign b22_shf_v1[7:0] = {8{ aes_shf_v1[10]}} & {b22_v1[6:0], 1'b0} |
{8{~aes_shf_v1[10]}} & {b22_v1[7:0]};
assign b12_shf_v1[7:0] = {8{ aes_shf_v1[ 9]}} & {b12_v1[6:0], 1'b0} |
{8{~aes_shf_v1[ 9]}} & {b12_v1[7:0]};
assign b02_shf_v1[7:0] = {8{ aes_shf_v1[ 8]}} & {b02_v1[6:0], 1'b0} |
{8{~aes_shf_v1[ 8]}} & {b02_v1[7:0]};
assign b31_shf_v1[7:0] = {8{ aes_shf_v1[ 7]}} & {b31_v1[6:0], 1'b0} |
{8{~aes_shf_v1[ 7]}} & {b31_v1[7:0]};
assign b21_shf_v1[7:0] = {8{ aes_shf_v1[ 6]}} & {b21_v1[6:0], 1'b0} |
{8{~aes_shf_v1[ 6]}} & {b21_v1[7:0]};
assign b11_shf_v1[7:0] = {8{ aes_shf_v1[ 5]}} & {b11_v1[6:0], 1'b0} |
{8{~aes_shf_v1[ 5]}} & {b11_v1[7:0]};
assign b01_shf_v1[7:0] = {8{ aes_shf_v1[ 4]}} & {b01_v1[6:0], 1'b0} |
{8{~aes_shf_v1[ 4]}} & {b01_v1[7:0]};
assign b30_shf_v1[7:0] = {8{ aes_shf_v1[ 3]}} & {b30_v1[6:0], 1'b0} |
{8{~aes_shf_v1[ 3]}} & {b30_v1[7:0]};
assign b20_shf_v1[7:0] = {8{ aes_shf_v1[ 2]}} & {b20_v1[6:0], 1'b0} |
{8{~aes_shf_v1[ 2]}} & {b20_v1[7:0]};
assign b10_shf_v1[7:0] = {8{ aes_shf_v1[ 1]}} & {b10_v1[6:0], 1'b0} |
{8{~aes_shf_v1[ 1]}} & {b10_v1[7:0]};
assign b00_shf_v1[7:0] = {8{ aes_shf_v1[ 0]}} & {b00_v1[6:0], 1'b0} |
{8{~aes_shf_v1[ 0]}} & {b00_v1[7:0]};
assign b33_corr_v1[7:0] = {8{aes_shf_v1[15]}} & {8{b33_v1[7]}} & 8'h1b;
assign b23_corr_v1[7:0] = {8{aes_shf_v1[14]}} & {8{b23_v1[7]}} & 8'h1b;
assign b13_corr_v1[7:0] = {8{aes_shf_v1[13]}} & {8{b13_v1[7]}} & 8'h1b;
assign b03_corr_v1[7:0] = {8{aes_shf_v1[12]}} & {8{b03_v1[7]}} & 8'h1b;
assign b32_corr_v1[7:0] = {8{aes_shf_v1[11]}} & {8{b32_v1[7]}} & 8'h1b;
assign b22_corr_v1[7:0] = {8{aes_shf_v1[10]}} & {8{b22_v1[7]}} & 8'h1b;
assign b12_corr_v1[7:0] = {8{aes_shf_v1[ 9]}} & {8{b12_v1[7]}} & 8'h1b;
assign b02_corr_v1[7:0] = {8{aes_shf_v1[ 8]}} & {8{b02_v1[7]}} & 8'h1b;
assign b31_corr_v1[7:0] = {8{aes_shf_v1[ 7]}} & {8{b31_v1[7]}} & 8'h1b;
assign b21_corr_v1[7:0] = {8{aes_shf_v1[ 6]}} & {8{b21_v1[7]}} & 8'h1b;
assign b11_corr_v1[7:0] = {8{aes_shf_v1[ 5]}} & {8{b11_v1[7]}} & 8'h1b;
assign b01_corr_v1[7:0] = {8{aes_shf_v1[ 4]}} & {8{b01_v1[7]}} & 8'h1b;
assign b30_corr_v1[7:0] = {8{aes_shf_v1[ 3]}} & {8{b30_v1[7]}} & 8'h1b;
assign b20_corr_v1[7:0] = {8{aes_shf_v1[ 2]}} & {8{b20_v1[7]}} & 8'h1b;
assign b10_corr_v1[7:0] = {8{aes_shf_v1[ 1]}} & {8{b10_v1[7]}} & 8'h1b;
assign b00_corr_v1[7:0] = {8{aes_shf_v1[ 0]}} & {8{b00_v1[7]}} & 8'h1b;
assign b33_redn_v1[7:0] = b33_corr_v1[7:0] ^ b33_shf_v1[7:0];
assign b23_redn_v1[7:0] = b23_corr_v1[7:0] ^ b23_shf_v1[7:0];
assign b13_redn_v1[7:0] = b13_corr_v1[7:0] ^ b13_shf_v1[7:0];
assign b03_redn_v1[7:0] = b03_corr_v1[7:0] ^ b03_shf_v1[7:0];
assign b32_redn_v1[7:0] = b32_corr_v1[7:0] ^ b32_shf_v1[7:0];
assign b22_redn_v1[7:0] = b22_corr_v1[7:0] ^ b22_shf_v1[7:0];
assign b12_redn_v1[7:0] = b12_corr_v1[7:0] ^ b12_shf_v1[7:0];
assign b02_redn_v1[7:0] = b02_corr_v1[7:0] ^ b02_shf_v1[7:0];
assign b31_redn_v1[7:0] = b31_corr_v1[7:0] ^ b31_shf_v1[7:0];
assign b21_redn_v1[7:0] = b21_corr_v1[7:0] ^ b21_shf_v1[7:0];
assign b11_redn_v1[7:0] = b11_corr_v1[7:0] ^ b11_shf_v1[7:0];
assign b01_redn_v1[7:0] = b01_corr_v1[7:0] ^ b01_shf_v1[7:0];
assign b30_redn_v1[7:0] = b30_corr_v1[7:0] ^ b30_shf_v1[7:0];
assign b20_redn_v1[7:0] = b20_corr_v1[7:0] ^ b20_shf_v1[7:0];
assign b10_redn_v1[7:0] = b10_corr_v1[7:0] ^ b10_shf_v1[7:0];
assign b00_redn_v1[7:0] = b00_corr_v1[7:0] ^ b00_shf_v1[7:0];
always_ff @(posedge clk or posedge reset)
begin: u_b33_redn_v2_q_7_0_grp
if (reset == 1'b1) begin
b33_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b23_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b13_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b03_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b32_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b22_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b12_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b02_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b31_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b21_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b11_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b01_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b30_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b20_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b10_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b00_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
end
`ifdef HERCULESAE_XPROP_FLOP
else if (reset == 1'b0 && ival_v1_q == 1'b1) begin
b33_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b33_redn_v1[7:0];
b23_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b23_redn_v1[7:0];
b13_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b13_redn_v1[7:0];
b03_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b03_redn_v1[7:0];
b32_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b32_redn_v1[7:0];
b22_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b22_redn_v1[7:0];
b12_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b12_redn_v1[7:0];
b02_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b02_redn_v1[7:0];
b31_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b31_redn_v1[7:0];
b21_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b21_redn_v1[7:0];
b11_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b11_redn_v1[7:0];
b01_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b01_redn_v1[7:0];
b30_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b30_redn_v1[7:0];
b20_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b20_redn_v1[7:0];
b10_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b10_redn_v1[7:0];
b00_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b00_redn_v1[7:0];
end
else if (reset == 1'b0 && ival_v1_q == 1'b0)
begin
end
else begin
b33_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b23_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b13_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b03_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b32_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b22_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b12_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b02_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b31_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b21_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b11_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b01_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b30_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b20_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b10_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b00_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
end
`else
else if (ival_v1_q == 1'b1) begin
b33_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b33_redn_v1[7:0];
b23_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b23_redn_v1[7:0];
b13_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b13_redn_v1[7:0];
b03_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b03_redn_v1[7:0];
b32_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b32_redn_v1[7:0];
b22_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b22_redn_v1[7:0];
b12_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b12_redn_v1[7:0];
b02_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b02_redn_v1[7:0];
b31_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b31_redn_v1[7:0];
b21_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b21_redn_v1[7:0];
b11_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b11_redn_v1[7:0];
b01_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b01_redn_v1[7:0];
b30_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b30_redn_v1[7:0];
b20_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b20_redn_v1[7:0];
b10_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b10_redn_v1[7:0];
b00_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b00_redn_v1[7:0];
end
`endif
end
assign aesd_out[127:120] = b33_redn_v2_q[7:0];
assign aesd_out[119:112] = b23_redn_v2_q[7:0];
assign aesd_out[111:104] = b13_redn_v2_q[7:0];
assign aesd_out[103:96] = b03_redn_v2_q[7:0];
assign aesd_out[95:88] = b32_redn_v2_q[7:0];
assign aesd_out[87:80] = b22_redn_v2_q[7:0];
assign aesd_out[79:72] = b12_redn_v2_q[7:0];
assign aesd_out[71:64] = b02_redn_v2_q[7:0];
assign aesd_out[63:56] = b31_redn_v2_q[7:0];
assign aesd_out[55:48] = b21_redn_v2_q[7:0];
assign aesd_out[47:40] = b11_redn_v2_q[7:0];
assign aesd_out[39:32] = b01_redn_v2_q[7:0];
assign aesd_out[31:24] = b30_redn_v2_q[7:0];
assign aesd_out[23:16] = b20_redn_v2_q[7:0];
assign aesd_out[15:8] = b10_redn_v2_q[7:0];
assign aesd_out[7:0] = b00_redn_v2_q[7:0];
assign aesimc_in[127:0] = aesd_out[127:0];
herculesae_vx_aesimc u_aesimc(
.d_in (aesimc_in[127:0]),
.imc (aesdimc_out[127:0])
);
assign aese_out[0] = b00_redn_v2_q[0] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b1;
assign aese_out[1] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b1;
assign aese_out[2] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b0;
assign aese_out[3] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[7] ^ 1'b0;
assign aese_out[4] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ 1'b0;
assign aese_out[5] = b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ 1'b1;
assign aese_out[6] = b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ 1'b1;
assign aese_out[7] = b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b0;
assign aese_out[8] = b10_redn_v2_q[0] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b1;
assign aese_out[9] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b1;
assign aese_out[10] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b0;
assign aese_out[11] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[7] ^ 1'b0;
assign aese_out[12] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ 1'b0;
assign aese_out[13] = b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ 1'b1;
assign aese_out[14] = b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ 1'b1;
assign aese_out[15] = b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b0;
assign aese_out[16] = b20_redn_v2_q[0] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b1;
assign aese_out[17] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b1;
assign aese_out[18] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b0;
assign aese_out[19] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[7] ^ 1'b0;
assign aese_out[20] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ 1'b0;
assign aese_out[21] = b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ 1'b1;
assign aese_out[22] = b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ 1'b1;
assign aese_out[23] = b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b0;
assign aese_out[24] = b30_redn_v2_q[0] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b1;
assign aese_out[25] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b1;
assign aese_out[26] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b0;
assign aese_out[27] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[7] ^ 1'b0;
assign aese_out[28] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ 1'b0;
assign aese_out[29] = b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ 1'b1;
assign aese_out[30] = b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ 1'b1;
assign aese_out[31] = b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b0;
assign aese_out[32] = b01_redn_v2_q[0] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b1;
assign aese_out[33] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b1;
assign aese_out[34] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b0;
assign aese_out[35] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[7] ^ 1'b0;
assign aese_out[36] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ 1'b0;
assign aese_out[37] = b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ 1'b1;
assign aese_out[38] = b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ 1'b1;
assign aese_out[39] = b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b0;
assign aese_out[40] = b11_redn_v2_q[0] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b1;
assign aese_out[41] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b1;
assign aese_out[42] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b0;
assign aese_out[43] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[7] ^ 1'b0;
assign aese_out[44] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ 1'b0;
assign aese_out[45] = b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ 1'b1;
assign aese_out[46] = b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ 1'b1;
assign aese_out[47] = b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b0;
assign aese_out[48] = b21_redn_v2_q[0] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b1;
assign aese_out[49] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b1;
assign aese_out[50] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b0;
assign aese_out[51] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[7] ^ 1'b0;
assign aese_out[52] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ 1'b0;
assign aese_out[53] = b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ 1'b1;
assign aese_out[54] = b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ 1'b1;
assign aese_out[55] = b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b0;
assign aese_out[56] = b31_redn_v2_q[0] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b1;
assign aese_out[57] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b1;
assign aese_out[58] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b0;
assign aese_out[59] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[7] ^ 1'b0;
assign aese_out[60] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ 1'b0;
assign aese_out[61] = b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ 1'b1;
assign aese_out[62] = b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ 1'b1;
assign aese_out[63] = b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b0;
assign aese_out[64] = b02_redn_v2_q[0] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b1;
assign aese_out[65] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b1;
assign aese_out[66] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b0;
assign aese_out[67] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[7] ^ 1'b0;
assign aese_out[68] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ 1'b0;
assign aese_out[69] = b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ 1'b1;
assign aese_out[70] = b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ 1'b1;
assign aese_out[71] = b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b0;
assign aese_out[72] = b12_redn_v2_q[0] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b1;
assign aese_out[73] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b1;
assign aese_out[74] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b0;
assign aese_out[75] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[7] ^ 1'b0;
assign aese_out[76] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ 1'b0;
assign aese_out[77] = b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ 1'b1;
assign aese_out[78] = b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ 1'b1;
assign aese_out[79] = b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b0;
assign aese_out[80] = b22_redn_v2_q[0] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b1;
assign aese_out[81] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b1;
assign aese_out[82] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b0;
assign aese_out[83] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[7] ^ 1'b0;
assign aese_out[84] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ 1'b0;
assign aese_out[85] = b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ 1'b1;
assign aese_out[86] = b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ 1'b1;
assign aese_out[87] = b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b0;
assign aese_out[88] = b32_redn_v2_q[0] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b1;
assign aese_out[89] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b1;
assign aese_out[90] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b0;
assign aese_out[91] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[7] ^ 1'b0;
assign aese_out[92] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ 1'b0;
assign aese_out[93] = b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ 1'b1;
assign aese_out[94] = b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ 1'b1;
assign aese_out[95] = b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b0;
assign aese_out[96] = b03_redn_v2_q[0] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b1;
assign aese_out[97] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b1;
assign aese_out[98] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b0;
assign aese_out[99] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[7] ^ 1'b0;
assign aese_out[100] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ 1'b0;
assign aese_out[101] = b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ 1'b1;
assign aese_out[102] = b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ 1'b1;
assign aese_out[103] = b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b0;
assign aese_out[104] = b13_redn_v2_q[0] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b1;
assign aese_out[105] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b1;
assign aese_out[106] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b0;
assign aese_out[107] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[7] ^ 1'b0;
assign aese_out[108] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ 1'b0;
assign aese_out[109] = b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ 1'b1;
assign aese_out[110] = b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ 1'b1;
assign aese_out[111] = b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b0;
assign aese_out[112] = b23_redn_v2_q[0] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b1;
assign aese_out[113] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b1;
assign aese_out[114] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b0;
assign aese_out[115] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[7] ^ 1'b0;
assign aese_out[116] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ 1'b0;
assign aese_out[117] = b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ 1'b1;
assign aese_out[118] = b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ 1'b1;
assign aese_out[119] = b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b0;
assign aese_out[120] = b33_redn_v2_q[0] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b1;
assign aese_out[121] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b1;
assign aese_out[122] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b0;
assign aese_out[123] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[7] ^ 1'b0;
assign aese_out[124] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ 1'b0;
assign aese_out[125] = b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ 1'b1;
assign aese_out[126] = b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ 1'b1;
assign aese_out[127] = b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[0] = b00_redn_v2_q[0] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[1] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[2] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[3] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[4] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[5] = b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[6] = b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[7] = b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[8] = b10_redn_v2_q[0] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[9] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[10] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[11] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[12] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[13] = b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[14] = b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[15] = b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[16] = b20_redn_v2_q[0] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[17] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[18] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[19] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[20] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[21] = b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[22] = b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[23] = b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[24] = b30_redn_v2_q[0] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[25] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[26] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[27] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[28] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[29] = b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[30] = b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[31] = b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[32] = b01_redn_v2_q[0] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[33] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[34] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[35] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[36] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[37] = b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[38] = b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[39] = b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[40] = b11_redn_v2_q[0] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[41] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[42] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[43] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[44] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[45] = b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[46] = b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[47] = b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[48] = b21_redn_v2_q[0] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[49] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[50] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[51] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[52] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[53] = b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[54] = b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[55] = b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[56] = b31_redn_v2_q[0] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[57] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[58] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[59] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[60] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[61] = b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[62] = b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[63] = b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[64] = b02_redn_v2_q[0] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[65] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[66] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[67] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[68] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[69] = b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[70] = b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[71] = b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[72] = b12_redn_v2_q[0] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[73] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[74] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[75] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[76] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[77] = b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[78] = b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[79] = b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[80] = b22_redn_v2_q[0] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[81] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[82] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[83] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[84] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[85] = b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[86] = b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[87] = b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[88] = b32_redn_v2_q[0] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[89] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[90] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[91] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[92] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[93] = b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[94] = b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[95] = b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[96] = b03_redn_v2_q[0] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[97] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[98] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[99] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[100] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[101] = b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[102] = b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[103] = b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[104] = b13_redn_v2_q[0] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[105] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[106] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[107] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[108] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[109] = b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[110] = b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[111] = b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[112] = b23_redn_v2_q[0] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[113] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[114] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[115] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[116] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[117] = b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[118] = b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[119] = b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[120] = b33_redn_v2_q[0] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[121] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[122] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[123] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[124] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[125] = b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[126] = b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[127] = b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b0;
herculesae_vx_aesmc u_aesmc(
.d_in (aesmc_in[127:0]),
.mc (aesemc_out[127:0])
);
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

93
Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aesed2_lut.sv
View File

@ -1,93 +0,0 @@
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_aesed2_lut
(
input wire [127:0] lut_in,
output wire [127:0] lut_out
);
wire [7:0] b00;
wire [7:0] b01;
wire [7:0] b02;
wire [7:0] b03;
wire [7:0] b10;
wire [7:0] b11;
wire [7:0] b12;
wire [7:0] b13;
wire [7:0] b20;
wire [7:0] b21;
wire [7:0] b22;
wire [7:0] b23;
wire [7:0] b30;
wire [7:0] b31;
wire [7:0] b32;
wire [7:0] b33;
herculesae_vx_aesinv u_inv_lut0(.lut_in(lut_in[127:120]), .lut_out(b33[7:0]));
herculesae_vx_aesinv u_inv_lut1(.lut_in(lut_in[119:112]), .lut_out(b23[7:0]));
herculesae_vx_aesinv u_inv_lut2(.lut_in(lut_in[111:104]), .lut_out(b13[7:0]));
herculesae_vx_aesinv u_inv_lut3(.lut_in(lut_in[103:96]), .lut_out(b03[7:0]));
herculesae_vx_aesinv u_inv_lut4(.lut_in(lut_in[95:88]), .lut_out(b32[7:0]));
herculesae_vx_aesinv u_inv_lut5(.lut_in(lut_in[87:80]), .lut_out(b22[7:0]));
herculesae_vx_aesinv u_inv_lut6(.lut_in(lut_in[79:72]), .lut_out(b12[7:0]));
herculesae_vx_aesinv u_inv_lut7(.lut_in(lut_in[71:64]), .lut_out(b02[7:0]));
herculesae_vx_aesinv u_inv_lut8 (.lut_in(lut_in[63:56]), .lut_out(b31[7:0]));
herculesae_vx_aesinv u_inv_lut9 (.lut_in(lut_in[55:48]), .lut_out(b21[7:0]));
herculesae_vx_aesinv u_inv_lut10(.lut_in(lut_in[47:40]), .lut_out(b11[7:0]));
herculesae_vx_aesinv u_inv_lut11(.lut_in(lut_in[39:32]), .lut_out(b01[7:0]));
herculesae_vx_aesinv u_inv_lut12(.lut_in(lut_in[31:24]), .lut_out(b30[7:0]));
herculesae_vx_aesinv u_inv_lut13(.lut_in(lut_in[23:16]), .lut_out(b20[7:0]));
herculesae_vx_aesinv u_inv_lut14(.lut_in(lut_in[15:8]), .lut_out(b10[7:0]));
herculesae_vx_aesinv u_inv_lut15(.lut_in(lut_in[7:0]), .lut_out(b00[7:0]));
assign lut_out[127:0] = {b33[7:0],b23[7:0],b13[7:0],b03[7:0],
b32[7:0],b22[7:0],b12[7:0],b02[7:0],
b31[7:0],b21[7:0],b11[7:0],b01[7:0],
b30[7:0],b20[7:0],b10[7:0],b00[7:0]
};
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

234
Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aesimc.sv
View File

@ -1,234 +0,0 @@
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_aesimc
(
input wire [127:0] d_in,
output wire [127:0] imc
);
wire [7:0] i00;
wire [7:0] i01;
wire [7:0] i02;
wire [7:0] i03;
wire [7:0] i10;
wire [7:0] i11;
wire [7:0] i12;
wire [7:0] i13;
wire [7:0] i20;
wire [7:0] i21;
wire [7:0] i22;
wire [7:0] i23;
wire [7:0] i30;
wire [7:0] i31;
wire [7:0] i32;
wire [7:0] i33;
wire [7:0] s00;
wire [10:0] s00_nr;
wire [7:0] s01;
wire [10:0] s01_nr;
wire [7:0] s02;
wire [10:0] s02_nr;
wire [7:0] s03;
wire [10:0] s03_nr;
wire [7:0] s10;
wire [10:0] s10_nr;
wire [7:0] s11;
wire [10:0] s11_nr;
wire [7:0] s12;
wire [10:0] s12_nr;
wire [7:0] s13;
wire [10:0] s13_nr;
wire [7:0] s20;
wire [10:0] s20_nr;
wire [7:0] s21;
wire [10:0] s21_nr;
wire [7:0] s22;
wire [10:0] s22_nr;
wire [7:0] s23;
wire [10:0] s23_nr;
wire [7:0] s30;
wire [10:0] s30_nr;
wire [7:0] s31;
wire [10:0] s31_nr;
wire [7:0] s32;
wire [10:0] s32_nr;
wire [7:0] s33;
wire [10:0] s33_nr;
assign i33[7:0] = d_in[127:120];
assign i23[7:0] = d_in[119:112];
assign i13[7:0] = d_in[111:104];
assign i03[7:0] = d_in[103:96];
assign i32[7:0] = d_in[95:88];
assign i22[7:0] = d_in[87:80];
assign i12[7:0] = d_in[79:72];
assign i02[7:0] = d_in[71:64];
assign i31[7:0] = d_in[63:56];
assign i21[7:0] = d_in[55:48];
assign i11[7:0] = d_in[47:40];
assign i01[7:0] = d_in[39:32];
assign i30[7:0] = d_in[31:24];
assign i20[7:0] = d_in[23:16];
assign i10[7:0] = d_in[15:8];
assign i00[7:0] = d_in[7:0];
assign s00_nr[10:0] = {i00[7:0],3'b000} ^ {1'b0,i00[7:0],2'b00} ^ {2'b00,i00[7:0],1'b0}
^ {i10[7:0],3'b000} ^ {2'b00,i10[7:0],1'b0} ^ {3'b000,i10[7:0]}
^ {i20[7:0],3'b000} ^ {1'b0,i20[7:0],2'b00} ^ {3'b000,i20[7:0]}
^ {i30[7:0],3'b000} ^ {3'b000,i30[7:0]};
assign s00[7:0] = s00_nr[7:0] ^ ({8{s00_nr[8]}} & 8'h1b) ^ ({8{s00_nr[9]}} & 8'h36) ^ ({8{s00_nr[10]}} & 8'h6c);
assign s01_nr[10:0] = {i01[7:0],3'b000} ^ {1'b0,i01[7:0],2'b00} ^ {2'b00,i01[7:0],1'b0}
^ {i11[7:0],3'b000} ^ {2'b00,i11[7:0],1'b0} ^ {3'b000,i11[7:0]}
^ {i21[7:0],3'b000} ^ {1'b0,i21[7:0],2'b00} ^ {3'b000,i21[7:0]}
^ {i31[7:0],3'b000} ^ {3'b000,i31[7:0]};
assign s01[7:0] = s01_nr[7:0] ^ ({8{s01_nr[8]}} & 8'h1b) ^ ({8{s01_nr[9]}} & 8'h36) ^ ({8{s01_nr[10]}} & 8'h6c);
assign s02_nr[10:0] = {i02[7:0],3'b000} ^ {1'b0,i02[7:0],2'b00} ^ {2'b00,i02[7:0],1'b0}
^ {i12[7:0],3'b000} ^ {2'b00,i12[7:0],1'b0} ^ {3'b000,i12[7:0]}
^ {i22[7:0],3'b000} ^ {1'b0,i22[7:0],2'b00} ^ {3'b000,i22[7:0]}
^ {i32[7:0],3'b000} ^ {3'b000,i32[7:0]};
assign s02[7:0] = s02_nr[7:0] ^ ({8{s02_nr[8]}} & 8'h1b) ^ ({8{s02_nr[9]}} & 8'h36) ^ ({8{s02_nr[10]}} & 8'h6c);
assign s03_nr[10:0] = {i03[7:0],3'b000} ^ {1'b0,i03[7:0],2'b00} ^ {2'b00,i03[7:0],1'b0}
^ {i13[7:0],3'b000} ^ {2'b00,i13[7:0],1'b0} ^ {3'b000,i13[7:0]}
^ {i23[7:0],3'b000} ^ {1'b0,i23[7:0],2'b00} ^ {3'b000,i23[7:0]}
^ {i33[7:0],3'b000} ^ {3'b000,i33[7:0]};
assign s03[7:0] = s03_nr[7:0] ^ ({8{s03_nr[8]}} & 8'h1b) ^ ({8{s03_nr[9]}} & 8'h36) ^ ({8{s03_nr[10]}} & 8'h6c);
assign s10_nr[10:0] = {i10[7:0],3'b000} ^ {1'b0,i10[7:0],2'b00} ^ {2'b00,i10[7:0],1'b0}
^ {i20[7:0],3'b000} ^ {2'b00,i20[7:0],1'b0} ^ {3'b000,i20[7:0]}
^ {i30[7:0],3'b000} ^ {1'b0,i30[7:0],2'b00} ^ {3'b000,i30[7:0]}
^ {i00[7:0],3'b000} ^ {3'b000,i00[7:0]};
assign s10[7:0] = s10_nr[7:0] ^ ({8{s10_nr[8]}} & 8'h1b) ^ ({8{s10_nr[9]}} & 8'h36) ^ ({8{s10_nr[10]}} & 8'h6c);
assign s11_nr[10:0] = {i11[7:0],3'b000} ^ {1'b0,i11[7:0],2'b00} ^ {2'b00,i11[7:0],1'b0}
^ {i21[7:0],3'b000} ^ {2'b00,i21[7:0],1'b0} ^ {3'b000,i21[7:0]}
^ {i31[7:0],3'b000} ^ {1'b0,i31[7:0],2'b00} ^ {3'b000,i31[7:0]}
^ {i01[7:0],3'b000} ^ {3'b000,i01[7:0]};
assign s11[7:0] = s11_nr[7:0] ^ ({8{s11_nr[8]}} & 8'h1b) ^ ({8{s11_nr[9]}} & 8'h36) ^ ({8{s11_nr[10]}} & 8'h6c);
assign s12_nr[10:0] = {i12[7:0],3'b000} ^ {1'b0,i12[7:0],2'b00} ^ {2'b00,i12[7:0],1'b0}
^ {i22[7:0],3'b000} ^ {2'b00,i22[7:0],1'b0} ^ {3'b000,i22[7:0]}
^ {i32[7:0],3'b000} ^ {1'b0,i32[7:0],2'b00} ^ {3'b000,i32[7:0]}
^ {i02[7:0],3'b000} ^ {3'b000,i02[7:0]};
assign s12[7:0] = s12_nr[7:0] ^ ({8{s12_nr[8]}} & 8'h1b) ^ ({8{s12_nr[9]}} & 8'h36) ^ ({8{s12_nr[10]}} & 8'h6c);
assign s13_nr[10:0] = {i13[7:0],3'b000} ^ {1'b0,i13[7:0],2'b00} ^ {2'b00,i13[7:0],1'b0}
^ {i23[7:0],3'b000} ^ {2'b00,i23[7:0],1'b0} ^ {3'b000,i23[7:0]}
^ {i33[7:0],3'b000} ^ {1'b0,i33[7:0],2'b00} ^ {3'b000,i33[7:0]}
^ {i03[7:0],3'b000} ^ {3'b000,i03[7:0]};
assign s13[7:0] = s13_nr[7:0] ^ ({8{s13_nr[8]}} & 8'h1b) ^ ({8{s13_nr[9]}} & 8'h36) ^ ({8{s13_nr[10]}} & 8'h6c);
assign s20_nr[10:0] = {i20[7:0],3'b000} ^ {1'b0,i20[7:0],2'b00} ^ {2'b00,i20[7:0],1'b0}
^ {i30[7:0],3'b000} ^ {2'b00,i30[7:0],1'b0} ^ {3'b000,i30[7:0]}
^ {i00[7:0],3'b000} ^ {1'b0,i00[7:0],2'b00} ^ {3'b000,i00[7:0]}
^ {i10[7:0],3'b000} ^ {3'b000,i10[7:0]};
assign s20[7:0] = s20_nr[7:0] ^ ({8{s20_nr[8]}} & 8'h1b) ^ ({8{s20_nr[9]}} & 8'h36) ^ ({8{s20_nr[10]}} & 8'h6c);
assign s21_nr[10:0] = {i21[7:0],3'b000} ^ {1'b0,i21[7:0],2'b00} ^ {2'b00,i21[7:0],1'b0}
^ {i31[7:0],3'b000} ^ {2'b00,i31[7:0],1'b0} ^ {3'b000,i31[7:0]}
^ {i01[7:0],3'b000} ^ {1'b0,i01[7:0],2'b00} ^ {3'b000,i01[7:0]}
^ {i11[7:0],3'b000} ^ {3'b000,i11[7:0]};
assign s21[7:0] = s21_nr[7:0] ^ ({8{s21_nr[8]}} & 8'h1b) ^ ({8{s21_nr[9]}} & 8'h36) ^ ({8{s21_nr[10]}} & 8'h6c);
assign s22_nr[10:0] = {i22[7:0],3'b000} ^ {1'b0,i22[7:0],2'b00} ^ {2'b00,i22[7:0],1'b0}
^ {i32[7:0],3'b000} ^ {2'b00,i32[7:0],1'b0} ^ {3'b000,i32[7:0]}
^ {i02[7:0],3'b000} ^ {1'b0,i02[7:0],2'b00} ^ {3'b000,i02[7:0]}
^ {i12[7:0],3'b000} ^ {3'b000,i12[7:0]};
assign s22[7:0] = s22_nr[7:0] ^ ({8{s22_nr[8]}} & 8'h1b) ^ ({8{s22_nr[9]}} & 8'h36) ^ ({8{s22_nr[10]}} & 8'h6c);
assign s23_nr[10:0] = {i23[7:0],3'b000} ^ {1'b0,i23[7:0],2'b00} ^ {2'b00,i23[7:0],1'b0}
^ {i33[7:0],3'b000} ^ {2'b00,i33[7:0],1'b0} ^ {3'b000,i33[7:0]}
^ {i03[7:0],3'b000} ^ {1'b0,i03[7:0],2'b00} ^ {3'b000,i03[7:0]}
^ {i13[7:0],3'b000} ^ {3'b000,i13[7:0]};
assign s23[7:0] = s23_nr[7:0] ^ ({8{s23_nr[8]}} & 8'h1b) ^ ({8{s23_nr[9]}} & 8'h36) ^ ({8{s23_nr[10]}} & 8'h6c);
assign s30_nr[10:0] = {i30[7:0],3'b000} ^ {1'b0,i30[7:0],2'b00} ^ {2'b00,i30[7:0],1'b0}
^ {i00[7:0],3'b000} ^ {2'b00,i00[7:0],1'b0} ^ {3'b000,i00[7:0]}
^ {i10[7:0],3'b000} ^ {1'b0,i10[7:0],2'b00} ^ {3'b000,i10[7:0]}
^ {i20[7:0],3'b000} ^ {3'b000,i20[7:0]};
assign s30[7:0] = s30_nr[7:0] ^ ({8{s30_nr[8]}} & 8'h1b) ^ ({8{s30_nr[9]}} & 8'h36) ^ ({8{s30_nr[10]}} & 8'h6c);
assign s31_nr[10:0] = {i31[7:0],3'b000} ^ {1'b0,i31[7:0],2'b00} ^ {2'b00,i31[7:0],1'b0}
^ {i01[7:0],3'b000} ^ {2'b00,i01[7:0],1'b0} ^ {3'b000,i01[7:0]}
^ {i11[7:0],3'b000} ^ {1'b0,i11[7:0],2'b00} ^ {3'b000,i11[7:0]}
^ {i21[7:0],3'b000} ^ {3'b000,i21[7:0]};
assign s31[7:0] = s31_nr[7:0] ^ ({8{s31_nr[8]}} & 8'h1b) ^ ({8{s31_nr[9]}} & 8'h36) ^ ({8{s31_nr[10]}} & 8'h6c);
assign s32_nr[10:0] = {i32[7:0],3'b000} ^ {1'b0,i32[7:0],2'b00} ^ {2'b00,i32[7:0],1'b0}
^ {i02[7:0],3'b000} ^ {2'b00,i02[7:0],1'b0} ^ {3'b000,i02[7:0]}
^ {i12[7:0],3'b000} ^ {1'b0,i12[7:0],2'b00} ^ {3'b000,i12[7:0]}
^ {i22[7:0],3'b000} ^ {3'b000,i22[7:0]};
assign s32[7:0] = s32_nr[7:0] ^ ({8{s32_nr[8]}} & 8'h1b) ^ ({8{s32_nr[9]}} & 8'h36) ^ ({8{s32_nr[10]}} & 8'h6c);
assign s33_nr[10:0] = {i33[7:0],3'b000} ^ {1'b0,i33[7:0],2'b00} ^ {2'b00,i33[7:0],1'b0}
^ {i03[7:0],3'b000} ^ {2'b00,i03[7:0],1'b0} ^ {3'b000,i03[7:0]}
^ {i13[7:0],3'b000} ^ {1'b0,i13[7:0],2'b00} ^ {3'b000,i13[7:0]}
^ {i23[7:0],3'b000} ^ {3'b000,i23[7:0]};
assign s33[7:0] = s33_nr[7:0] ^ ({8{s33_nr[8]}} & 8'h1b) ^ ({8{s33_nr[9]}} & 8'h36) ^ ({8{s33_nr[10]}} & 8'h6c);
assign imc[127:120] = s33[7:0];
assign imc[119:112] = s23[7:0];
assign imc[111:104] = s13[7:0];
assign imc[103:96] = s03[7:0];
assign imc[95:88] = s32[7:0];
assign imc[87:80] = s22[7:0];
assign imc[79:72] = s12[7:0];
assign imc[71:64] = s02[7:0];
assign imc[63:56] = s31[7:0];
assign imc[55:48] = s21[7:0];
assign imc[47:40] = s11[7:0];
assign imc[39:32] = s01[7:0];
assign imc[31:24] = s30[7:0];
assign imc[23:16] = s20[7:0];
assign imc[15:8] = s10[7:0];
assign imc[7:0] = s00[7:0];
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

517
Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aesinv.sv
View File

@ -1,517 +0,0 @@
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_aesinv
(
input wire [7:0] lut_in,
output wire [7:0] lut_out
);
assign lut_out[7] = (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]
&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]
&lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[0]) | (
lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]
&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]
&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7]&lut_in[6]
&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[6]
&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (
!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]
&lut_in[1]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]
&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[5]&!lut_in[4]&lut_in[3]
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]
&lut_in[4]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]
&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]
&lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]) | (
!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]
&!lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]
&!lut_in[2]&!lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]
&lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[6]&lut_in[4]&!lut_in[3]
&lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]
&lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]) | (lut_in[7]&!lut_in[6]
&lut_in[5]&!lut_in[4]&lut_in[2]&!lut_in[1]) | (lut_in[7]&!lut_in[6]
&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (
lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[2]&!lut_in[1]
&!lut_in[0]) | (lut_in[7]&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[1]
&!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]) | (lut_in[7]&lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[6]&!lut_in[5]&lut_in[4]
&lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]
&!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (lut_in[7]
&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]
&lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (
!lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]
&lut_in[0]) | (lut_in[6]&lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]
&lut_in[0]) | (!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]
&lut_in[0]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]
&lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]
&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[5]
&!lut_in[4]&lut_in[3]&lut_in[1]) | (!lut_in[7]&lut_in[6]&lut_in[5]
&lut_in[4]&lut_in[3]&lut_in[2]) | (lut_in[6]&!lut_in[5]&!lut_in[4]
&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[6]&!lut_in[5]
&lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]
&!lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[6]
&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]
&!lut_in[6]&!lut_in[5]&!lut_in[3]&lut_in[2]&!lut_in[1]) | (lut_in[6]
&!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (!lut_in[7]
&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (lut_in[7]
&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[2]&lut_in[1]) | (!lut_in[7]
&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[5]
&lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[5]
&lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]
&lut_in[6]&lut_in[5]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[4]
&!lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[6]&lut_in[5]
&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6]
&lut_in[5]&lut_in[3]&!lut_in[2]) | (lut_in[6]&!lut_in[5]&!lut_in[4]
&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[6]&!lut_in[5]&lut_in[4]
&lut_in[3]&lut_in[1]) | (!lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]
&lut_in[1]) | (lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[1]&lut_in[0]);
assign lut_out[6] = (lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]
&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]
&!lut_in[6]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (
!lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]
&lut_in[1]) | (lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]) | (lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]
&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]
&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (
lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]
&lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]
&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[4]
&lut_in[3]&lut_in[2]&!lut_in[1]) | (lut_in[7]&lut_in[6]&lut_in[5]
&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]
&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[7]&lut_in[6]
&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[6]
&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]
&lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (
!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]
&!lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]
&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]
&!lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[7]&!lut_in[6]
&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]) | (lut_in[7]&lut_in[5]
&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]
&lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[0]) | (lut_in[7]
&lut_in[6]&!lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (
lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]
&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]
&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]
&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6]
&!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]) | (!lut_in[6]&!lut_in[5]
&!lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[7]
&!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]) | (
!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[0]) | (
!lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]
&!lut_in[1]) | (lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]
&!lut_in[1]&!lut_in[0]) | (lut_in[6]&lut_in[4]&!lut_in[3]&lut_in[2]
&!lut_in[1]&lut_in[0]) | (lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]
&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7]&lut_in[5]&!lut_in[4]
&!lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]
&!lut_in[3]&lut_in[2]&lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]
&lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]
&!lut_in[4]&!lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]
&!lut_in[4]&!lut_in[3]&lut_in[2]) | (!lut_in[6]&lut_in[5]&!lut_in[4]
&lut_in[1]&lut_in[0]) | (!lut_in[6]&!lut_in[5]&!lut_in[3]&lut_in[2]
&lut_in[1]&lut_in[0]) | (!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]
&!lut_in[1]&lut_in[0]) | (lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[1]
&lut_in[0]) | (!lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[2]&!lut_in[1]
&lut_in[0]) | (!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[1]&lut_in[0]) | (
lut_in[6]&!lut_in[5]&lut_in[3]&lut_in[2]&lut_in[0]) | (!lut_in[7]
&!lut_in[6]&!lut_in[5]&lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[5]
&lut_in[3]&lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[4]
&lut_in[3]&!lut_in[1]) | (lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[2]
&!lut_in[1]&lut_in[0]);
assign lut_out[5] = (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]
&lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]
&!lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]
&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]
&!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]
&lut_in[5]&lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]
&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]
&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
&lut_in[2]&lut_in[1]) | (!lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]
&!lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[7]&lut_in[6]&lut_in[5]
&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[6]&!lut_in[5]
&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7]
&lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (
!lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&lut_in[0]) | (
!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]) | (
!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]
&lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]
&lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]
&!lut_in[2]&lut_in[1]) | (lut_in[7]&lut_in[5]&lut_in[4]&lut_in[3]
&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[4]
&!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]
&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[7]
&lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (
!lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]) | (
!lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]
&!lut_in[1]) | (!lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]
&lut_in[2]&lut_in[1]) | (lut_in[6]&lut_in[5]&lut_in[3]&!lut_in[2]
&lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4]
&!lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[4]
&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[5]&!lut_in[4]
&!lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[6]&!lut_in[5]
&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[6]
&!lut_in[5]&lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[6]
&!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[6]
&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (lut_in[6]
&!lut_in[5]&!lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[7]
&!lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[7]
&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (lut_in[5]
&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[0]) | (!lut_in[7]&lut_in[4]
&!lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[5]&lut_in[3]
&lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[2]
&!lut_in[1]&lut_in[0]) | (!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[1]
&lut_in[0]) | (lut_in[6]&!lut_in[5]&lut_in[3]&lut_in[2]&lut_in[0]) | (
!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[2]&lut_in[1]) | (!lut_in[7]
&!lut_in[5]&lut_in[3]&lut_in[2]&lut_in[1]) | (!lut_in[6]&!lut_in[4]
&!lut_in[3]&!lut_in[1]&lut_in[0]) | (!lut_in[5]&!lut_in[4]&lut_in[3]
&lut_in[2]&lut_in[1]) | (lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[1]
&lut_in[0]) | (!lut_in[7]&!lut_in[4]&lut_in[2]&lut_in[1]);
assign lut_out[4] = (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]
&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[6]
&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (
lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[2]&lut_in[1]
&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]
&lut_in[2]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4]
&!lut_in[3]&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]
&!lut_in[4]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]
&!lut_in[5]&!lut_in[4]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]
&lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (
lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]
&lut_in[0]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
&lut_in[2]&!lut_in[1]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]
&lut_in[3]&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[4]&lut_in[3]
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[4]
&lut_in[3]&lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]
&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[6]&lut_in[5]
&lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]
&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]) | (
!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]
&lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]
&!lut_in[2]&lut_in[1]) | (!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[4]
&!lut_in[3]&lut_in[1]) | (lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4]
&lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6]&lut_in[5]
&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (lut_in[7]&lut_in[6]
&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]) | (lut_in[7]&lut_in[5]
&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]
&!lut_in[6]&lut_in[4]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]
&lut_in[6]&!lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (
lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]
&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]
&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[5]&!lut_in[4]
&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[6]&!lut_in[5]
&!lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[7]
&!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]) | (
!lut_in[7]&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (
!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]
&!lut_in[0]) | (lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]
&!lut_in[1]&!lut_in[0]) | (!lut_in[6]&lut_in[4]&lut_in[3]&lut_in[2]
&lut_in[1]&lut_in[0]) | (!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]
&!lut_in[1]&!lut_in[0]) | (!lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]
&!lut_in[1]&lut_in[0]) | (lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]
&lut_in[1]&lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[3]
&lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]
&lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[2]
&lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[5]&lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[3]&lut_in[2]
&lut_in[1]&lut_in[0]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]
&lut_in[1]&lut_in[0]) | (!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]
&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]
&!lut_in[3]) | (!lut_in[7]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]) | (
!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]) | (
lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (
!lut_in[7]&!lut_in[6]&lut_in[4]&lut_in[3]&!lut_in[1]) | (!lut_in[7]
&lut_in[6]&lut_in[5]&lut_in[3]&!lut_in[2]) | (!lut_in[7]&!lut_in[6]
&lut_in[4]&lut_in[2]&!lut_in[1]) | (!lut_in[6]&!lut_in[4]&!lut_in[3]
&!lut_in[1]&lut_in[0]) | (lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[2]
&!lut_in[1]&lut_in[0]);
assign lut_out[3] = (lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]
&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]
&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]
&lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]
&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]
&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]
&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[1]&!lut_in[0]) | (lut_in[7]
&lut_in[6]&!lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (
lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]
&lut_in[1]&!lut_in[0]) | (!lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]
&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]
&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]
&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (lut_in[7]
&lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[2]&!lut_in[0]) | (lut_in[7]
&!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (
lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]
&lut_in[0]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]
&lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[7]&lut_in[6]&lut_in[5]
&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&!lut_in[4]
&!lut_in[3]&lut_in[2]&lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]
&!lut_in[3]&!lut_in[2]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]
&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]
&!lut_in[6]&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (
lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[2]&!lut_in[1]
&!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]) | (lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]
&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]
&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (lut_in[7]&lut_in[5]
&lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&lut_in[6]
&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (!lut_in[7]
&!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]) | (
!lut_in[7]&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (
!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]
&!lut_in[0]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]
&!lut_in[1]&lut_in[0]) | (lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[5]
&!lut_in[4]&lut_in[3]&lut_in[1]) | (!lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]
&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[6]&!lut_in[4]
&lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[6]&lut_in[4]
&lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[6]&!lut_in[4]
&!lut_in[3]&lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[7]&lut_in[6]
&!lut_in[5]&lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[7]&!lut_in[6]
&!lut_in[5]&!lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6]
&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[7]&!lut_in[6]
&!lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[6]
&!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]) | (lut_in[6]&lut_in[4]
&lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[6]&lut_in[3]&!lut_in[2]
&lut_in[1]&lut_in[0]) | (!lut_in[6]&lut_in[4]&!lut_in[3]&!lut_in[2]
&lut_in[1]&lut_in[0]) | (!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]
&!lut_in[1]&lut_in[0]) | (lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
&lut_in[0]) | (!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]
&!lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[2]&!lut_in[1]
&lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[1]) | (
!lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[1]);
assign lut_out[2] = (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]
&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]
&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]
&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[3]&!lut_in[2]
&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]
&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]
&lut_in[5]&!lut_in[4]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]
&lut_in[6]&!lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (
lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]
&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[3]
&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]
&!lut_in[4]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]
&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (!lut_in[6]
&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (
!lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]
&lut_in[1]) | (!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3]
&lut_in[2]&!lut_in[1]) | (lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]
&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[7]&!lut_in[6]
&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]) | (lut_in[7]
&!lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (
lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[2]&!lut_in[1]
&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[4]&lut_in[3]&!lut_in[2]
&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]
&lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[6]&!lut_in[5]&!lut_in[4]
&!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[6]&!lut_in[5]
&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[7]
&lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]) | (
!lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]
&!lut_in[1]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[4]
&lut_in[3]&!lut_in[2]&!lut_in[1]) | (lut_in[7]&!lut_in[6]&lut_in[5]
&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[6]&lut_in[5]
&lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[5]
&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[6]
&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (
!lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]
&lut_in[1]) | (!lut_in[6]&!lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]
&lut_in[0]) | (lut_in[7]&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]
&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]
&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]
&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]
&lut_in[5]&lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[6]
&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (
lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]
&!lut_in[0]) | (lut_in[6]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]
&lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]) | (!lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]
&!lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]&lut_in[4]&lut_in[3]
&lut_in[2]&!lut_in[1]) | (lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]
&lut_in[1]&lut_in[0]) | (!lut_in[6]&lut_in[4]&lut_in[3]&lut_in[2]
&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]
&lut_in[3]&lut_in[2]) | (!lut_in[6]&lut_in[4]&!lut_in[3]&!lut_in[2]
&lut_in[1]&lut_in[0]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]
&lut_in[1]&lut_in[0]) | (lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3]
&lut_in[0]) | (!lut_in[5]&!lut_in[4]&lut_in[2]&lut_in[1]&lut_in[0]) | (
!lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (
lut_in[6]&lut_in[5]&!lut_in[3]&lut_in[2]&lut_in[0]) | (lut_in[6]
&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[7]
&lut_in[6]&!lut_in[5]&!lut_in[3]&lut_in[1]) | (lut_in[6]&!lut_in[5]
&!lut_in[4]&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]
&!lut_in[5]&!lut_in[3]&!lut_in[1]);
assign lut_out[1] = (lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]
&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7]
&lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]) | (
lut_in[7]&!lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]
&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[3]&lut_in[2]
&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]
&!lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&!lut_in[4]
&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]
&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (lut_in[7]
&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]) | (
lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]
&!lut_in[0]) | (lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]
&!lut_in[1]&lut_in[0]) | (lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]
&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[5]
&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (lut_in[7]&!lut_in[6]
&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[6]
&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (
!lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]
&lut_in[1]) | (lut_in[7]&!lut_in[6]&lut_in[4]&!lut_in[2]&lut_in[1]
&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[4]&lut_in[3]&!lut_in[2]
&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[3]
&!lut_in[2]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]
&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]
&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7]
&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (
!lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]) | (
lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]
&lut_in[0]) | (lut_in[7]&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]
&!lut_in[0]) | (!lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]
&lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4]
&!lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[4]
&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[6]&lut_in[5]
&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[6]
&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[6]
&lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[5]
&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[6]
&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]
&!lut_in[6]&lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]) | (lut_in[6]
&!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (lut_in[7]
&!lut_in[6]&!lut_in[4]&!lut_in[1]&!lut_in[0]) | (lut_in[6]&!lut_in[5]
&!lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[5]
&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[7]&!lut_in[6]
&!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]) | (lut_in[6]&!lut_in[5]
&lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]
&!lut_in[4]&!lut_in[2]&lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[4]
&!lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]
&!lut_in[3]&lut_in[2]) | (!lut_in[7]&lut_in[5]&lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[3]&lut_in[2]
&lut_in[1]&lut_in[0]) | (!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]
&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]) | (lut_in[7]&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[1]) | (
!lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]);
assign lut_out[0] = (lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]
&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]
&!lut_in[6]&!lut_in[5]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (
lut_in[7]&!lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]
&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]
&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]
&!lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (
!lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]
&!lut_in[1]) | (lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]) | (lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[6]&!lut_in[5]&!lut_in[4]
&!lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]
&!lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]) | (lut_in[6]
&lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (
lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]
&!lut_in[0]) | (lut_in[7]&!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]
&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]
&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[6]&!lut_in[5]&lut_in[4]
&lut_in[3]&lut_in[1]&lut_in[0]) | (lut_in[6]&!lut_in[5]&lut_in[4]
&!lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[7]&!lut_in[6]
&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[7]
&!lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (
!lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]
&lut_in[0]) | (lut_in[6]&lut_in[5]&lut_in[3]&lut_in[2]&!lut_in[1]
&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]
&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[4]&lut_in[3]&!lut_in[2]
&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[5]&lut_in[4]&lut_in[3]
&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[6]&!lut_in[5]&lut_in[4]
&lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]
&!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]) | (!lut_in[6]&!lut_in[5]
&!lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[7]
&!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]) | (
lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]
&!lut_in[0]) | (lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]
&lut_in[0]) | (!lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]
&lut_in[2]) | (!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]
&!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]) | (lut_in[6]&!lut_in[4]&!lut_in[3]&lut_in[2]
&lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[5]&!lut_in[4]&!lut_in[3]
&lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6]&!lut_in[4]&!lut_in[3]
&lut_in[2]&!lut_in[1]) | (lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3]
&!lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]
&lut_in[2]&!lut_in[1]) | (lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[2]
&lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[3]
&!lut_in[2]&lut_in[1]) | (lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[2]
&!lut_in[0]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[2]&lut_in[1]
&lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]
&lut_in[2]) | (!lut_in[6]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]
&lut_in[0]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&lut_in[1]
&lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[4]&lut_in[3]&lut_in[1]) | (
!lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (
!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[3]&lut_in[1]) | (!lut_in[7]
&!lut_in[6]&lut_in[4]&lut_in[2]&!lut_in[1]) | (lut_in[6]&lut_in[5]
&!lut_in[4]&lut_in[1]&lut_in[0]);
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

186
Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aesmc.sv
View File

@ -1,186 +0,0 @@
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_aesmc
(
input wire [127:0] d_in,
output wire [127:0] mc
);
wire [7:0] i00;
wire [7:0] i01;
wire [7:0] i02;
wire [7:0] i03;
wire [7:0] i10;
wire [7:0] i11;
wire [7:0] i12;
wire [7:0] i13;
wire [7:0] i20;
wire [7:0] i21;
wire [7:0] i22;
wire [7:0] i23;
wire [7:0] i30;
wire [7:0] i31;
wire [7:0] i32;
wire [7:0] i33;
wire [7:0] s00;
wire [7:0] s01;
wire [7:0] s02;
wire [7:0] s03;
wire [7:0] s10;
wire [7:0] s11;
wire [7:0] s12;
wire [7:0] s13;
wire [7:0] s20;
wire [7:0] s21;
wire [7:0] s22;
wire [7:0] s23;
wire [7:0] s30;
wire [7:0] s31;
wire [7:0] s32;
wire [7:0] s33;
assign i33[7:0] = d_in[127:120];
assign i23[7:0] = d_in[119:112];
assign i13[7:0] = d_in[111:104];
assign i03[7:0] = d_in[103:96];
assign i32[7:0] = d_in[95:88];
assign i22[7:0] = d_in[87:80];
assign i12[7:0] = d_in[79:72];
assign i02[7:0] = d_in[71:64];
assign i31[7:0] = d_in[63:56];
assign i21[7:0] = d_in[55:48];
assign i11[7:0] = d_in[47:40];
assign i01[7:0] = d_in[39:32];
assign i30[7:0] = d_in[31:24];
assign i20[7:0] = d_in[23:16];
assign i10[7:0] = d_in[15:8];
assign i00[7:0] = d_in[7:0];
assign s00[7:0] = {i00[6:0],1'b0} ^ ({8{i00[7]}} & 8'h1b)
^ {i10[6:0],1'b0} ^ ({8{i10[7]}} & 8'h1b) ^ i10[7:0]
^ i20[7:0]
^ i30[7:0];
assign s01[7:0] = {i01[6:0],1'b0} ^ ({8{i01[7]}} & 8'h1b)
^ {i11[6:0],1'b0} ^ ({8{i11[7]}} & 8'h1b) ^ i11[7:0]
^ i21[7:0]
^ i31[7:0];
assign s02[7:0] = {i02[6:0],1'b0} ^ ({8{i02[7]}} & 8'h1b)
^ {i12[6:0],1'b0} ^ ({8{i12[7]}} & 8'h1b) ^ i12[7:0]
^ i22[7:0]
^ i32[7:0];
assign s03[7:0] = {i03[6:0],1'b0} ^ ({8{i03[7]}} & 8'h1b)
^ {i13[6:0],1'b0} ^ ({8{i13[7]}} & 8'h1b) ^ i13[7:0]
^ i23[7:0]
^ i33[7:0];
assign s10[7:0] = i00[7:0]
^ {i10[6:0],1'b0} ^ ({8{i10[7]}} & 8'h1b)
^ {i20[6:0],1'b0} ^ ({8{i20[7]}} & 8'h1b) ^ i20[7:0]
^ i30[7:0];
assign s11[7:0] = i01[7:0]
^ {i11[6:0],1'b0} ^ ({8{i11[7]}} & 8'h1b)
^ {i21[6:0],1'b0} ^ ({8{i21[7]}} & 8'h1b) ^ i21[7:0]
^ i31[7:0];
assign s12[7:0] = i02[7:0]
^ {i12[6:0],1'b0} ^ ({8{i12[7]}} & 8'h1b)
^ {i22[6:0],1'b0} ^ ({8{i22[7]}} & 8'h1b) ^ i22[7:0]
^ i32[7:0];
assign s13[7:0] = i03[7:0]
^ {i13[6:0],1'b0} ^ ({8{i13[7]}} & 8'h1b)
^ {i23[6:0],1'b0} ^ ({8{i23[7]}} & 8'h1b) ^ i23[7:0]
^ i33[7:0];
assign s20[7:0] = i00[7:0]
^ i10[7:0]
^ {i20[6:0],1'b0} ^ ({8{i20[7]}} & 8'h1b)
^ {i30[6:0],1'b0} ^ ({8{i30[7]}} & 8'h1b) ^ i30[7:0];
assign s21[7:0] = i01[7:0]
^ i11[7:0]
^ {i21[6:0],1'b0} ^ ({8{i21[7]}} & 8'h1b)
^ {i31[6:0],1'b0} ^ ({8{i31[7]}} & 8'h1b) ^ i31[7:0];
assign s22[7:0] = i02[7:0]
^ i12[7:0]
^ {i22[6:0],1'b0} ^ ({8{i22[7]}} & 8'h1b)
^ {i32[6:0],1'b0} ^ ({8{i32[7]}} & 8'h1b) ^ i32[7:0];
assign s23[7:0] = i03[7:0]
^ i13[7:0]
^ {i23[6:0],1'b0} ^ ({8{i23[7]}} & 8'h1b)
^ {i33[6:0],1'b0} ^ ({8{i33[7]}} & 8'h1b) ^ i33[7:0];
assign s30[7:0] = {i00[6:0],1'b0} ^ ({8{i00[7]}} & 8'h1b) ^ i00[7:0]
^ i10[7:0]
^ i20[7:0]
^ {i30[6:0],1'b0} ^ ({8{i30[7]}} & 8'h1b);
assign s31[7:0] = {i01[6:0],1'b0} ^ ({8{i01[7]}} & 8'h1b) ^ i01[7:0]
^ i11[7:0]
^ i21[7:0]
^ {i31[6:0],1'b0} ^ ({8{i31[7]}} & 8'h1b);
assign s32[7:0] = {i02[6:0],1'b0} ^ ({8{i02[7]}} & 8'h1b) ^ i02[7:0]
^ i12[7:0]
^ i22[7:0]
^ {i32[6:0],1'b0} ^ ({8{i32[7]}} & 8'h1b);
assign s33[7:0] = {i03[6:0],1'b0} ^ ({8{i03[7]}} & 8'h1b) ^ i03[7:0]
^ i13[7:0]
^ i23[7:0]
^ {i33[6:0],1'b0} ^ ({8{i33[7]}} & 8'h1b);
assign mc[127:120] = s33[7:0];
assign mc[119:112] = s23[7:0];
assign mc[111:104] = s13[7:0];
assign mc[103:96] = s03[7:0];
assign mc[95:88] = s32[7:0];
assign mc[87:80] = s22[7:0];
assign mc[79:72] = s12[7:0];
assign mc[71:64] = s02[7:0];
assign mc[63:56] = s31[7:0];
assign mc[55:48] = s21[7:0];
assign mc[47:40] = s11[7:0];
assign mc[39:32] = s01[7:0];
assign mc[31:24] = s30[7:0];
assign mc[23:16] = s20[7:0];
assign mc[15:8] = s10[7:0];
assign mc[7:0] = s00[7:0];
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

966
Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_crypt.sv
View File

@ -1,966 +0,0 @@
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_crypt
(
input wire clk,
input wire reset,
input wire ival_v1_q,
input wire sha1c_v1_q,
input wire sha1p_v1_q,
input wire sha1m_v1_q,
input wire sha1cpm_v1_q,
input wire sha256h_v1_q,
input wire sha256h2_v1_q,
input wire sha256hh2_v1_q,
input wire sha1h_v1_q,
input wire sha1su0_v1_q,
input wire sha1su1_v1_q,
input wire sha256su0_v1_q,
input wire sha256su1_v1_q,
input wire sha256su1_dup_x_v1_q,
input wire sha256su1_dup_y_v1_q,
input wire sha256su1_dup_z_v1_q,
input wire [127:0] opa_v1,
input wire [127:0] opb_v1,
input wire [127:0] opc_v1,
output wire [127:0] cryptout_v2,
output wire [127:0] cryptout_v4,
output wire crypt_active
);
wire block_opa_passthrough;
wire [63:0] carry1c_v1;
wire [63:0] carry4c_v3;
wire [31:0] carry4c_v4;
wire [63:0] carry_2c4c_v2;
wire [31:0] carry_sha1cpm_v1;
wire [31:0] carry_sha1cpm_v2;
wire [31:0] carry_sha1cpm_v3;
wire [31:0] carry_sha1cpm_v4;
wire [63:0] carry_sha256h32_v1;
wire [63:0] carry_sha256h32_v2;
wire [63:0] carry_sha256h32_v3;
wire [31:0] carry_sha256h32_v4;
wire [31:0] carry_sha256su0_v1;
wire [63:0] carry_sha256su1_v1;
wire [63:0] carry_sha256su1_v2;
wire ival_en;
wire ival_v1_or_v2;
wire ival_v2_4latency;
reg ival_v2_q;
reg ival_v3_q;
wire [127:0] newa_v1;
wire [127:0] newa_v2;
wire [127:0] newa_v3;
wire [127:0] newb_v1;
wire [127:0] newb_v2;
wire [127:0] newb_v3;
wire [95:0] newc_v1;
wire [127:0] newx_v4;
wire [127:0] newy_v4;
reg [127:0] opa_v2_q;
reg [127:0] opa_v3_q;
reg [127:0] opa_v4_q;
reg [127:0] opb_v2_q;
reg [127:0] opb_v3_q;
reg [127:0] opb_v4_q;
reg [95:0] opc_v2_q;
reg [63:0] opc_v3_q;
reg [31:0] opc_v4_q;
wire [127:0] sha1_out_v1;
wire sha1_v1;
wire [127:0] sha1_xin_v1;
wire [31:0] sha1_yin_v1;
wire [31:0] sha1_zin_v1;
reg sha1c_v2_q;
reg sha1c_v3_q;
reg sha1c_v4_q;
reg sha1cpm_h_v4_q;
reg sha1cpm_l_v4_q;
reg sha1cpm_v2_q;
reg sha1cpm_v3_q;
reg sha1cpm_v4_q;
wire [127:0] sha1cpm_x_v1;
wire [127:0] sha1cpm_x_v2;
wire [127:0] sha1cpm_x_v3;
wire [127:0] sha1cpm_x_v4;
wire [127:0] sha1cpm_y_v1;
wire [127:0] sha1cpm_y_v2;
wire [127:0] sha1cpm_y_v3;
wire [31:0] sha1cpm_y_v4;
wire [31:0] sha1h_qnin_v1;
reg sha1m_v2_q;
reg sha1m_v3_q;
reg sha1m_v4_q;
reg sha1p_v2_q;
reg sha1p_v3_q;
reg sha1p_v4_q;
wire [127:0] sha1su0_q_v1;
reg sha1su0_v2_q;
wire [127:0] sha1su1_qdin_v1;
wire [127:0] sha1su1_qnin_v1;
wire [127:0] sha256_xin_v1;
wire [127:0] sha256_yin_v1;
wire [31:0] sha256_zin_v1;
reg sha256h2_h_v4_q;
reg sha256h2_l_v4_q;
reg sha256h2_v2_q;
reg sha256h2_v3_q;
reg sha256h2_v4_q;
reg sha256h_h_v4_q;
reg sha256h_l_v4_q;
reg sha256h_v2_q;
reg sha256h_v3_q;
reg sha256h_v4_q;
wire [127:0] sha256h_x_v1;
wire [127:0] sha256h_x_v2;
wire [127:0] sha256h_x_v3;
wire [127:0] sha256h_x_v4;
wire [127:0] sha256h_y_v1;
wire [127:0] sha256h_y_v2;
wire [127:0] sha256h_y_v3;
wire [127:0] sha256h_y_v4;
wire sha256hh2_v2;
wire sha256hh2_v3;
wire sha256hh2_v4;
wire [127:0] sha256su0_out_v1;
wire [127:0] sha256su0_qdin_v1;
wire [127:0] sha256su0_qnin_v1;
reg sha256su1_dup_x_v2_q;
reg sha256su1_dup_y_v2_q;
reg sha256su1_dup_z_v2_q;
reg sha256su1_h_v2_q;
reg sha256su1_l_v2_q;
reg sha256su1_v2_q;
wire [63:0] sha256su1_x_v1;
wire [63:0] sha256su1_x_v2;
reg sha_inst_h_v2_q;
reg sha_inst_l_v2_q;
wire sha_inst_v1;
reg sha_inst_v2_q;
wire short_pipe_out_v3_en;
wire [31:0] sigma0_v3;
wire [31:0] sigma0_v4;
wire [31:0] sigma1_v3;
wire [63:0] sum1c_v1;
wire [63:0] sum4c_v3;
wire [31:0] sum4c_v4;
wire [63:0] sum_2c4c_v2;
wire [31:0] sum_sha1cpm_v1;
wire [31:0] sum_sha1cpm_v2;
wire [31:0] sum_sha1cpm_v3;
wire [31:0] sum_sha1cpm_v4;
wire [63:0] sum_sha256h32_v1;
wire [63:0] sum_sha256h32_v2;
wire [63:0] sum_sha256h32_v3;
wire [31:0] sum_sha256h32_v4;
wire [31:0] sum_sha256su0_v1;
wire [63:0] sum_sha256su1_v1;
wire [63:0] sum_sha256su1_v2;
wire [63:0] sumnr1c_v1;
wire [63:0] sumnr4c_v3;
wire [31:0] sumnr4c_v4;
wire [63:0] sumnr_2c4c_v2;
wire [63:0] sumres_sha256su1_v2;
wire [31:0] tchoose_v3;
wire [31:0] tmajority_v3;
wire [31:0] tmajority_v4;
wire unused_cout1c2_v1;
wire unused_cout1c_v1;
wire unused_cout2_2c4c_v2;
wire unused_cout2_4c_v3;
wire unused_cout4c_v3;
wire unused_cout4c_v4;
wire unused_cout_2c4c_v2;
wire unused_cout_sha256su1h_v2;
wire unused_cout_sha256su1l_v2;
wire [32:0] x_fa2_c_v4;
wire [31:0] x_fa2_s_v4;
wire [127:0] x_v1;
wire [127:0] x_v2;
wire [127:0] x_v3;
wire [127:0] x_v4;
wire xprime_carry;
wire [127:96] xprime_v4;
wire [32:0] xy_fa0_c_v3;
wire [31:0] xy_fa0_s_v3;
wire [32:0] xy_fa1_c_v3;
wire [31:0] xy_fa1_c_v4;
wire [31:0] xy_fa1_s_v3;
wire [31:0] xy_fa1_s_v4;
wire [32:0] y_fa2_c_v4;
wire [31:0] y_fa2_s_v4;
wire [32:0] y_fa3_c_v4;
wire [31:0] y_fa3_s_v4;
wire [127:0] y_v1;
wire [127:0] y_v2;
wire [127:0] y_v3;
wire [127:0] y_v4;
wire [127:96] yprime_v4;
wire [127:0] z_v1;
wire [95:0] z_v2;
wire [63:0] z_v3;
wire [31:0] z_v4;
assign ival_en = ival_v1_q | ival_v2_q | ival_v3_q;
assign short_pipe_out_v3_en = sha_inst_v2_q | sha1su0_v2_q | sha256su1_v2_q;
assign ival_v2_4latency = ~short_pipe_out_v3_en & ival_v2_q;
assign ival_v1_or_v2 = ival_v1_q | ival_v2_q;
always_ff @(posedge clk or posedge reset)
begin: u_ival_v2_q
if (reset == 1'b1)
ival_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
`ifdef HERCULESAE_XPROP_FLOP
else if (reset == 1'b0 && ival_en == 1'b1)
ival_v2_q <= `HERCULESAE_DFF_DELAY ival_v1_q;
else if (reset == 1'b0 && ival_en == 1'b0)
begin
end
else
ival_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
`else
else if (ival_en == 1'b1)
ival_v2_q <= `HERCULESAE_DFF_DELAY ival_v1_q;
`endif
end
always_ff @(posedge clk or posedge reset)
begin: u_ival_v3_q
if (reset == 1'b1)
ival_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
`ifdef HERCULESAE_XPROP_FLOP
else if (reset == 1'b0 && ival_en == 1'b1)
ival_v3_q <= `HERCULESAE_DFF_DELAY ival_v2_4latency;
else if (reset == 1'b0 && ival_en == 1'b0)
begin
end
else
ival_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
`else
else if (ival_en == 1'b1)
ival_v3_q <= `HERCULESAE_DFF_DELAY ival_v2_4latency;
`endif
end
always_ff @(posedge clk or posedge reset)
begin: u_sha1c_v2_q_grp
if (reset == 1'b1) begin
sha1c_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha1p_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha1m_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256h2_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha1cpm_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha_inst_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha_inst_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha_inst_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha1su0_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256su1_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256su1_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256su1_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256su1_dup_x_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256su1_dup_y_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256su1_dup_z_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
end
`ifdef HERCULESAE_XPROP_FLOP
else if (reset == 1'b0 && ival_v1_q == 1'b1) begin
sha1c_v2_q <= `HERCULESAE_DFF_DELAY sha1c_v1_q;
sha1p_v2_q <= `HERCULESAE_DFF_DELAY sha1p_v1_q;
sha1m_v2_q <= `HERCULESAE_DFF_DELAY sha1m_v1_q;
sha256h_v2_q <= `HERCULESAE_DFF_DELAY sha256h_v1_q;
sha256h2_v2_q <= `HERCULESAE_DFF_DELAY sha256h2_v1_q;
sha1cpm_v2_q <= `HERCULESAE_DFF_DELAY sha1cpm_v1_q;
sha_inst_v2_q <= `HERCULESAE_DFF_DELAY sha_inst_v1;
sha_inst_h_v2_q <= `HERCULESAE_DFF_DELAY sha_inst_v1;
sha_inst_l_v2_q <= `HERCULESAE_DFF_DELAY sha_inst_v1;
sha1su0_v2_q <= `HERCULESAE_DFF_DELAY sha1su0_v1_q;
sha256su1_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
sha256su1_h_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
sha256su1_l_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
sha256su1_dup_x_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
sha256su1_dup_y_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
sha256su1_dup_z_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
end
else if (reset == 1'b0 && ival_v1_q == 1'b0)
begin
end
else begin
sha1c_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha1p_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha1m_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256h2_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha1cpm_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha_inst_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha_inst_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha_inst_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha1su0_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256su1_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256su1_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256su1_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256su1_dup_x_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256su1_dup_y_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256su1_dup_z_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
end
`else
else if (ival_v1_q == 1'b1) begin
sha1c_v2_q <= `HERCULESAE_DFF_DELAY sha1c_v1_q;
sha1p_v2_q <= `HERCULESAE_DFF_DELAY sha1p_v1_q;
sha1m_v2_q <= `HERCULESAE_DFF_DELAY sha1m_v1_q;
sha256h_v2_q <= `HERCULESAE_DFF_DELAY sha256h_v1_q;
sha256h2_v2_q <= `HERCULESAE_DFF_DELAY sha256h2_v1_q;
sha1cpm_v2_q <= `HERCULESAE_DFF_DELAY sha1cpm_v1_q;
sha_inst_v2_q <= `HERCULESAE_DFF_DELAY sha_inst_v1;
sha_inst_h_v2_q <= `HERCULESAE_DFF_DELAY sha_inst_v1;
sha_inst_l_v2_q <= `HERCULESAE_DFF_DELAY sha_inst_v1;
sha1su0_v2_q <= `HERCULESAE_DFF_DELAY sha1su0_v1_q;
sha256su1_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
sha256su1_h_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
sha256su1_l_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
sha256su1_dup_x_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
sha256su1_dup_y_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
sha256su1_dup_z_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
end
`endif
end
always_ff @(posedge clk or posedge reset)
begin: u_sha1c_v3_q_grp
if (reset == 1'b1) begin
sha1c_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha1p_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha1m_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha1cpm_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256h_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256h2_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
end
`ifdef HERCULESAE_XPROP_FLOP
else if (reset == 1'b0 && ival_v2_4latency == 1'b1) begin
sha1c_v3_q <= `HERCULESAE_DFF_DELAY sha1c_v2_q;
sha1p_v3_q <= `HERCULESAE_DFF_DELAY sha1p_v2_q;
sha1m_v3_q <= `HERCULESAE_DFF_DELAY sha1m_v2_q;
sha1cpm_v3_q <= `HERCULESAE_DFF_DELAY sha1cpm_v2_q;
sha256h_v3_q <= `HERCULESAE_DFF_DELAY sha256h_v2_q;
sha256h2_v3_q <= `HERCULESAE_DFF_DELAY sha256h2_v2_q;
end
else if (reset == 1'b0 && ival_v2_4latency == 1'b0)
begin
end
else begin
sha1c_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha1p_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha1m_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha1cpm_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256h_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256h2_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
end
`else
else if (ival_v2_4latency == 1'b1) begin
sha1c_v3_q <= `HERCULESAE_DFF_DELAY sha1c_v2_q;
sha1p_v3_q <= `HERCULESAE_DFF_DELAY sha1p_v2_q;
sha1m_v3_q <= `HERCULESAE_DFF_DELAY sha1m_v2_q;
sha1cpm_v3_q <= `HERCULESAE_DFF_DELAY sha1cpm_v2_q;
sha256h_v3_q <= `HERCULESAE_DFF_DELAY sha256h_v2_q;
sha256h2_v3_q <= `HERCULESAE_DFF_DELAY sha256h2_v2_q;
end
`endif
end
always_ff @(posedge clk or posedge reset)
begin: u_sha1c_v4_q_grp
if (reset == 1'b1) begin
sha1c_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha1p_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha1m_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha1cpm_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha1cpm_h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha1cpm_l_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256h_h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256h_l_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256h2_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256h2_h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256h2_l_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
end
`ifdef HERCULESAE_XPROP_FLOP
else if (reset == 1'b0 && ival_v3_q == 1'b1) begin
sha1c_v4_q <= `HERCULESAE_DFF_DELAY sha1c_v3_q;
sha1p_v4_q <= `HERCULESAE_DFF_DELAY sha1p_v3_q;
sha1m_v4_q <= `HERCULESAE_DFF_DELAY sha1m_v3_q;
sha1cpm_v4_q <= `HERCULESAE_DFF_DELAY sha1cpm_v3_q;
sha1cpm_h_v4_q <= `HERCULESAE_DFF_DELAY sha1cpm_v3_q;
sha1cpm_l_v4_q <= `HERCULESAE_DFF_DELAY sha1cpm_v3_q;
sha256h_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q;
sha256h_h_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q;
sha256h_l_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q;
sha256h2_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q;
sha256h2_h_v4_q <= `HERCULESAE_DFF_DELAY sha256h2_v3_q;
sha256h2_l_v4_q <= `HERCULESAE_DFF_DELAY sha256h2_v3_q;
end
else if (reset == 1'b0 && ival_v3_q == 1'b0)
begin
end
else begin
sha1c_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha1p_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha1m_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha1cpm_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha1cpm_h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha1cpm_l_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256h_h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256h_l_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256h2_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256h2_h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256h2_l_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
end
`else
else if (ival_v3_q == 1'b1) begin
sha1c_v4_q <= `HERCULESAE_DFF_DELAY sha1c_v3_q;
sha1p_v4_q <= `HERCULESAE_DFF_DELAY sha1p_v3_q;
sha1m_v4_q <= `HERCULESAE_DFF_DELAY sha1m_v3_q;
sha1cpm_v4_q <= `HERCULESAE_DFF_DELAY sha1cpm_v3_q;
sha1cpm_h_v4_q <= `HERCULESAE_DFF_DELAY sha1cpm_v3_q;
sha1cpm_l_v4_q <= `HERCULESAE_DFF_DELAY sha1cpm_v3_q;
sha256h_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q;
sha256h_h_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q;
sha256h_l_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q;
sha256h2_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q;
sha256h2_h_v4_q <= `HERCULESAE_DFF_DELAY sha256h2_v3_q;
sha256h2_l_v4_q <= `HERCULESAE_DFF_DELAY sha256h2_v3_q;
end
`endif
end
assign sha1_v1 = sha1h_v1_q | sha1su0_v1_q | sha1su1_v1_q;
assign sha1h_qnin_v1[ 31:0] = {32{sha1h_v1_q}} & opa_v1[ 31:0];
assign sha1su1_qdin_v1[127:0] = {128{sha1su0_v1_q | sha1su1_v1_q}} & opb_v1[127:0];
assign sha1su1_qnin_v1[127:0] = {128{sha1su0_v1_q | sha1su1_v1_q}} & opa_v1[127:0];
assign sha1su0_q_v1[127:0] = {128{sha1su0_v1_q}} & opc_v1[127:0];
herculesae_vx_sha1 u_sha1(
.sha1h_v1_i (sha1h_v1_q),
.sha1su0_v1_i (sha1su0_v1_q),
.sha1su1_v1_i (sha1su1_v1_q),
.sha1h_qn (sha1h_qnin_v1[31:0]),
.sha1su0_qd (sha1su0_q_v1[127:0]),
.sha1su1_qd (sha1su1_qdin_v1[127:0]),
.sha1su1_qn (sha1su1_qnin_v1[127:0]),
.sha1_v1_o (sha1_out_v1[127:0]));
assign sha256su0_qdin_v1[127:0] = {128{sha256su0_v1_q}} & opb_v1[127:0];
assign sha256su0_qnin_v1[127:0] = {128{sha256su0_v1_q}} & opa_v1[127:0];
herculesae_vx_sha256su0 u_sha256su0(
.qd (sha256su0_qdin_v1[127:0]),
.qn (sha256su0_qnin_v1[ 31:0]),
.sumd (sumnr1c_v1[31:0]),
.suma (sum_sha256su0_v1[31:0]),
.sumb (carry_sha256su0_v1[31:0]),
.d (sha256su0_out_v1[127:0]));
herculesae_vx_sha256su1 u_sha256su1_v1(
.sha256su1_x_op (sha256su1_dup_x_v1_q),
.sha256su1_y_op (sha256su1_dup_y_v1_q),
.sha256su1_z_op (sha256su1_dup_z_v1_q),
.x (opc_v1[63:0]),
.y (opa_v1[95:32]),
.z (opb_v1[127:64]),
.sumnr (sumnr1c_v1[63:0]),
.sum_3to2 (sum_sha256su1_v1[63:0]),
.carry_3to2 (carry_sha256su1_v1[63:0]),
.newx (sha256su1_x_v1[63:0]));
assign x_v1[127:0] = opc_v1[127:0];
assign y_v1[127:0] = opa_v1[127:0];
assign z_v1[127:0] = opb_v1[127:0];
assign sha1_xin_v1[127:0] = {128{sha1cpm_v1_q}} & x_v1[127:0];
assign sha1_yin_v1[31:0] = { 32{sha1cpm_v1_q}} & y_v1[31:0];
assign sha1_zin_v1[31:0] = { 32{sha1cpm_v1_q}} & z_v1[31:0];
herculesae_vx_sha1cpm u_sha1cpm_v1(
.choose (sha1c_v1_q),
.parity (sha1p_v1_q),
.majority (sha1m_v1_q),
.cpm (sha1cpm_v1_q),
.x (sha1_xin_v1[127:0]),
.y (sha1_yin_v1[31:0]),
.z (sha1_zin_v1[31:0]),
.t2 (sumnr1c_v1[31:0]),
.fa1_s (sum_sha1cpm_v1[31:0]),
.fa1_c (carry_sha1cpm_v1[31:0]),
.newx (sha1cpm_x_v1[127:0]),
.newy (sha1cpm_y_v1[31:0]));
assign sha1cpm_y_v1[127:32] = {96{sha1cpm_v1_q}} & y_v1[127:32];
assign sha256_xin_v1[127:0] = {128{sha256hh2_v1_q}} & x_v1[127:0];
assign sha256_yin_v1[127:0] = {128{sha256hh2_v1_q}} & y_v1[127:0];
assign sha256_zin_v1[ 31:0] = {32{ sha256hh2_v1_q}} & z_v1[31:0];
herculesae_vx_sha256h32 u_sha256h32_v1(
.x (sha256_xin_v1[127:0]),
.y (sha256_yin_v1[127:0]),
.z (sha256_zin_v1[31:0]),
.sumnr (sumnr1c_v1[63:0]),
.sum (sum_sha256h32_v1[63:0]),
.carry (carry_sha256h32_v1[63:0]),
.newx (sha256h_x_v1[127:0]),
.newy (sha256h_y_v1[127:0]));
assign sum1c_v1[31:0] = {32{sha256su0_v1_q}} & sum_sha256su0_v1[31:0]
| {32{sha1cpm_v1_q }} & sum_sha1cpm_v1[31:0]
| {32{sha256hh2_v1_q}} & sum_sha256h32_v1[31:0]
| {32{sha256su1_v1_q}} & sum_sha256su1_v1[31:0];
assign carry1c_v1[31:0] = {32{sha256su0_v1_q}} & carry_sha256su0_v1[31:0]
| {32{sha1cpm_v1_q }} & carry_sha1cpm_v1[31:0]
| {32{sha256hh2_v1_q}} & carry_sha256h32_v1[31:0]
| {32{sha256su1_v1_q}} & carry_sha256su1_v1[31:0];
assign {unused_cout1c_v1, sumnr1c_v1[31:0]} = sum1c_v1[31:0] + carry1c_v1[31:0] + {{31{1'b0}}, 1'b0};
assign sum1c_v1[63:32] = {32{sha256hh2_v1_q}} & sum_sha256h32_v1[63:32]
| {32{sha256su1_v1_q}} & sum_sha256su1_v1[63:32];
assign carry1c_v1[63:32] = {32{sha256hh2_v1_q}} & carry_sha256h32_v1[63:32]
| {32{sha256su1_v1_q}} & carry_sha256su1_v1[63:32];
assign {unused_cout1c2_v1, sumnr1c_v1[63:32]} = sum1c_v1[63:32] + carry1c_v1[63:32] + {{31{1'b0}}, 1'b0};
assign sha_inst_v1 = sha1h_v1_q | sha1su0_v1_q | sha1su1_v1_q | sha256su0_v1_q;
assign block_opa_passthrough = sha_inst_v1 | sha256su1_v1_q |
sha256hh2_v1_q | sha1cpm_v1_q;
assign newa_v1[127:0] = ({128{sha1cpm_v1_q }} & sha1cpm_y_v1[127:0])
| ({128{sha256hh2_v1_q}} & sha256h_y_v1[127:0])
| ({128{sha256su1_v1_q}} & {opb_v1[31:0],opa_v1[127:32]})
| ({128{sha256su0_v1_q}} & sha256su0_out_v1[127:0])
| ({128{sha1_v1}} & sha1_out_v1[127:0])
| ({128{~(block_opa_passthrough)}} & opa_v1[127:0]);
assign newb_v1[127:0] = ({128{sha1cpm_v1_q }} & sha1cpm_x_v1[127:0])
| ({128{sha256hh2_v1_q}} & sha256h_x_v1[127:0])
| ({128{sha256su1_v1_q}} & {opc_v1[127:64], sha256su1_x_v1[63:0]});
assign newc_v1[95:0] = opb_v1[127:32];
always_ff @(posedge clk or posedge reset)
begin: u_opa_v2_q_127_0_grp
if (reset == 1'b1) begin
opa_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}};
opb_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}};
opc_v2_q[95:0] <= `HERCULESAE_DFF_DELAY {96{1'b0}};
end
`ifdef HERCULESAE_XPROP_FLOP
else if (reset == 1'b0 && ival_v1_q == 1'b1) begin
opa_v2_q[127:0] <= `HERCULESAE_DFF_DELAY newa_v1[127:0];
opb_v2_q[127:0] <= `HERCULESAE_DFF_DELAY newb_v1[127:0];
opc_v2_q[95:0] <= `HERCULESAE_DFF_DELAY newc_v1[95:0];
end
else if (reset == 1'b0 && ival_v1_q == 1'b0)
begin
end
else begin
opa_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}};
opb_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}};
opc_v2_q[95:0] <= `HERCULESAE_DFF_DELAY {96{1'bx}};
end
`else
else if (ival_v1_q == 1'b1) begin
opa_v2_q[127:0] <= `HERCULESAE_DFF_DELAY newa_v1[127:0];
opb_v2_q[127:0] <= `HERCULESAE_DFF_DELAY newb_v1[127:0];
opc_v2_q[95:0] <= `HERCULESAE_DFF_DELAY newc_v1[95:0];
end
`endif
end
assign x_v2[127:0] = opb_v2_q[127:0];
assign y_v2[127:0] = opa_v2_q[127:0];
assign z_v2[95:0] = opc_v2_q[95:0];
herculesae_vx_sha256su1 u_sha256su1_v2(
.sha256su1_x_op (sha256su1_dup_x_v2_q),
.sha256su1_y_op (sha256su1_dup_y_v2_q),
.sha256su1_z_op (sha256su1_dup_z_v2_q),
.x (x_v2[127:64]),
.y (y_v2[127:64]),
.z (x_v2[63:0]),
.sumnr (sumres_sha256su1_v2[63:0]),
.sum_3to2 (sum_sha256su1_v2[63:0]),
.carry_3to2 (carry_sha256su1_v2[63:0]),
.newx (sha256su1_x_v2[63:0]));
herculesae_vx_sha1cpm u_sha1cpm_v2(
.choose (sha1c_v2_q),
.parity (sha1p_v2_q),
.majority (sha1m_v2_q),
.cpm (sha1cpm_v2_q),
.x (x_v2[127:0]),
.y (y_v2[31:0]),
.z (z_v2[31:0]),
.t2 (sumnr_2c4c_v2[31:0]),
.fa1_s (sum_sha1cpm_v2[31:0]),
.fa1_c (carry_sha1cpm_v2[31:0]),
.newx (sha1cpm_x_v2[127:0]),
.newy (sha1cpm_y_v2[31:0]));
assign sha1cpm_y_v2[127:32] = y_v2[127:32];
herculesae_vx_sha256h32 u_sha256h32_v2(
.x (x_v2[127:0]),
.y (y_v2[127:0]),
.z (z_v2[31:0]),
.sumnr (sumnr_2c4c_v2[63:0]),
.sum (sum_sha256h32_v2[63:0]),
.carry (carry_sha256h32_v2[63:0]),
.newx (sha256h_x_v2[127:0]),
.newy (sha256h_y_v2[127:0]));
assign sha256hh2_v2 = sha256h_v2_q | sha256h2_v2_q;
assign sum_2c4c_v2[31:0] = {32{sha1cpm_v2_q}} & sum_sha1cpm_v2[31:0] |
{32{sha256hh2_v2}} & sum_sha256h32_v2[31:0];
assign carry_2c4c_v2[31:0] = {32{sha1cpm_v2_q}} & carry_sha1cpm_v2[31:0] |
{32{sha256hh2_v2}} & carry_sha256h32_v2[31:0];
assign {unused_cout_2c4c_v2, sumnr_2c4c_v2[31:0]} = sum_2c4c_v2[31:0] + carry_2c4c_v2[31:0] + {{31{1'b0}}, 1'b0};
assign sum_2c4c_v2[63:32] = {32{sha256hh2_v2}} & sum_sha256h32_v2[63:32];
assign carry_2c4c_v2[63:32] = {32{sha256hh2_v2}} & carry_sha256h32_v2[63:32];
assign {unused_cout2_2c4c_v2, sumnr_2c4c_v2[63:32]} = sum_2c4c_v2[63:32] + carry_2c4c_v2[63:32] + {{31{1'b0}}, 1'b0};
assign {unused_cout_sha256su1l_v2, sumres_sha256su1_v2[31:0]} = sum_sha256su1_v2[31:0] + carry_sha256su1_v2[31:0] + {{31{1'b0}}, 1'b0};
assign {unused_cout_sha256su1h_v2, sumres_sha256su1_v2[63:32]} = sum_sha256su1_v2[63:32] + carry_sha256su1_v2[63:32] + {{31{1'b0}}, 1'b0};
assign newb_v2[127:0] = ({128{sha1cpm_v2_q}} & sha1cpm_x_v2[127:0])
| ({128{sha256hh2_v2}} & sha256h_x_v2[127:0]);
assign newa_v2[127:0] = ({128{sha1cpm_v2_q}} & sha1cpm_y_v2[127:0])
| ({128{sha256hh2_v2}} & sha256h_y_v2[127:0]);
assign cryptout_v2[127:64] = ({64{sha256su1_h_v2_q}} & sha256su1_x_v2[63:0])
| ({64{sha_inst_h_v2_q}} & opa_v2_q[127:64]);
assign cryptout_v2[63:0] = ({64{sha256su1_l_v2_q}} & opb_v2_q[63:0])
| ({64{sha_inst_l_v2_q}} & opa_v2_q[63:0]);
always_ff @(posedge clk or posedge reset)
begin: u_opa_v3_q_127_0_grp
if (reset == 1'b1) begin
opa_v3_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}};
opb_v3_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}};
opc_v3_q[63:0] <= `HERCULESAE_DFF_DELAY {64{1'b0}};
end
`ifdef HERCULESAE_XPROP_FLOP
else if (reset == 1'b0 && ival_v2_4latency == 1'b1) begin
opa_v3_q[127:0] <= `HERCULESAE_DFF_DELAY newa_v2[127:0];
opb_v3_q[127:0] <= `HERCULESAE_DFF_DELAY newb_v2[127:0];
opc_v3_q[63:0] <= `HERCULESAE_DFF_DELAY opc_v2_q[95:32];
end
else if (reset == 1'b0 && ival_v2_4latency == 1'b0)
begin
end
else begin
opa_v3_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}};
opb_v3_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}};
opc_v3_q[63:0] <= `HERCULESAE_DFF_DELAY {64{1'bx}};
end
`else
else if (ival_v2_4latency == 1'b1) begin
opa_v3_q[127:0] <= `HERCULESAE_DFF_DELAY newa_v2[127:0];
opb_v3_q[127:0] <= `HERCULESAE_DFF_DELAY newb_v2[127:0];
opc_v3_q[63:0] <= `HERCULESAE_DFF_DELAY opc_v2_q[95:32];
end
`endif
end
assign x_v3[127:0] = opb_v3_q[127:0];
assign y_v3[127:0] = opa_v3_q[127:0];
assign z_v3[63:0] = opc_v3_q[63:0];
herculesae_vx_sha1cpm u_sha1cpm_v3(
.choose (sha1c_v3_q),
.parity (sha1p_v3_q),
.majority (sha1m_v3_q),
.cpm (sha1cpm_v3_q),
.x (x_v3[127:0]),
.y (y_v3[31:0]),
.z (z_v3[31:0]),
.t2 (sumnr4c_v3[31:0]),
.fa1_s (sum_sha1cpm_v3[31:0]),
.fa1_c (carry_sha1cpm_v3[31:0]),
.newx (sha1cpm_x_v3[127:0]),
.newy (sha1cpm_y_v3[31:0]));
assign sha1cpm_y_v3[127:32] = y_v3[127:32];
herculesae_vx_sha256h32 u_sha256h32_v3(
.x (x_v3[127:0]),
.y (y_v3[127:0]),
.z (z_v3[31:0]),
.sumnr (sumnr4c_v3[63:0]),
.sum (sum_sha256h32_v3[63:0]),
.carry (carry_sha256h32_v3[63:0]),
.newx (sha256h_x_v3[127:0]),
.newy (sha256h_y_v3[127:0]));
assign tchoose_v3[31:0] = (sha256h_y_v3[31:0] & sha256h_y_v3[63:32]) |
(~sha256h_y_v3[31:0] & sha256h_y_v3[95:64]);
assign tmajority_v3[31:0] = (sha256h_x_v3[31:0] & sha256h_x_v3[63:32]) |
(sha256h_x_v3[31:0] & sha256h_x_v3[95:64]) |
(sha256h_x_v3[63:32] & sha256h_x_v3[95:64]);
assign sigma0_v3[31:0] = {sha256h_x_v3[1:0], sha256h_x_v3[31:2]}
^ {sha256h_x_v3[12:0], sha256h_x_v3[31:13]}
^ {sha256h_x_v3[21:0], sha256h_x_v3[31:22]};
assign sigma1_v3[31:0] = {sha256h_y_v3[5:0], sha256h_y_v3[31:6]}
^ {sha256h_y_v3[10:0], sha256h_y_v3[31:11]}
^ {sha256h_y_v3[24:0], sha256h_y_v3[31:25]};
assign xy_fa0_s_v3[31:0] = sha256h_y_v3[127:96] ^ z_v3[63:32] ^ tchoose_v3[31:0];
assign xy_fa0_c_v3[32:0] = {sha256h_y_v3[127:96] & z_v3[63:32] | tchoose_v3[31:0] &
(sha256h_y_v3[127:96] | z_v3[63:32]), 1'b0};
assign xy_fa1_s_v3[31:0] = xy_fa0_s_v3[31:0] ^ xy_fa0_c_v3[31:0] ^ sigma1_v3[31:0];
assign xy_fa1_c_v3[32:0] = {xy_fa0_s_v3[31:0] & xy_fa0_c_v3[31:0] | sigma1_v3[31:0] &
(xy_fa0_s_v3[31:0] | xy_fa0_c_v3[31:0]), 1'b0};
assign sha256hh2_v3 = sha256h_v3_q | sha256h2_v3_q;
assign sum4c_v3[31:0] = {32{sha1cpm_v3_q}} & sum_sha1cpm_v3[31:0] |
{32{sha256hh2_v3}} & sum_sha256h32_v3[31:0];
assign carry4c_v3[31:0] = {32{sha1cpm_v3_q}} & carry_sha1cpm_v3[31:0] |
{32{sha256hh2_v3}} & carry_sha256h32_v3[31:0];
assign {unused_cout4c_v3, sumnr4c_v3[31:0]} = sum4c_v3[31:0] + carry4c_v3[31:0] + {{31{1'b0}}, 1'b0};
assign sum4c_v3[63:32] = sum_sha256h32_v3[63:32];
assign carry4c_v3[63:32] = carry_sha256h32_v3[63:32];
assign {unused_cout2_4c_v3, sumnr4c_v3[63:32]} = sum4c_v3[63:32] + carry4c_v3[63:32] + {{31{1'b0}}, 1'b0};
assign newa_v3[127:0] = ({128{sha1cpm_v3_q}} & sha1cpm_y_v3[127:0])
| ({128{sha256h_v3_q}} & {sigma0_v3[31:0], tmajority_v3[31:0],
xy_fa1_s_v3[31:0], xy_fa1_c_v3[31:0]})
| ({128{sha256h2_v3_q}} & {sigma0_v3[31:0],tmajority_v3[31:0],
xy_fa1_s_v3[31:0],xy_fa1_c_v3[31:0]});
assign newb_v3[127:0] = ({128{sha1cpm_v3_q}} & sha1cpm_x_v3[127:0])
| ({128{sha256h_v3_q }} & sha256h_x_v3[127:0])
| ({128{sha256h2_v3_q }} & {sha256h_x_v3[127:96], sha256h_y_v3[95:0]});
always_ff @(posedge clk or posedge reset)
begin: u_opb_v4_q_127_0_grp
if (reset == 1'b1) begin
opb_v4_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}};
opa_v4_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}};
opc_v4_q[31:0] <= `HERCULESAE_DFF_DELAY {32{1'b0}};
end
`ifdef HERCULESAE_XPROP_FLOP
else if (reset == 1'b0 && ival_v3_q == 1'b1) begin
opb_v4_q[127:0] <= `HERCULESAE_DFF_DELAY newb_v3[127:0];
opa_v4_q[127:0] <= `HERCULESAE_DFF_DELAY newa_v3[127:0];
opc_v4_q[31:0] <= `HERCULESAE_DFF_DELAY opc_v3_q[63:32];
end
else if (reset == 1'b0 && ival_v3_q == 1'b0)
begin
end
else begin
opb_v4_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}};
opa_v4_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}};
opc_v4_q[31:0] <= `HERCULESAE_DFF_DELAY {32{1'bx}};
end
`else
else if (ival_v3_q == 1'b1) begin
opb_v4_q[127:0] <= `HERCULESAE_DFF_DELAY newb_v3[127:0];
opa_v4_q[127:0] <= `HERCULESAE_DFF_DELAY newa_v3[127:0];
opc_v4_q[31:0] <= `HERCULESAE_DFF_DELAY opc_v3_q[63:32];
end
`endif
end
assign x_v4[127:0] = opb_v4_q[127:0];
assign y_v4[127:0] = opa_v4_q[127:0];
assign z_v4[31:0] = opc_v4_q[31:0];
herculesae_vx_sha1cpm u_sha1cpm_v4(
.choose (sha1c_v4_q),
.parity (sha1p_v4_q),
.majority (sha1m_v4_q),
.cpm (sha1cpm_v4_q),
.x (x_v4[127:0]),
.y (y_v4[31:0]),
.z (z_v4[31:0]),
.t2 (sumnr4c_v4[31:0]),
.fa1_s (sum_sha1cpm_v4[31:0]),
.fa1_c (carry_sha1cpm_v4[31:0]),
.newx (sha1cpm_x_v4[127:0]),
.newy (sha1cpm_y_v4[31:0]));
assign sigma0_v4[31:0] = y_v4[127:96];
assign tmajority_v4[31:0] = y_v4[95:64];
assign xy_fa1_s_v4[31:0] = y_v4[63:32];
assign xy_fa1_c_v4[31:0] = y_v4[31:0];
assign x_fa2_s_v4[31:0] = xy_fa1_s_v4[31:0] ^ xy_fa1_c_v4[31:0] ^ x_v4[127:96];
assign x_fa2_c_v4[32:0] = {xy_fa1_s_v4[31:0] & xy_fa1_c_v4[31:0] |
x_v4[127:96] & (xy_fa1_s_v4[31:0] |
xy_fa1_c_v4[31:0]), 1'b0};
assign y_fa2_s_v4[31:0] = sigma0_v4[31:0] ^ tmajority_v4[31:0] ^ xy_fa1_c_v4[31:0];
assign y_fa2_c_v4[32:0] = {sigma0_v4[31:0] & tmajority_v4[31:0] |
xy_fa1_c_v4[31:0] & (sigma0_v4[31:0] |
tmajority_v4[31:0]), 1'b0};
assign y_fa3_s_v4[31:0] = y_fa2_s_v4[31:0] ^ y_fa2_c_v4[31:0] ^ xy_fa1_s_v4[31:0];
assign y_fa3_c_v4[32:0] = {y_fa2_s_v4[31:0] & y_fa2_c_v4[31:0] |
xy_fa1_s_v4[31:0] & (y_fa2_s_v4[31:0] |
y_fa2_c_v4[31:0]), 1'b0};
assign {xprime_carry, xprime_v4[127:96]} = x_fa2_s_v4[31:0] + x_fa2_c_v4[31:0] + {{31{1'b0}}, 1'b0};
assign sha256hh2_v4 = sha256h_v4_q | sha256h2_v4_q;
assign sum_sha256h32_v4[31:0] = y_fa3_s_v4[31:0];
assign carry_sha256h32_v4[31:0] = y_fa3_c_v4[31:0];
assign sum4c_v4[31:0] = {32{sha1cpm_v4_q}} & sum_sha1cpm_v4[31:0] |
{32{sha256hh2_v4}} & sum_sha256h32_v4[31:0];
assign carry4c_v4[31:0] = {32{sha1cpm_v4_q}} & carry_sha1cpm_v4[31:0] |
{32{sha256hh2_v4}} & carry_sha256h32_v4[31:0];
assign {unused_cout4c_v4, sumnr4c_v4[31:0]} = sum4c_v4[31:0] + carry4c_v4[31:0] + {{31{1'b0}}, 1'b0};
assign yprime_v4[127:96] = sumnr4c_v4[31:0];
assign newx_v4[127:0] = {x_v4[95:0], yprime_v4[127:96]};
assign newy_v4[127:0] = {x_v4[95:0], xprime_v4[127:96]};
assign sha256h_x_v4[127:0] = newx_v4[127:0];
assign sha256h_y_v4[127:0] = newy_v4[127:0];
assign cryptout_v4[63:0] = ({64{sha1cpm_l_v4_q}} & sha1cpm_x_v4[63:0])
| ({64{sha256h_l_v4_q}} & sha256h_x_v4[63:0])
| ({64{sha256h2_l_v4_q}} & sha256h_y_v4[63:0]);
assign cryptout_v4[127:64] = ({64{sha1cpm_h_v4_q}} & sha1cpm_x_v4[127:64])
| ({64{sha256h_h_v4_q}} & sha256h_x_v4[127:64])
| ({64{sha256h2_h_v4_q}} & sha256h_y_v4[127:64]);
assign crypt_active = ival_v1_or_v2;
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

257
Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_pmull.sv
View File

@ -1,257 +0,0 @@
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_pmull
(
input wire clk,
input wire reset,
input wire ival_v1_q,
input wire [63:0] opa_v1,
input wire [63:0] opb_v1,
output reg [127:0] pmullout_v2_q
);
wire [63:0] a_in;
wire [63:0] b_in;
wire [127:0] p_out;
wire [63:0] pp0;
wire [63:0] pp1;
wire [63:0] pp2;
wire [63:0] pp3;
wire [63:0] pp4;
wire [63:0] pp5;
wire [63:0] pp6;
wire [63:0] pp7;
wire [63:0] pp8;
wire [63:0] pp9;
wire [63:0] pp10;
wire [63:0] pp11;
wire [63:0] pp12;
wire [63:0] pp13;
wire [63:0] pp14;
wire [63:0] pp15;
wire [63:0] pp16;
wire [63:0] pp17;
wire [63:0] pp18;
wire [63:0] pp19;
wire [63:0] pp20;
wire [63:0] pp21;
wire [63:0] pp22;
wire [63:0] pp23;
wire [63:0] pp24;
wire [63:0] pp25;
wire [63:0] pp26;
wire [63:0] pp27;
wire [63:0] pp28;
wire [63:0] pp29;
wire [63:0] pp30;
wire [63:0] pp31;
wire [63:0] pp32;
wire [63:0] pp33;
wire [63:0] pp34;
wire [63:0] pp35;
wire [63:0] pp36;
wire [63:0] pp37;
wire [63:0] pp38;
wire [63:0] pp39;
wire [63:0] pp40;
wire [63:0] pp41;
wire [63:0] pp42;
wire [63:0] pp43;
wire [63:0] pp44;
wire [63:0] pp45;
wire [63:0] pp46;
wire [63:0] pp47;
wire [63:0] pp48;
wire [63:0] pp49;
wire [63:0] pp50;
wire [63:0] pp51;
wire [63:0] pp52;
wire [63:0] pp53;
wire [63:0] pp54;
wire [63:0] pp55;
wire [63:0] pp56;
wire [63:0] pp57;
wire [63:0] pp58;
wire [63:0] pp59;
wire [63:0] pp60;
wire [63:0] pp61;
wire [63:0] pp62;
wire [63:0] pp63;
wire [66:0] rednl0_0;
wire [66:0] rednl0_1;
wire [66:0] rednl0_2;
wire [66:0] rednl0_3;
wire [66:0] rednl0_4;
wire [66:0] rednl0_5;
wire [66:0] rednl0_6;
wire [66:0] rednl0_7;
wire [66:0] rednl0_8;
wire [66:0] rednl0_9;
wire [66:0] rednl0_10;
wire [66:0] rednl0_11;
wire [66:0] rednl0_12;
wire [66:0] rednl0_13;
wire [66:0] rednl0_14;
wire [66:0] rednl0_15;
wire [78:0] rednl1_0;
wire [78:0] rednl1_1;
wire [78:0] rednl1_2;
wire [78:0] rednl1_3;
assign a_in[63:0] = opa_v1[63:0];
assign b_in[63:0] = opb_v1[63:0];
assign pp0[63:0] = {64{a_in[ 0]}} & b_in[63:0];
assign pp1[63:0] = {64{a_in[ 1]}} & b_in[63:0];
assign pp2[63:0] = {64{a_in[ 2]}} & b_in[63:0];
assign pp3[63:0] = {64{a_in[ 3]}} & b_in[63:0];
assign pp4[63:0] = {64{a_in[ 4]}} & b_in[63:0];
assign pp5[63:0] = {64{a_in[ 5]}} & b_in[63:0];
assign pp6[63:0] = {64{a_in[ 6]}} & b_in[63:0];
assign pp7[63:0] = {64{a_in[ 7]}} & b_in[63:0];
assign pp8[63:0] = {64{a_in[ 8]}} & b_in[63:0];
assign pp9[63:0] = {64{a_in[ 9]}} & b_in[63:0];
assign pp10[63:0] = {64{a_in[10]}} & b_in[63:0];
assign pp11[63:0] = {64{a_in[11]}} & b_in[63:0];
assign pp12[63:0] = {64{a_in[12]}} & b_in[63:0];
assign pp13[63:0] = {64{a_in[13]}} & b_in[63:0];
assign pp14[63:0] = {64{a_in[14]}} & b_in[63:0];
assign pp15[63:0] = {64{a_in[15]}} & b_in[63:0];
assign pp16[63:0] = {64{a_in[16]}} & b_in[63:0];
assign pp17[63:0] = {64{a_in[17]}} & b_in[63:0];
assign pp18[63:0] = {64{a_in[18]}} & b_in[63:0];
assign pp19[63:0] = {64{a_in[19]}} & b_in[63:0];
assign pp20[63:0] = {64{a_in[20]}} & b_in[63:0];
assign pp21[63:0] = {64{a_in[21]}} & b_in[63:0];
assign pp22[63:0] = {64{a_in[22]}} & b_in[63:0];
assign pp23[63:0] = {64{a_in[23]}} & b_in[63:0];
assign pp24[63:0] = {64{a_in[24]}} & b_in[63:0];
assign pp25[63:0] = {64{a_in[25]}} & b_in[63:0];
assign pp26[63:0] = {64{a_in[26]}} & b_in[63:0];
assign pp27[63:0] = {64{a_in[27]}} & b_in[63:0];
assign pp28[63:0] = {64{a_in[28]}} & b_in[63:0];
assign pp29[63:0] = {64{a_in[29]}} & b_in[63:0];
assign pp30[63:0] = {64{a_in[30]}} & b_in[63:0];
assign pp31[63:0] = {64{a_in[31]}} & b_in[63:0];
assign pp32[63:0] = {64{a_in[32]}} & b_in[63:0];
assign pp33[63:0] = {64{a_in[33]}} & b_in[63:0];
assign pp34[63:0] = {64{a_in[34]}} & b_in[63:0];
assign pp35[63:0] = {64{a_in[35]}} & b_in[63:0];
assign pp36[63:0] = {64{a_in[36]}} & b_in[63:0];
assign pp37[63:0] = {64{a_in[37]}} & b_in[63:0];
assign pp38[63:0] = {64{a_in[38]}} & b_in[63:0];
assign pp39[63:0] = {64{a_in[39]}} & b_in[63:0];
assign pp40[63:0] = {64{a_in[40]}} & b_in[63:0];
assign pp41[63:0] = {64{a_in[41]}} & b_in[63:0];
assign pp42[63:0] = {64{a_in[42]}} & b_in[63:0];
assign pp43[63:0] = {64{a_in[43]}} & b_in[63:0];
assign pp44[63:0] = {64{a_in[44]}} & b_in[63:0];
assign pp45[63:0] = {64{a_in[45]}} & b_in[63:0];
assign pp46[63:0] = {64{a_in[46]}} & b_in[63:0];
assign pp47[63:0] = {64{a_in[47]}} & b_in[63:0];
assign pp48[63:0] = {64{a_in[48]}} & b_in[63:0];
assign pp49[63:0] = {64{a_in[49]}} & b_in[63:0];
assign pp50[63:0] = {64{a_in[50]}} & b_in[63:0];
assign pp51[63:0] = {64{a_in[51]}} & b_in[63:0];
assign pp52[63:0] = {64{a_in[52]}} & b_in[63:0];
assign pp53[63:0] = {64{a_in[53]}} & b_in[63:0];
assign pp54[63:0] = {64{a_in[54]}} & b_in[63:0];
assign pp55[63:0] = {64{a_in[55]}} & b_in[63:0];
assign pp56[63:0] = {64{a_in[56]}} & b_in[63:0];
assign pp57[63:0] = {64{a_in[57]}} & b_in[63:0];
assign pp58[63:0] = {64{a_in[58]}} & b_in[63:0];
assign pp59[63:0] = {64{a_in[59]}} & b_in[63:0];
assign pp60[63:0] = {64{a_in[60]}} & b_in[63:0];
assign pp61[63:0] = {64{a_in[61]}} & b_in[63:0];
assign pp62[63:0] = {64{a_in[62]}} & b_in[63:0];
assign pp63[63:0] = {64{a_in[63]}} & b_in[63:0];
assign rednl0_0[66:0] = { pp3[63:0], 3'b000} ^ {1'b0, pp2[63:0], 2'b00} ^ {2'b00, pp1[63:0], 1'b0} ^ {3'b000, pp0[63:0]};
assign rednl0_1[66:0] = { pp7[63:0], 3'b000} ^ {1'b0, pp6[63:0], 2'b00} ^ {2'b00, pp5[63:0], 1'b0} ^ {3'b000, pp4[63:0]};
assign rednl0_2[66:0] = {pp11[63:0], 3'b000} ^ {1'b0, pp10[63:0], 2'b00} ^ {2'b00, pp9[63:0], 1'b0} ^ {3'b000, pp8[63:0]};
assign rednl0_3[66:0] = {pp15[63:0], 3'b000} ^ {1'b0, pp14[63:0], 2'b00} ^ {2'b00, pp13[63:0], 1'b0} ^ {3'b000, pp12[63:0]};
assign rednl0_4[66:0] = {pp19[63:0], 3'b000} ^ {1'b0, pp18[63:0], 2'b00} ^ {2'b00, pp17[63:0], 1'b0} ^ {3'b000, pp16[63:0]};
assign rednl0_5[66:0] = {pp23[63:0], 3'b000} ^ {1'b0, pp22[63:0], 2'b00} ^ {2'b00, pp21[63:0], 1'b0} ^ {3'b000, pp20[63:0]};
assign rednl0_6[66:0] = {pp27[63:0], 3'b000} ^ {1'b0, pp26[63:0], 2'b00} ^ {2'b00, pp25[63:0], 1'b0} ^ {3'b000, pp24[63:0]};
assign rednl0_7[66:0] = {pp31[63:0], 3'b000} ^ {1'b0, pp30[63:0], 2'b00} ^ {2'b00, pp29[63:0], 1'b0} ^ {3'b000, pp28[63:0]};
assign rednl0_8[66:0] = {pp35[63:0], 3'b000} ^ {1'b0, pp34[63:0], 2'b00} ^ {2'b00, pp33[63:0], 1'b0} ^ {3'b000, pp32[63:0]};
assign rednl0_9[66:0] = {pp39[63:0], 3'b000} ^ {1'b0, pp38[63:0], 2'b00} ^ {2'b00, pp37[63:0], 1'b0} ^ {3'b000, pp36[63:0]};
assign rednl0_10[66:0] = {pp43[63:0], 3'b000} ^ {1'b0, pp42[63:0], 2'b00} ^ {2'b00, pp41[63:0], 1'b0} ^ {3'b000, pp40[63:0]};
assign rednl0_11[66:0] = {pp47[63:0], 3'b000} ^ {1'b0, pp46[63:0], 2'b00} ^ {2'b00, pp45[63:0], 1'b0} ^ {3'b000, pp44[63:0]};
assign rednl0_12[66:0] = {pp51[63:0], 3'b000} ^ {1'b0, pp50[63:0], 2'b00} ^ {2'b00, pp49[63:0], 1'b0} ^ {3'b000, pp48[63:0]};
assign rednl0_13[66:0] = {pp55[63:0], 3'b000} ^ {1'b0, pp54[63:0], 2'b00} ^ {2'b00, pp53[63:0], 1'b0} ^ {3'b000, pp52[63:0]};
assign rednl0_14[66:0] = {pp59[63:0], 3'b000} ^ {1'b0, pp58[63:0], 2'b00} ^ {2'b00, pp57[63:0], 1'b0} ^ {3'b000, pp56[63:0]};
assign rednl0_15[66:0] = {pp63[63:0], 3'b000} ^ {1'b0, pp62[63:0], 2'b00} ^ {2'b00, pp61[63:0], 1'b0} ^ {3'b000, pp60[63:0]};
assign rednl1_0[78:0] = { rednl0_3[66:0], 12'h000} ^ {4'h0, rednl0_2[66:0], 8'h00} ^ {8'h00, rednl0_1[66:0], 4'h0} ^ {12'h000, rednl0_0[66:0]};
assign rednl1_1[78:0] = { rednl0_7[66:0], 12'h000} ^ {4'h0, rednl0_6[66:0], 8'h00} ^ {8'h00, rednl0_5[66:0], 4'h0} ^ {12'h000, rednl0_4[66:0]};
assign rednl1_2[78:0] = {rednl0_11[66:0], 12'h000} ^ {4'h0, rednl0_10[66:0], 8'h00} ^ {8'h00, rednl0_9[66:0], 4'h0} ^ {12'h000, rednl0_8[66:0]};
assign rednl1_3[78:0] = {rednl0_15[66:0], 12'h000} ^ {4'h0, rednl0_14[66:0], 8'h00} ^ {8'h00, rednl0_13[66:0], 4'h0} ^ {12'h000, rednl0_12[66:0]};
assign p_out[15: 0] = rednl1_0[15: 0];
assign p_out[31: 16] = rednl1_1[15: 0] ^ rednl1_0[31:16];
assign p_out[47: 32] = rednl1_2[15: 0] ^ rednl1_1[31:16] ^ rednl1_0[47:32];
assign p_out[78: 48] = rednl1_3[30: 0] ^ rednl1_2[46:16] ^ rednl1_1[62:32] ^ rednl1_0[78:48];
assign p_out[94: 79] = rednl1_3[46:31] ^ rednl1_2[62:47] ^ rednl1_1[78:63];
assign p_out[110: 95] = rednl1_3[62:47] ^ rednl1_2[78:63];
assign p_out[127:111] = {1'b0, rednl1_3[78:63]};
always_ff @(posedge clk or posedge reset)
begin: u_pmullout_v2_q_127_0
if (reset == 1'b1)
pmullout_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}};
`ifdef HERCULESAE_XPROP_FLOP
else if (reset == 1'b0 && ival_v1_q == 1'b1)
pmullout_v2_q[127:0] <= `HERCULESAE_DFF_DELAY p_out[127:0];
else if (reset == 1'b0 && ival_v1_q == 1'b0)
begin
end
else
pmullout_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}};
`else
else if (ival_v1_q == 1'b1)
pmullout_v2_q[127:0] <= `HERCULESAE_DFF_DELAY p_out[127:0];
`endif
end
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

78
Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_sha1.sv
View File

@ -1,78 +0,0 @@
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_sha1
(
input wire sha1h_v1_i,
input wire sha1su0_v1_i,
input wire sha1su1_v1_i,
input wire [31:0] sha1h_qn,
input wire [127:0] sha1su0_qd,
input wire [127:0] sha1su1_qd,
input wire [127:0] sha1su1_qn,
output wire [127:0] sha1_v1_o
);
wire [31:0] sha1h_v1;
wire [63:0] sha1su0_opa_v1;
wire [127:0] sha1su0_opb_v1;
wire [127:0] sha1su0_opc_v1;
wire [127:0] sha1su0_v1;
wire [127:0] sha1su1_v1;
wire [127:0] t;
assign sha1h_v1[31:0] = {sha1h_qn[1:0], sha1h_qn[31:2]};
assign sha1su0_opa_v1[63:0] = sha1su1_qn[63:0];
assign sha1su0_opb_v1[127:0] = sha1su1_qd[127:0];
assign sha1su0_opc_v1[127:0] = sha1su0_qd[127:0];
assign sha1su0_v1 [127:0] = sha1su0_opc_v1[127:0]
^ {sha1su0_opa_v1[63:0], sha1su0_opc_v1[127:64]}
^ sha1su0_opb_v1[127:0];
assign t[127:0] = sha1su1_qd[127:0] ^ {{32{1'b0}}, sha1su1_qn[127:32]};
assign sha1su1_v1[127:96] = {t[126:96], t[127]} ^ {t[29:0], t[31:30]};
assign sha1su1_v1[95:64] = {t[94:64], t[95]};
assign sha1su1_v1[63:32] = {t[62:32], t[63]};
assign sha1su1_v1[31:0] = {t[30:0], t[31]};
assign sha1_v1_o[127:0] = {128{sha1su0_v1_i}} & sha1su0_v1[127:0] |
{128{sha1su1_v1_i}} & sha1su1_v1[127:0] |
{128{sha1h_v1_i}} & {{96{1'b0}}, sha1h_v1[31:0]};
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

101
Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_sha1cpm.sv
View File

@ -1,101 +0,0 @@
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_sha1cpm
(
input wire choose,
input wire parity,
input wire majority,
input wire cpm,
input wire [127:0] x,
input wire [31:0] y,
input wire [31:0] z,
input wire [31:0] t2,
output wire [31:0] fa1_s,
output wire [31:0] fa1_c,
output wire [127:0] newx,
output wire [31:0] newy
);
wire [32:0] fa0_c;
wire [31:0] fa0_s;
wire shacpm_nop;
wire [31:0] t1_nop;
wire [31:0] t1c;
wire [31:0] t1m;
wire [31:0] t1p;
wire [127:0] x1;
wire [127:0] x_nop;
wire [31:0] x_rol5_nop;
wire [31:0] y_nop;
wire [31:0] z_nop;
assign shacpm_nop = ~cpm;
assign t1c[31:0] = (x[63:32] & x[95:64]) | (~x[63:32] & x[127:96]);
assign t1p[31:0] = x[63:32] ^ x[95:64] ^ x[127:96];
assign t1m[31:0] = (x[63:32] & x[95:64])
| (x[63:32] & x[127:96])
| (x[95:64] & x[127:96]);
assign t1_nop[31:0] = ({32{choose}} & t1c[31:0])
| ({32{parity}} & t1p[31:0])
| ({32{majority}} & t1m[31:0]);
assign x_rol5_nop[31:0] = {32{~shacpm_nop}} & {x[26:0], x[31:27]};
assign y_nop[31:0] = {32{~shacpm_nop}} & y[31:0];
assign z_nop[31:0] = {32{~shacpm_nop}} & z[31:0];
assign fa0_s[31:0] = y_nop[31:0] ^ x_rol5_nop[31:0] ^ z_nop[31:0];
assign fa0_c[32:0] = {y_nop[31:0] & x_rol5_nop[31:0] | z_nop[31:0] & (y_nop[31:0] | x_rol5_nop[31:0]), 1'b0};
assign fa1_s[31:0] = fa0_s[31:0] ^ fa0_c[31:0] ^ t1_nop[31:0];
assign fa1_c[31:0] = {fa0_s[30:0] & fa0_c[30:0] | t1_nop[30:0] & (fa0_s[30:0] | fa0_c[30:0]), 1'b0};
assign x_nop[127:0] = {128{~shacpm_nop}} & x[127:0];
assign x1[127:64] = x_nop[127:64];
assign x1[63:32] = {x_nop[33:32], x_nop[63:34]};
assign x1[31:0] = x_nop[31:0];
assign newx[127:0] = {x1[95:0], t2[31:0]};
assign newy[31:0] = x1[127:96];
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

104
Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_sha256h32.sv
View File

@ -1,104 +0,0 @@
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_sha256h32
(
input wire [127:0] x,
input wire [127:0] y,
input wire [31:0] z,
input wire [63:0] sumnr,
output wire [63:0] sum,
output wire [63:0] carry,
output wire [127:0] newx,
output wire [127:0] newy
);
wire [31:0] sigma0;
wire [31:0] sigma1;
wire [31:0] tchoose;
wire [31:0] tmajority;
wire [32:0] x_fa2_c;
wire [31:0] x_fa2_s;
wire [127:96] xprime;
wire [32:0] xy_fa0_c;
wire [31:0] xy_fa0_s;
wire [32:0] xy_fa1_c;
wire [31:0] xy_fa1_s;
wire [32:0] y_fa2_c;
wire [31:0] y_fa2_s;
wire [31:0] y_fa3_c;
wire [31:0] y_fa3_s;
wire [127:96] yprime;
assign tchoose[31:0] = (y[31:0] & y[63:32]) | (~y[31:0] & y[95:64]);
assign tmajority[31:0] = (x[31:0] & x[63:32]) | (x[31:0] & x[95:64]) | (x[63:32] & x[95:64]);
assign sigma0[31:0] = {x[1:0], x[31:2]}
^ {x[12:0], x[31:13]}
^ {x[21:0], x[31:22]};
assign sigma1[31:0] = {y[5:0], y[31:6]}
^ {y[10:0], y[31:11]}
^ {y[24:0], y[31:25]};
assign xy_fa0_s[31:0] = y[127:96] ^ z[31:0] ^ tchoose[31:0];
assign xy_fa0_c[32:0] = {y[127:96] & z[31:0] | tchoose[31:0] & (y[127:96] | z[31:0]), 1'b0};
assign xy_fa1_s[31:0] = xy_fa0_s[31:0] ^ xy_fa0_c[31:0] ^ sigma1[31:0];
assign xy_fa1_c[32:0] = {xy_fa0_s[31:0] & xy_fa0_c[31:0] | sigma1[31:0] & (xy_fa0_s[31:0] | xy_fa0_c[31:0]), 1'b0};
assign x_fa2_s[31:0] = xy_fa1_s[31:0] ^ xy_fa1_c[31:0] ^ x[127:96];
assign x_fa2_c[32:0] = {xy_fa1_s[31:0] & xy_fa1_c[31:0] | x[127:96] & (xy_fa1_s[31:0] | xy_fa1_c[31:0]), 1'b0};
assign y_fa2_s[31:0] = sigma0[31:0] ^ tmajority[31:0] ^ xy_fa1_c[31:0];
assign y_fa2_c[32:0] = {sigma0[31:0] & tmajority[31:0] | xy_fa1_c[31:0] & (sigma0[31:0] | tmajority[31:0]), 1'b0};
assign y_fa3_s[31:0] = y_fa2_s[31:0] ^ y_fa2_c[31:0] ^ xy_fa1_s[31:0];
assign y_fa3_c[31:0] = {y_fa2_s[30:0] & y_fa2_c[30:0] | xy_fa1_s[30:0] & (y_fa2_s[30:0] | y_fa2_c[30:0]), 1'b0};
assign sum[63:0] = {x_fa2_s[31:0], y_fa3_s[31:0]};
assign carry[63:0] = {x_fa2_c[31:0], y_fa3_c[31:0]};
assign xprime[127:96] = sumnr[63:32];
assign yprime[127:96] = sumnr[31:0];
assign newx[127:0] = {x[95:0], yprime[127:96]};
assign newy[127:0] = {y[95:0], xprime[127:96]};
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

76
Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_sha256su0.sv
View File

@ -1,76 +0,0 @@
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_sha256su0
(
input wire [127:0] qd,
input wire [31:0] qn,
input wire [31:0] sumd,
output wire [31:0] suma,
output wire [31:0] sumb,
output wire [127:0] d
);
wire d1_cout;
wire d2_cout;
wire d3_cout;
wire [127:0] t;
wire [127:0] t0;
assign t[127:0] = {qn[31:0], qd[127:32]};
assign t0[127:96] = {t[102:96], t[127:103]} ^ {t[113:96], t[127:114]} ^ {3'b000, t[127:99]};
assign t0[95:64] = {t[ 70:64], t[ 95: 71]} ^ {t[ 81:64], t[ 95: 82]} ^ {3'b000, t[ 95:67]};
assign t0[63:32] = {t[ 38:32], t[ 63: 39]} ^ {t[ 49:32], t[ 63: 50]} ^ {3'b000, t[ 63:35]};
assign t0[31:0] = {t[ 6: 0], t[ 31: 7]} ^ {t[ 17: 0], t[ 31: 18]} ^ {3'b000, t[ 31: 3]};
assign {d3_cout, d[127:96]} = t0[127:96] + qd[127:96] + {{31{1'b0}}, 1'b0};
assign {d2_cout, d[95:64]} = t0[95:64] + qd[95:64] + {{31{1'b0}}, 1'b0};
assign {d1_cout, d[63:32]} = t0[63:32] + qd[63:32] + {{31{1'b0}}, 1'b0};
assign suma[31:0] = t0[31:0];
assign sumb[31:0] = qd[31:0];
assign d[31:0] = sumd[31:0];
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

90
Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_sha256su1.sv
View File

@ -1,90 +0,0 @@
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_sha256su1
(
input wire sha256su1_x_op,
input wire sha256su1_y_op,
input wire sha256su1_z_op,
input wire [63:0] x,
input wire [63:0] y,
input wire [63:0] z,
input wire [63:0] sumnr,
output wire [63:0] sum_3to2,
output wire [63:0] carry_3to2,
output wire [63:0] newx
);
wire [63:0] carry;
wire [63:0] sum;
wire [63:0] x_nop;
wire [63:0] y_nop;
wire [63:0] z_nop;
wire [63:0] z_rot;
wire [63:0] zror17;
wire [63:0] zror19;
wire [63:0] zshr10;
assign x_nop[63:0] = x[63:0] & {64{sha256su1_x_op}};
assign y_nop[63:0] = y[63:0] & {64{sha256su1_y_op}};
assign z_nop[63:0] = z[63:0] & {64{sha256su1_z_op}};
assign zror17[63:0] = {z_nop[48:32], z_nop[63:49],
z_nop[16:0], z_nop[31:17]};
assign zror19[63:0] = {z_nop[50:32], z_nop[63:51],
z_nop[18:0], z_nop[31:19]};
assign zshr10[63:0] = {10'b00_0000_0000, z_nop[63:42],
10'b00_0000_0000, z_nop[31:10]};
assign z_rot[63:0] = zror17[63:0] ^ zror19[63:0] ^ zshr10[63:0];
assign sum[63:0] = (x_nop[63:0] ^ y_nop[63:0]) ^ z_rot[63:0];
assign carry[63:32] = {(x_nop[62:32] & y_nop[62:32])
| (y_nop[62:32] & z_rot[62:32])
| (x_nop[62:32] & z_rot[62:32]), 1'b0};
assign carry[31:0] = {(x_nop[30:0] & y_nop[30:0])
| (y_nop[30:0] & z_rot[30:0])
| (x_nop[30:0] & z_rot[30:0]), 1'b0};
assign sum_3to2[63:0] = sum[63:0];
assign carry_3to2[63:0] = carry[63:0];
assign newx[63:0] = sumnr[63:0];
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

4802
Security Algo Accelerator/logical/maia/verilog/MAIA.v
View File

File diff suppressed because it is too large Load Diff

4801
Security Algo Accelerator/logical/maia/verilog/MAIA_feq20.v
View File

File diff suppressed because it is too large Load Diff

4821
Security Algo Accelerator/logical/maia/verilog/MAIA_feq20_s.v
View File

File diff suppressed because it is too large Load Diff

4801
Security Algo Accelerator/logical/maia/verilog/MAIA_feq28.v
View File

File diff suppressed because it is too large Load Diff

4821
Security Algo Accelerator/logical/maia/verilog/MAIA_feq28_s.v
View File

File diff suppressed because it is too large Load Diff

4821
Security Algo Accelerator/logical/maia/verilog/MAIA_s.v
View File

File diff suppressed because it is too large Load Diff

7931
Security Algo Accelerator/logical/maia/verilog/maia_noncpu.v
View File

File diff suppressed because it is too large Load Diff

7934
Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq20.v
View File

File diff suppressed because it is too large Load Diff

7951
Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq20_s.v
View File

File diff suppressed because it is too large Load Diff

7934
Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq28.v
View File

File diff suppressed because it is too large Load Diff

7951
Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq28_s.v
View File

File diff suppressed because it is too large Load Diff

7952
Security Algo Accelerator/logical/maia/verilog/maia_noncpu_s.v
View File

File diff suppressed because it is too large Load Diff

2816
Security Algo Accelerator/logical/maia_complex/verilog/maia_complex.v
View File

File diff suppressed because it is too large Load Diff

351
Security Algo Accelerator/logical/maia_complex/verilog/maia_cx_crypt2.v
View File

@ -1,351 +0,0 @@
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
// (C) COPYRIGHT 2013-2014 ARM Limited.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//
// Filename : $RCSfile: maia_cx_crypt2.v $
// Checked In : $Date: 2014-08-29 00:16:46 -0500 (Fri, 29 Aug 2014) $
// Revision : $Revision: 70482 $
// Release Information : Cortex-A72-r1p0-00rel0
//
//-----------------------------------------------------------------------------
// Verilog-2001 (IEEE Std 1364-2001)
//-----------------------------------------------------------------------------
//#
//# Overview
//# ========
//#
// This block does the following operations:
// - AES encrypt and decrypt operations: aesd, aese, aesmc, aesimc
// - SHA single-cycle operations: sha1h, sha1su1, sha256su0
//#
//# Module Declaration
//# ==================
//#
`include "maia_header.v"
module maia_cx_crypt2 (
//#
//# Interface Signals
//# =================
//#
// Global inputs
ck_gclkcx_crypt,
cx_reset3,
// Control inputs
ival_e1_q,
aesd_e1_q,
aese_e1_q,
aesmc_e1_q,
aesimc_e1_q,
aesdimc_e1_q,
aesemc_e1_q,
pmull_e1_q,
sha1h_e1_q,
sha1su1_e1_q,
sha256su0_e1_q,
// Data inputs
qd,
qn,
// Outputs
crypt2_out_e3_q,
crypt2_active
);
//#
//# Interface Signals
//# =================
//#
// Global inputs
input ck_gclkcx_crypt;
input cx_reset3;
// Control inputs
input ival_e1_q;
input aesd_e1_q; // aes encode
input aese_e1_q; // aes decode
input aesmc_e1_q; // ae smix columns
input aesimc_e1_q; // aes inverse mix columns
input aesdimc_e1_q; // aes decode superop
input aesemc_e1_q; // aes encode superop
input pmull_e1_q; // polynomial multiplication
input sha1h_e1_q; // sha1 fixed rotate
input sha1su1_e1_q; // sha1 schedule update 1
input sha256su0_e1_q; // sha256 schedule update 0
// Data inputs
input [127:0] qd;
input [127:0] qn;
// Outputs
output [127:0] crypt2_out_e3_q;
output crypt2_active;
//#
//# Internal Signals - Automatic Declarations
//# =========================================
//#
wire [ 15: 0] aes_shf_e1;
reg [ 15: 0] aes_shf_e2_q;
wire [127: 0] aesd_e1;
reg aesd_e2_q;
wire aesd_or_e_e1;
wire [127: 0] aesd_out;
wire [ 15: 0] aesd_shf_e1;
reg aesdimc_e2_q;
wire [127: 0] aesdimc_out;
wire [127: 0] aese_e1;
reg aese_e2_q;
wire [127: 0] aese_out;
wire [ 15: 0] aese_shf_e1;
reg aesemc_e2_q;
wire [127: 0] aesemc_out;
reg aesimc_e2_q;
wire [127: 0] aesimc_in;
wire [127: 0] aesimc_out;
reg aesmc_e2_q;
wire [127: 0] aesmc_in;
wire [127: 0] aesmc_out;
wire [127: 0] crypt2_d_e1;
reg [127: 0] crypt2_d_e2_q;
wire [127: 0] crypt2_out_e2;
reg [127: 0] crypt2_out_e3_q;
reg ival_e2_q;
reg pmull_e2_q;
wire [127: 0] pmull_out;
wire [127: 0] qx_e1;
wire [ 31: 0] sha1h_in_e1;
wire [ 31: 0] sha1h_out_e1;
wire [127: 0] sha1su1_out_e1;
wire [127: 0] sha1su1_qdin_e1;
wire [127: 0] sha1su1_qnin_e1;
wire [127: 0] sha256su0_out_e1;
wire sha_inst_e1;
reg sha_inst_e2_q;
//#
//# Main Code
//# =========
//#
//
// aes functions are all in the same block because of limited result bus bandwidth.
// Mais CX has 3x64-bit result buses, and each of these instructions produces
// a 128-bit result. Two instructions could be issued in a cycle, but there is
// no value in doing this because they could not both write results.
//
// The single-cycle 2-input SHA instructions are in the same block because they have the same inputs
// and latency as the aes instructions.
//
// Originally, all functions in this block had single-cycle latency, but CX is unable to make use
// of single-cycle latency. To reduce area, functionality is spread across E1 and E2
// In particular, the AES SBOX and ISBOX functions are split into LUT(mult inverse) -> affine transform
// & affine inverse transform -> LUT(mult inverse), so that they can share the same LUT.
// E1
// 38% of this cycle is used up to drive qd and qn from the issq block. Therefore, the relatively
// shallow SHA operations are performed in this cycle, along with some preliminary processing for AESE and AESD
assign qx_e1[127:0] = {128{aesd_or_e_e1}} & (qd[127:0] ^ qn[127:0]);
maia_cx_aese1 uaese1(
.q (qx_e1[127:0]),
.aese_out (aese_e1[127:0]),
.aese_shf (aese_shf_e1[15:0])
);
maia_cx_aesd1 uaesd1(
.q (qx_e1[127:0]),
.aesd_out (aesd_e1[127:0]),
.aesd_shf (aesd_shf_e1[15:0])
);
assign aesd_or_e_e1 = aesd_e1_q | aese_e1_q;
// Perform sha functions in E1 to save pipeline flops
// and reduce complexity of multiplexer in E2
assign sha1h_in_e1[31:0] = {32{sha1h_e1_q}} & qn[31:0];
maia_cx_sha1h usha1h(
.qn (sha1h_in_e1[31:0]),
.d (sha1h_out_e1[31:0])
);
assign sha1su1_qdin_e1[127:0] = {128{sha1su1_e1_q}} & qd[127:0];
assign sha1su1_qnin_e1[127:0] = {128{sha1su1_e1_q}} & qn[127:0];
maia_cx_sha1su1 usha1su1(
.qd (sha1su1_qdin_e1[127:0]),
.qn (sha1su1_qnin_e1[127:0]),
.d (sha1su1_out_e1[127:0])
);
maia_cx_sha256su0 usha256su0(
.qd (qd[127:0]),
.qn (qn[127:0]),
.d (sha256su0_out_e1[127:0])
);
assign sha_inst_e1 = sha1h_e1_q | sha1su1_e1_q | sha256su0_e1_q;
assign crypt2_d_e1[127:0] = ({128{sha1h_e1_q}} & {{96{1'b0}}, sha1h_out_e1[31:0]})
| ({128{sha1su1_e1_q}} & sha1su1_out_e1[127:0])
| ({128{sha256su0_e1_q}} & sha256su0_out_e1[127:0])
| ({128{aese_e1_q}} & aese_e1[127:0])
| ({128{aesd_e1_q}} & aesd_e1[127:0])
| ({128{~(aesd_or_e_e1 | sha_inst_e1)}} & qn[127:0]);
assign aes_shf_e1[15:0] = {16{aese_e1_q}} & aese_shf_e1[15:0] |
{16{aesd_e1_q}} & aesd_shf_e1[15:0];
// reset flop(s) since feeds into active signal used for RCG
// Macro DFF called
// verilint flop_checks off
always @(posedge ck_gclkcx_crypt or posedge cx_reset3)
begin: uival_e2_q
if (cx_reset3 == 1'b1)
ival_e2_q <= `MAIA_DFF_DELAY {1{1'b0}};
`ifdef MAIA_XPROP_FLOP
else if (cx_reset3==1'b0)
ival_e2_q <= `MAIA_DFF_DELAY ival_e1_q;
else
ival_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
`else
else
ival_e2_q <= `MAIA_DFF_DELAY ival_e1_q;
`endif
end
// verilint flop_checks on
// end of Macro DFF
// Macro DFF called
// verilint flop_checks off
always @(posedge ck_gclkcx_crypt)
begin: ucrypt2_e2
if (ival_e1_q==1'b1) begin
crypt2_d_e2_q[127:0] <= `MAIA_DFF_DELAY crypt2_d_e1[127:0];
aes_shf_e2_q[15:0] <= `MAIA_DFF_DELAY aes_shf_e1[15:0];
aesd_e2_q <= `MAIA_DFF_DELAY aesd_e1_q;
aese_e2_q <= `MAIA_DFF_DELAY aese_e1_q;
aesmc_e2_q <= `MAIA_DFF_DELAY aesmc_e1_q;
aesimc_e2_q <= `MAIA_DFF_DELAY aesimc_e1_q;
aesemc_e2_q <= `MAIA_DFF_DELAY aesemc_e1_q;
aesdimc_e2_q <= `MAIA_DFF_DELAY aesdimc_e1_q;
pmull_e2_q <= `MAIA_DFF_DELAY pmull_e1_q;
sha_inst_e2_q <= `MAIA_DFF_DELAY sha_inst_e1;
end
`ifdef MAIA_XPROP_FLOP
else if ((ival_e1_q==1'b0));
else begin
crypt2_d_e2_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}};
aes_shf_e2_q[15:0] <= `MAIA_DFF_DELAY {16{1'bx}};
aesd_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
aese_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
aesmc_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
aesimc_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
aesemc_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
aesdimc_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
pmull_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
sha_inst_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
end
`endif
end
// verilint flop_checks on
// end of Macro DFF
// Enable data inputs for selected operation (glitch suppression in unused datapaths)
assign aesmc_in[127:0] = {128{aesmc_e2_q }} & crypt2_d_e2_q[127:0];
assign aesimc_in[127:0] = {128{aesimc_e2_q}} & crypt2_d_e2_q[127:0];
maia_cx_aesed2 uaesed2(
.aes_din (crypt2_d_e2_q[127:0]),
.aes_shf (aes_shf_e2_q[15:0]),
.aesd_out (aesd_out[127:0]),
.aese_out (aese_out[127:0]),
.aesemc_out (aesemc_out[127:0]),
.aesdimc_out (aesdimc_out[127:0])
);
maia_cx_aesmc uaesmc(
.d_in (aesmc_in[127:0]),
.mc (aesmc_out[127:0])
);
maia_cx_aesimc uaesimc(
.d_in (aesimc_in[127:0]),
.imc (aesimc_out[127:0])
);
maia_cx_pmull upmull(
.a_in (crypt2_d_e2_q[63:0]),
.b_in (crypt2_d_e2_q[127:64]),
.p_out (pmull_out[127:0])
);
assign crypt2_out_e2[127:0] = ({128{aesd_e2_q & ~aesdimc_e2_q}} & aesd_out[127:0])
| ({128{aese_e2_q & ~aesemc_e2_q}} & aese_out[127:0])
| ({128{aesmc_e2_q}} & aesmc_out[127:0])
| ({128{aesemc_e2_q}} & aesemc_out[127:0])
| ({128{aesimc_e2_q}} & aesimc_out[127:0])
| ({128{aesdimc_e2_q}} & aesdimc_out[127:0])
| ({128{sha_inst_e2_q}} & crypt2_d_e2_q[127:0])
| ({128{pmull_e2_q}} & pmull_out[127:0]);
// Macro DFF called
// verilint flop_checks off
always @(posedge ck_gclkcx_crypt)
begin: ucrypt2_e3
if (ival_e2_q==1'b1) begin
crypt2_out_e3_q[127:0] <= `MAIA_DFF_DELAY crypt2_out_e2[127:0];
end
`ifdef MAIA_XPROP_FLOP
else if ((ival_e2_q==1'b0));
else begin
crypt2_out_e3_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}};
end
`endif
end
// verilint flop_checks on
// end of Macro DFF
//-----------------------------------------------------------------------------
// regional clock gating (RCG) terms
//-----------------------------------------------------------------------------
assign crypt2_active = (ival_e1_q | ival_e2_q);
endmodule
//ARMAUTO UNDEF START
`define MAIA_UNDEFINE
`include "maia_header.v"
`undef MAIA_UNDEFINE
//ARMAUTO UNDEF END

713
Security Algo Accelerator/logical/maia_complex/verilog/maia_cx_crypt3.v
View File

@ -1,713 +0,0 @@
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
// (C) COPYRIGHT 2013-2014 ARM Limited.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//
// Filename : $RCSfile: maia_cx_crypt3.v $
// Checked In : $Date: 2014-08-29 00:16:46 -0500 (Fri, 29 Aug 2014) $
// Revision : $Revision: 70482 $
// Release Information : Cortex-A72-r1p0-00rel0
//
//-----------------------------------------------------------------------------
// Verilog-2001 (IEEE Std 1364-2001)
//-----------------------------------------------------------------------------
//#
//# Overview
//# ========
//#
// This block does the following operations:
// - SHA 3-input operations: sha1cpm, sha1su0, sha256h, sha256h2, sha256su1
//#
//# Module Declaration
//# ==================
//#
`include "maia_header.v"
module maia_cx_crypt3 (
//#
//# Interface Signals
//# =================
//#
// Global inputs
ck_gclkcx_crypt,
cx_reset3,
// Control inputs
//
// This block has 3x128-bit inputs for each instruction, so it requires two cycles just to
// get its operands. In E1, we receive two of the operands (qn and qm) and ival_e1_q,
// which allows the operands to be stored in flops. We also get inputs indicating which
// instruction is to be computed.
//
// At some later cycle, we receive the 3rd operand, qd, and ival_e2_q, indicating that
// we should begin the computation.
//
// There are 4 execution stages, E2-E5.
ival_e1_q,
sha1c_e1_q,
sha1p_e1_q,
sha1m_e1_q,
sha256h_e1_q,
sha256h2_e1_q,
sha256su1_e1_q,
ival_e2_q,
// Data inputs
qn_e1_q,
qm_e1_q,
qd_e2_q,
// Outputs
crypt3_out_e6_q,
crypt3_active
);
//#
//# Interface Signals
//# =================
//#
// Global inputs
input ck_gclkcx_crypt;
input cx_reset3;
// Control inputs
//
// This block has 3x128-bit inputs for each instruction, so it requires two cycles just to
// get its operands. In E1, we receive two of the operands (qn and qm) and ival_e1_q,
// which allows the operands to be stored in flops. We also get inputs indicating which
// instruction is to be computed.
//
// At some later cycle, we receive the 3rd operand, qd, and ival_e2_q, indicating that
// we should begin the computation.
//
// There are 4 execution stages, E2-E5.
input ival_e1_q;
input sha1c_e1_q; // sha hash update (choose)
input sha1p_e1_q; // sha hash update (parity)
input sha1m_e1_q; // sha hash update (majority)
input sha256h_e1_q; // sha256 hash update
input sha256h2_e1_q; // sha256 hash update 2
input sha256su1_e1_q; // sha256 schedule update 1
input ival_e2_q;
// Data inputs
input [127:0] qn_e1_q; // qn arrives with first uop on {srcb,srca}
input [127:0] qm_e1_q; // qm arrives with first uop on {srcd,srcc}
input [127:0] qd_e2_q; // qd arrives with second uop on {srcb,srca}
// Outputs
output [127:0] crypt3_out_e6_q;
output crypt3_active;
//#
//# Internal Signals - Automatic Declarations
//# =========================================
//#
wire [127: 0] crypt3_out_e5;
reg [127: 0] crypt3_out_e6_q;
wire firstop_recvd_e1;
reg firstop_recvd_e2_q;
reg ival_e3_q;
reg ival_e4_q;
reg ival_e5_q;
wire [127: 0] newx_e2;
wire [127: 0] newx_e3;
wire [127: 0] newx_e4;
wire [127: 0] newy_e2;
wire [127: 0] newy_e3;
wire [127: 0] newy_e4;
reg [127: 0] qm_e2_q;
reg [127: 0] qn_e2_q;
wire [127: 0] sha1_xin_e2;
wire [ 31: 0] sha1_yin_e2;
wire [ 31: 0] sha1_zin_e2;
wire sha1c_e2;
reg sha1c_e2_q;
reg sha1c_e3_q;
reg sha1c_e4_q;
reg sha1c_e5_q;
wire sha1cpm_e2;
wire sha1cpm_e3;
wire sha1cpm_e4;
wire sha1cpm_e5;
wire [127: 0] sha1cpm_x_e2;
wire [127: 0] sha1cpm_x_e3;
wire [127: 0] sha1cpm_x_e4;
wire [127: 0] sha1cpm_x_e5;
wire [127: 0] sha1cpm_y_e2;
wire [127: 0] sha1cpm_y_e3;
wire [127: 0] sha1cpm_y_e4;
// verilint unused_sigs off
wire [ 31: 0] sha1cpm_y_e5;
// verilint unused_sigs on
wire sha1m_e2;
reg sha1m_e2_q;
reg sha1m_e3_q;
reg sha1m_e4_q;
reg sha1m_e5_q;
wire sha1p_e2;
reg sha1p_e2_q;
reg sha1p_e3_q;
reg sha1p_e4_q;
reg sha1p_e5_q;
wire [127: 0] sha256_xin_e2;
wire [127: 0] sha256_yin_e2;
wire [ 31: 0] sha256_zin_e2;
wire sha256h2_e2;
reg sha256h2_e2_q;
reg sha256h2_e3_q;
reg sha256h2_e4_q;
reg sha256h2_e5_q;
wire sha256h_e2;
reg sha256h_e2_q;
reg sha256h_e3_q;
reg sha256h_e4_q;
reg sha256h_e5_q;
wire [127: 0] sha256h_x_e2;
wire [127: 0] sha256h_x_e3;
wire [127: 0] sha256h_x_e4;
wire [127: 0] sha256h_x_e5;
wire [127: 0] sha256h_y_e2;
wire [127: 0] sha256h_y_e3;
wire [127: 0] sha256h_y_e4;
wire [127: 0] sha256h_y_e5;
wire sha256hh2_e2;
wire sha256hh2_e3;
wire sha256hh2_e4;
wire sha256su1_e2;
reg sha256su1_e2_q;
reg sha256su1_e3_q;
reg sha256su1_e4_q;
reg sha256su1_e5_q;
wire [ 63: 0] sha256su1_x_e3;
wire [ 63: 0] sha256su1_x_e4;
wire [127: 0] x_e2;
wire [127: 0] x_e3;
reg [127: 0] x_e3_q;
wire [127: 0] x_e4;
reg [127: 0] x_e4_q;
wire [127: 0] x_e5;
reg [127: 0] x_e5_q;
wire [127: 0] y_e2;
wire [127: 0] y_e3;
reg [127: 0] y_e3_q;
wire [127: 0] y_e4;
reg [127: 0] y_e4_q;
wire [127: 0] y_e5;
reg [127: 0] y_e5_q;
wire [127: 0] z_e2;
wire [ 95: 0] z_e3;
reg [ 95: 0] z_e3_q;
wire [ 63: 0] z_e4;
reg [ 63: 0] z_e4_q;
wire [ 31: 0] z_e5;
reg [ 31: 0] z_e5_q;
//#
//# Main Code
//# =========
//#
//
// set when ival_e1_q first received, and held until the 2nd uop (ival_e2_q) is received
assign firstop_recvd_e1 = (ival_e1_q | (firstop_recvd_e2_q & ~ival_e2_q));
// ival and instruction flops
// reset flop since 1st uop of crypto pair can be flushed due to SWDW nuke, thus might
// have received ival_e2_q without ever receiving ival_e1_q (since it was flushed). thus
// want firstop_recvd_e2_q to be 0 (not X) to stop X-prop
// Macro DFF called
// verilint flop_checks off
always @(posedge ck_gclkcx_crypt or posedge cx_reset3)
begin: ufirstop_recvd_e2_q
if (cx_reset3 == 1'b1)
firstop_recvd_e2_q <= `MAIA_DFF_DELAY {1{1'b0}};
`ifdef MAIA_XPROP_FLOP
else if (cx_reset3==1'b0)
firstop_recvd_e2_q <= `MAIA_DFF_DELAY firstop_recvd_e1;
else
firstop_recvd_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
`else
else
firstop_recvd_e2_q <= `MAIA_DFF_DELAY firstop_recvd_e1;
`endif
end
// verilint flop_checks on
// end of Macro DFF
// reset flop(s) since feeds into active signal used for RCG
// Macro DFF called
// verilint flop_checks off
always @(posedge ck_gclkcx_crypt or posedge cx_reset3)
begin: uival_e3_q
if (cx_reset3 == 1'b1)
ival_e3_q <= `MAIA_DFF_DELAY {1{1'b0}};
`ifdef MAIA_XPROP_FLOP
else if (cx_reset3==1'b0)
ival_e3_q <= `MAIA_DFF_DELAY ival_e2_q;
else
ival_e3_q <= `MAIA_DFF_DELAY {1{1'bx}};
`else
else
ival_e3_q <= `MAIA_DFF_DELAY ival_e2_q;
`endif
end
// verilint flop_checks on
// end of Macro DFF
// Macro DFF called
// verilint flop_checks off
always @(posedge ck_gclkcx_crypt or posedge cx_reset3)
begin: uival_e4_q
if (cx_reset3 == 1'b1)
ival_e4_q <= `MAIA_DFF_DELAY {1{1'b0}};
`ifdef MAIA_XPROP_FLOP
else if (cx_reset3==1'b0)
ival_e4_q <= `MAIA_DFF_DELAY ival_e3_q;
else
ival_e4_q <= `MAIA_DFF_DELAY {1{1'bx}};
`else
else
ival_e4_q <= `MAIA_DFF_DELAY ival_e3_q;
`endif
end
// verilint flop_checks on
// end of Macro DFF
// Macro DFF called
// verilint flop_checks off
always @(posedge ck_gclkcx_crypt or posedge cx_reset3)
begin: uival_e5_q
if (cx_reset3 == 1'b1)
ival_e5_q <= `MAIA_DFF_DELAY {1{1'b0}};
`ifdef MAIA_XPROP_FLOP
else if (cx_reset3==1'b0)
ival_e5_q <= `MAIA_DFF_DELAY ival_e4_q;
else
ival_e5_q <= `MAIA_DFF_DELAY {1{1'bx}};
`else
else
ival_e5_q <= `MAIA_DFF_DELAY ival_e4_q;
`endif
end
// verilint flop_checks on
// end of Macro DFF
// Macro DFF called
// verilint flop_checks off
always @(posedge ck_gclkcx_crypt)
begin: uinst_e2
if (ival_e1_q==1'b1) begin
sha1c_e2_q <= `MAIA_DFF_DELAY sha1c_e1_q;
sha1p_e2_q <= `MAIA_DFF_DELAY sha1p_e1_q;
sha1m_e2_q <= `MAIA_DFF_DELAY sha1m_e1_q;
sha256h_e2_q <= `MAIA_DFF_DELAY sha256h_e1_q;
sha256h2_e2_q <= `MAIA_DFF_DELAY sha256h2_e1_q;
sha256su1_e2_q <= `MAIA_DFF_DELAY sha256su1_e1_q;
end
`ifdef MAIA_XPROP_FLOP
else if ((ival_e1_q==1'b0));
else begin
sha1c_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
sha1p_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
sha1m_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
sha256h_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
sha256h2_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
sha256su1_e2_q <= `MAIA_DFF_DELAY {1{1'bx}};
end
`endif
end
// verilint flop_checks on
// end of Macro DFF
// stop X-prop if 1st uop was nuked due to swdw_nuke and 2nd was issued
assign sha1c_e2 = firstop_recvd_e2_q & sha1c_e2_q;
assign sha1p_e2 = firstop_recvd_e2_q & sha1p_e2_q;
assign sha1m_e2 = firstop_recvd_e2_q & sha1m_e2_q;
assign sha256h_e2 = firstop_recvd_e2_q & sha256h_e2_q;
assign sha256h2_e2 = firstop_recvd_e2_q & sha256h2_e2_q;
assign sha256su1_e2 = firstop_recvd_e2_q & sha256su1_e2_q;
// Macro DFF called
// verilint flop_checks off
always @(posedge ck_gclkcx_crypt)
begin: uinst_e3
if (ival_e2_q==1'b1) begin
sha1c_e3_q <= `MAIA_DFF_DELAY sha1c_e2;
sha1p_e3_q <= `MAIA_DFF_DELAY sha1p_e2;
sha1m_e3_q <= `MAIA_DFF_DELAY sha1m_e2;
sha256h_e3_q <= `MAIA_DFF_DELAY sha256h_e2;
sha256h2_e3_q <= `MAIA_DFF_DELAY sha256h2_e2;
sha256su1_e3_q <= `MAIA_DFF_DELAY sha256su1_e2;
end
`ifdef MAIA_XPROP_FLOP
else if ((ival_e2_q==1'b0));
else begin
sha1c_e3_q <= `MAIA_DFF_DELAY {1{1'bx}};
sha1p_e3_q <= `MAIA_DFF_DELAY {1{1'bx}};
sha1m_e3_q <= `MAIA_DFF_DELAY {1{1'bx}};
sha256h_e3_q <= `MAIA_DFF_DELAY {1{1'bx}};
sha256h2_e3_q <= `MAIA_DFF_DELAY {1{1'bx}};
sha256su1_e3_q <= `MAIA_DFF_DELAY {1{1'bx}};
end
`endif
end
// verilint flop_checks on
// end of Macro DFF
// Macro DFF called
// verilint flop_checks off
always @(posedge ck_gclkcx_crypt)
begin: uinst_e4
if (ival_e3_q==1'b1) begin
sha1c_e4_q <= `MAIA_DFF_DELAY sha1c_e3_q;
sha1p_e4_q <= `MAIA_DFF_DELAY sha1p_e3_q;
sha1m_e4_q <= `MAIA_DFF_DELAY sha1m_e3_q;
sha256h_e4_q <= `MAIA_DFF_DELAY sha256h_e3_q;
sha256h2_e4_q <= `MAIA_DFF_DELAY sha256h2_e3_q;
sha256su1_e4_q <= `MAIA_DFF_DELAY sha256su1_e3_q;
end
`ifdef MAIA_XPROP_FLOP
else if ((ival_e3_q==1'b0));
else begin
sha1c_e4_q <= `MAIA_DFF_DELAY {1{1'bx}};
sha1p_e4_q <= `MAIA_DFF_DELAY {1{1'bx}};
sha1m_e4_q <= `MAIA_DFF_DELAY {1{1'bx}};
sha256h_e4_q <= `MAIA_DFF_DELAY {1{1'bx}};
sha256h2_e4_q <= `MAIA_DFF_DELAY {1{1'bx}};
sha256su1_e4_q <= `MAIA_DFF_DELAY {1{1'bx}};
end
`endif
end
// verilint flop_checks on
// end of Macro DFF
// Macro DFF called
// verilint flop_checks off
always @(posedge ck_gclkcx_crypt)
begin: uinst_e5
if (ival_e4_q==1'b1) begin
sha1c_e5_q <= `MAIA_DFF_DELAY sha1c_e4_q;
sha1p_e5_q <= `MAIA_DFF_DELAY sha1p_e4_q;
sha1m_e5_q <= `MAIA_DFF_DELAY sha1m_e4_q;
sha256h_e5_q <= `MAIA_DFF_DELAY sha256h_e4_q;
sha256h2_e5_q <= `MAIA_DFF_DELAY sha256h2_e4_q;
sha256su1_e5_q <= `MAIA_DFF_DELAY sha256su1_e4_q;
end
`ifdef MAIA_XPROP_FLOP
else if ((ival_e4_q==1'b0));
else begin
sha1c_e5_q <= `MAIA_DFF_DELAY {1{1'bx}};
sha1p_e5_q <= `MAIA_DFF_DELAY {1{1'bx}};
sha1m_e5_q <= `MAIA_DFF_DELAY {1{1'bx}};
sha256h_e5_q <= `MAIA_DFF_DELAY {1{1'bx}};
sha256h2_e5_q <= `MAIA_DFF_DELAY {1{1'bx}};
sha256su1_e5_q <= `MAIA_DFF_DELAY {1{1'bx}};
end
`endif
end
// verilint flop_checks on
// end of Macro DFF
// E1
// Macro DFF called
// verilint flop_checks off
always @(posedge ck_gclkcx_crypt)
begin: uops_e2
if (ival_e1_q==1'b1) begin
qm_e2_q[127:0] <= `MAIA_DFF_DELAY qm_e1_q[127:0];
qn_e2_q[127:0] <= `MAIA_DFF_DELAY qn_e1_q[127:0];
end
`ifdef MAIA_XPROP_FLOP
else if ((ival_e1_q==1'b0));
else begin
qm_e2_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}};
qn_e2_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}};
end
`endif
end
// verilint flop_checks on
// end of Macro DFF
// E2
assign x_e2[127:0] = qd_e2_q[127:0];
assign y_e2[127:0] = qn_e2_q[127:0];
assign z_e2[127:0] = qm_e2_q[127:0];
assign sha1_xin_e2[127:0] = {128{sha1cpm_e2}} & x_e2[127:0];
assign sha1_yin_e2[ 31:0] = { 32{sha1cpm_e2}} & y_e2[ 31:0];
assign sha1_zin_e2[ 31:0] = { 32{sha1cpm_e2}} & z_e2[ 31:0];
// sha1 hash update
maia_cx_sha1cpm usha1cpm_e2(
.choose (sha1c_e2_q),
.parity (sha1p_e2_q),
.majority (sha1m_e2_q),
.x (sha1_xin_e2[127:0]),
.y (sha1_yin_e2[31:0]),
.z (sha1_zin_e2[31:0]),
.newx (sha1cpm_x_e2[127:0]),
.newy (sha1cpm_y_e2[31:0])
);
assign sha1cpm_y_e2[127:32] = {96{sha1cpm_e2}} & y_e2[127:32];
assign sha256_xin_e2[127:0] = {128{sha256hh2_e2}} & x_e2[127:0];
assign sha256_yin_e2[127:0] = {128{sha256hh2_e2}} & y_e2[127:0];
assign sha256_zin_e2[ 31:0] = { 32{sha256hh2_e2}} & z_e2[ 31:0];
// sha256 hash update (1 and 2)
maia_cx_sha256h32 usha256h32_e2(
.x (sha256_xin_e2[127:0]),
.y (sha256_yin_e2[127:0]),
.z (sha256_zin_e2[31:0]),
.newx (sha256h_x_e2[127:0]),
.newy (sha256h_y_e2[127:0])
);
// mux results
assign sha1cpm_e2 = sha1c_e2 | sha1p_e2 | sha1m_e2;
assign sha256hh2_e2 = sha256h_e2 | sha256h2_e2;
assign newx_e2[127:0] = ({128{sha1cpm_e2 }} & sha1cpm_x_e2[127:0])
| ({128{sha256hh2_e2}} & sha256h_x_e2[127:0])
| ({128{sha256su1_e2}} & x_e2[127:0]);
assign newy_e2[127:0] = ({128{sha1cpm_e2 }} & sha1cpm_y_e2[127:0])
| ({128{sha256hh2_e2}} & sha256h_y_e2[127:0])
| ({128{sha256su1_e2}} & {z_e2[31:0], y_e2[127:32]});
// Macro DFF called
// verilint flop_checks off
always @(posedge ck_gclkcx_crypt)
begin: uops_e3
if (ival_e2_q==1'b1) begin
x_e3_q[127:0] <= `MAIA_DFF_DELAY newx_e2[127:0];
y_e3_q[127:0] <= `MAIA_DFF_DELAY newy_e2[127:0];
z_e3_q[95:0] <= `MAIA_DFF_DELAY z_e2[127:32];
end
`ifdef MAIA_XPROP_FLOP
else if ((ival_e2_q==1'b0));
else begin
x_e3_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}};
y_e3_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}};
z_e3_q[95:0] <= `MAIA_DFF_DELAY {96{1'bx}};
end
`endif
end
// verilint flop_checks on
// end of Macro DFF
// E3
assign x_e3[127:0] = x_e3_q[127:0];
assign y_e3[127:0] = y_e3_q[127:0];
assign z_e3[95:0] = z_e3_q[95:0];
// sha1 hash update
maia_cx_sha1cpm usha1cpm_e3(
.choose (sha1c_e3_q),
.parity (sha1p_e3_q),
.majority (sha1m_e3_q),
.x (x_e3[127:0]),
.y (y_e3[31:0]),
.z (z_e3[31:0]),
.newx (sha1cpm_x_e3[127:0]),
.newy (sha1cpm_y_e3[31:0])
);
assign sha1cpm_y_e3[127:32] = y_e3[127:32];
// sha256 hash update (1 and 2)
maia_cx_sha256h32 usha256h32_e3(
.x (x_e3[127:0]),
.y (y_e3[127:0]),
.z (z_e3[31:0]),
.newx (sha256h_x_e3[127:0]),
.newy (sha256h_y_e3[127:0])
);
// sha256 schedule update 1, cycle 1
maia_cx_sha256su1 usha256su1_e3(
.sha256su1_op (sha256su1_e3_q),
.x (x_e3[63:0]), // qd[63:0]
.y (y_e3[63:0]), // qn[95:32]
.z (z_e3[95:32]), // qm[127:64]
.newx (sha256su1_x_e3[63:0])
);
// mux results
assign sha1cpm_e3 = sha1c_e3_q | sha1p_e3_q | sha1m_e3_q;
assign sha256hh2_e3 = sha256h_e3_q | sha256h2_e3_q;
assign newx_e3[127:0] = ({128{sha1cpm_e3 }} & sha1cpm_x_e3[127:0])
| ({128{sha256hh2_e3 }} & sha256h_x_e3[127:0])
| ({128{sha256su1_e3_q}} & {x_e3[127:64], sha256su1_x_e3[63:0]});
assign newy_e3[127:0] = ({128{sha1cpm_e3 }} & sha1cpm_y_e3[127:0])
| ({128{sha256hh2_e3 }} & sha256h_y_e3[127:0])
| ({128{sha256su1_e3_q}} & {y_e3[127:0]});
// Macro DFF called
// verilint flop_checks off
always @(posedge ck_gclkcx_crypt)
begin: uops_e4
if (ival_e3_q==1'b1) begin
x_e4_q[127:0] <= `MAIA_DFF_DELAY newx_e3[127:0];
y_e4_q[127:0] <= `MAIA_DFF_DELAY newy_e3[127:0];
z_e4_q[63:0] <= `MAIA_DFF_DELAY z_e3[95:32];
end
`ifdef MAIA_XPROP_FLOP
else if ((ival_e3_q==1'b0));
else begin
x_e4_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}};
y_e4_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}};
z_e4_q[63:0] <= `MAIA_DFF_DELAY {64{1'bx}};
end
`endif
end
// verilint flop_checks on
// end of Macro DFF
// E4
assign x_e4[127:0] = x_e4_q[127:0];
assign y_e4[127:0] = y_e4_q[127:0];
assign z_e4[63:0] = z_e4_q[63:0];
// sha1 hash update
maia_cx_sha1cpm usha1cpm_e4(
.choose (sha1c_e4_q),
.parity (sha1p_e4_q),
.majority (sha1m_e4_q),
.x (x_e4[127:0]),
.y (y_e4[31:0]),
.z (z_e4[31:0]),
.newx (sha1cpm_x_e4[127:0]),
.newy (sha1cpm_y_e4[31:0])
);
assign sha1cpm_y_e4[127:32] = y_e4[127:32];
// sha256 hash update (1 and 2)
maia_cx_sha256h32 usha256h32_e4(
.x (x_e4[127:0]),
.y (y_e4[127:0]),
.z (z_e4[31:0]),
.newx (sha256h_x_e4[127:0]),
.newy (sha256h_y_e4[127:0])
);
// sha256 schedule update 1, cycle 2
maia_cx_sha256su1 usha256su1_e4(
.sha256su1_op (sha256su1_e4_q),
.x (x_e4[127:64]), // qd[127:64]
.y (y_e4[127:64]), // {qm[31:0], qn[127:96]}
.z (x_e4[63:0]), // sha256su1_x_e3[63:0]
.newx (sha256su1_x_e4[63:0])
);
// mux results
assign sha1cpm_e4 = sha1c_e4_q | sha1p_e4_q | sha1m_e4_q;
assign sha256hh2_e4 = sha256h_e4_q | sha256h2_e4_q;
assign newx_e4[127:0] = ({128{sha1cpm_e4 }} & sha1cpm_x_e4[127:0])
| ({128{sha256hh2_e4 }} & sha256h_x_e4[127:0])
| ({128{sha256su1_e4_q}} & {sha256su1_x_e4[63:0], x_e4[63:0]});
assign newy_e4[127:0] = ({128{sha1cpm_e4 }} & sha1cpm_y_e4[127:0])
| ({128{sha256hh2_e4 }} & sha256h_y_e4[127:0]);
// Macro DFF called
// verilint flop_checks off
always @(posedge ck_gclkcx_crypt)
begin: uops_e5
if (ival_e4_q==1'b1) begin
x_e5_q[127:0] <= `MAIA_DFF_DELAY newx_e4[127:0];
y_e5_q[127:0] <= `MAIA_DFF_DELAY newy_e4[127:0];
z_e5_q[31:0] <= `MAIA_DFF_DELAY z_e4[63:32];
end
`ifdef MAIA_XPROP_FLOP
else if ((ival_e4_q==1'b0));
else begin
x_e5_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}};
y_e5_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}};
z_e5_q[31:0] <= `MAIA_DFF_DELAY {32{1'bx}};
end
`endif
end
// verilint flop_checks on
// end of Macro DFF
// E5
assign x_e5[127:0] = x_e5_q[127:0];
assign y_e5[127:0] = y_e5_q[127:0];
assign z_e5[31:0] = z_e5_q[31:0];
// sha1 hash update
maia_cx_sha1cpm usha1cpm_e5(
.choose (sha1c_e5_q),
.parity (sha1p_e5_q),
.majority (sha1m_e5_q),
.x (x_e5[127:0]),
.y (y_e5[31:0]),
.z (z_e5[31:0]),
.newx (sha1cpm_x_e5[127:0]),
.newy (sha1cpm_y_e5[31:0])
);
// sha256 hash update (1 and 2)
maia_cx_sha256h32 usha256h32_e5(
.x (x_e5[127:0]),
.y (y_e5[127:0]),
.z (z_e5[31:0]),
.newx (sha256h_x_e5[127:0]),
.newy (sha256h_y_e5[127:0])
);
// mux results
assign sha1cpm_e5 = sha1c_e5_q | sha1p_e5_q | sha1m_e5_q;
assign crypt3_out_e5[127:0] = ({128{sha1cpm_e5}} & sha1cpm_x_e5[127:0])
| ({128{sha256h_e5_q}} & sha256h_x_e5[127:0])
| ({128{sha256h2_e5_q}} & sha256h_y_e5[127:0])
| ({128{sha256su1_e5_q}} & x_e5[127:0]);
// Macro DFF called
// verilint flop_checks off
always @(posedge ck_gclkcx_crypt)
begin: ures_e6
if (ival_e5_q==1'b1) begin
crypt3_out_e6_q[127:0] <= `MAIA_DFF_DELAY crypt3_out_e5[127:0];
end
`ifdef MAIA_XPROP_FLOP
else if ((ival_e5_q==1'b0));
else begin
crypt3_out_e6_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}};
end
`endif
end
// verilint flop_checks on
// end of Macro DFF
//-----------------------------------------------------------------------------
// regional clock gating (RCG) terms
//-----------------------------------------------------------------------------
assign crypt3_active = (ival_e1_q |
ival_e2_q |
ival_e3_q |
ival_e4_q |
ival_e5_q
);
endmodule
//ARMAUTO UNDEF START
`define MAIA_UNDEFINE
`include "maia_header.v"
`undef MAIA_UNDEFINE
//ARMAUTO UNDEF END

67
Security Algo Accelerator/logical/testbench/execution_tb/tests/aarch32/crypto/Makefile.inc
View File

@ -1,67 +0,0 @@
#-----------------------------------------------------------------------------
# The confidential and proprietary information contained in this file may
# only be used by a person authorised under and to the extent permitted
# by a subsisting licensing agreement from ARM Limited or its affiliates.
#
# (C) COPYRIGHT 2013-2020 ARM Limited or its affiliates.
# ALL RIGHTS RESERVED
#
# This entire notice must be reproduced on all copies of this file
# and copies of this file may only be made by a person if such person is
# permitted to do so under the terms of a subsisting license agreement
# from ARM Limited or its affiliates.
#
# Release Information : HERCULESAE-MP106-r0p1-00eac0
#
#-----------------------------------------------------------------------------
# Makefile include file for AArch32 crypto. This must be included from the
# top-level Makefile; it is not a standalone Makefile.
#-----------------------------------------------------------------------------
# Note these variables must only be used in places where Make reads their
# immediate values rather than their deferred values. This is because all
# the include files use the same variables and the deferred evaluation will
# yeild the last values set by the last include file. They can be used in the
# target and prerequisite sections of rule definitions, which are evaluated
# immediately, but not in the recipe, where evaluation is deferred.
srcdir := aarch32/crypto
common_srcdir := common/crypto
libdir := common/shared
dstdir := aarch32/crypto
target := $(dstdir)/crypto.elf
csrcs := $(wildcard $(common_srcdir)/*.c)
asmsrcs := $(wildcard $(srcdir)/*.s)
libsrcs := $(wildcard $(libdir)/*.c)
cobjs := $(patsubst $(common_srcdir)/%.c,$(dstdir)/%.o,$(csrcs)) \
$(patsubst $(libdir)/%.c,$(dstdir)/%.o,$(libsrcs))
asmobjs := $(patsubst %.s,%.o,$(asmsrcs))
# Find common C files (the source files are not in the build target directory)
vpath %.c $(common_srcdir) $(libdir)
# Change the CPU target to include crypto for all files that need compiling
$(asmobjs): ARCH = armv8-a+crypto
$(asmobjs): %.o: %.s
@echo " [ASM ] $<"
@$(ASM32) $(ASM_OPTS_AARCH32) $< -o $@
$(cobjs): $(dstdir)/%.o: %.c
@echo " [CC $(CC32) ] $<"
ifeq ($(strip $(GCC)), yes)
@$(CC32) $(subst -funroll-loops ,,$(CC_OPTS_AARCH32)) -O3 -mword-relocations -fno-inline-functions -fno-inline $(foreach inc,$(^D),-I$(inc)) -I$(common_shared) $< -o $@
else
@$(CC32) -mfpu=none $(subst -funroll-loops ,,$(CC_OPTS_AARCH32)) -O3 -fno-inline-functions -fno-inline $(foreach inc,$(^D),-I$(inc)) -I$(common_shared) $< -o $@
endif
# Link. For C-based tests this is done through GCC to make sure that all
# standard libraries are set up correctly.
$(target): $(asmobjs) $(cobjs) $(aarch32_bootobj) $(aarch32_c_bootobj)
@echo " [LINK] $<"
ifeq ($(strip $(GCC)), yes)
@$(CC32) $(LINK_OPTS_CSRC_AARCH32) $^ -o $@
else
@$(LD32) $(LINK_OPTS_CSRC_AARCH32) $^ -o $@
endif
# ex: syntax=make:

BIN
Security Algo Accelerator/logical/testbench/execution_tb/tests/aarch32/crypto/crypto.elf
View File

Binary file not shown.

BIN
Security Algo Accelerator/logical/testbench/execution_tb/tests/aarch32/crypto/crypto_aarch32el0.elf
View File

Binary file not shown.

212
Security Algo Accelerator/logical/testbench/execution_tb/tests/aarch32/crypto/crypto_functions.s
View File

@ -1,212 +0,0 @@
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2013-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//------------------------------------------------------------------------------
// Description:
//
// This file defines assembler functions that are called from C in the main
// crypto test
//------------------------------------------------------------------------------
.section testcode, "ax", %progbits
//------------------------------------------------------------------------------
// Macros
//------------------------------------------------------------------------------
.macro aes128_key_expand_step rcon
VTBL.8 d26, {d22, d23}, d28
VTBL.8 d27, {d22, d23}, d29
AESE.8 q13, q12
VMOV.I32 q15, #\rcon
VEOR q13, q13, q15
VEXT.8 q15, q12, q11, #12
VEOR q11, q11, q15
VEXT.8 q15, q12, q15, #12
VEOR q11, q11, q15
VEXT.8 q15, q12, q15, #12
VEOR q11, q11, q15
VEOR q11, q11, q13
.endm
//------------------------------------------------------------------------------
// Function: aes128_key_expand
//------------------------------------------------------------------------------
.global aes128_key_expand
.type aes128_key_expand, %function
aes128_key_expand:
// C arguments:
// r0: const unsigned char *key_in
// r1: unsigned char *key_out
// Return: void
VLD1.8 {d22-d23}, [r0]
MOV r2, #0
VDUP.8 q12, r2
LDR r2, =0x0c0f0e0d
VDUP.32 q14, r2
VST1.8 {d22}, [r1]
ADD r1, r1, #8
VST1.8 {d23}, [r1]
ADD r1, r1, #8
aes128_key_expand_step 0x01
VST1.8 {d22}, [r1]
ADD r1, r1, #8
VST1.8 {d23}, [r1]
ADD r1, r1, #8
aes128_key_expand_step 0x02
VST1.8 {d22}, [r1]
ADD r1, r1, #8
VST1.8 {d23}, [r1]
ADD r1, r1, #8
aes128_key_expand_step 0x04
VST1.8 {d22}, [r1]
ADD r1, r1, #8
VST1.8 {d23}, [r1]
ADD r1, r1, #8
aes128_key_expand_step 0x08
VST1.8 {d22}, [r1]
ADD r1, r1, #8
VST1.8 {d23}, [r1]
ADD r1, r1, #8
aes128_key_expand_step 0x10
VST1.8 {d22}, [r1]
ADD r1, r1, #8
VST1.8 {d23}, [r1]
ADD r1, r1, #8
aes128_key_expand_step 0x20
VST1.8 {d22}, [r1]
ADD r1, r1, #8
VST1.8 {d23}, [r1]
ADD r1, r1, #8
aes128_key_expand_step 0x40
VST1.8 {d22}, [r1]
ADD r1, r1, #8
VST1.8 {d23}, [r1]
ADD r1, r1, #8
aes128_key_expand_step 0x80
VST1.8 {d22}, [r1]
ADD r1, r1, #8
VST1.8 {d23}, [r1]
ADD r1, r1, #8
aes128_key_expand_step 0x1B
VST1.8 {d22}, [r1]
ADD r1, r1, #8
VST1.8 {d23}, [r1]
ADD r1, r1, #8
aes128_key_expand_step 0x36
VST1.8 {d22}, [r1]
ADD r1, r1, #8
VST1.8 {d23}, [r1]
ADD r1, r1, #8
BX lr
//------------------------------------------------------------------------------
// Function: aes128_ecb_encrypt
//------------------------------------------------------------------------------
.global aes128_ecb_encrypt
.type aes128_ecb_encrypt, %function
aes128_ecb_encrypt:
// C arguments:
// r0: const unsigned char *key
// r1: const unsigned char *in_data
// r2: unsigned char *out_data
// r3: unsigned int size
// Return: void
VLD1.8 {d10-d13}, [r0]
ADD r0, r0, #32
VLD1.8 {d14-d17}, [r0]
ADD r0, r0, #32
VLD1.8 {d18-d21}, [r0]
ADD r0, r0, #32
VLD1.8 {d22-d25}, [r0]
ADD r0, r0, #32
VLD1.8 {d26-d29}, [r0]
ADD r0, r0, #32
VLD1.8 {d30-d31}, [r0]
aes128_ecb_enc_loop:
// Load data
VLD1.8 {d0-d3}, [r1]
ADD r1, r1, #32
// Round 1
AESE.8 q0, q5
AESMC.8 q0, q0
AESE.8 q1, q5
AESMC.8 q1, q1
// Round 2
AESE.8 q0, q6
AESMC.8 q0, q0
AESE.8 q1, q6
AESMC.8 q1, q1
// Round 3
AESE.8 q0, q7
AESMC.8 q0, q0
AESE.8 q1, q7
AESMC.8 q1, q1
// Round 4
AESE.8 q0, q8
AESMC.8 q0, q0
AESE.8 q1, q8
AESMC.8 q1, q1
// Round 5
AESE.8 q0, q9
AESMC.8 q0, q0
AESE.8 q1, q9
AESMC.8 q1, q1
// Round 6
AESE.8 q0, q10
AESMC.8 q0, q0
AESE.8 q1, q10
AESMC.8 q1, q1
// Round 7
AESE.8 q0, q11
AESMC.8 q0, q0
AESE.8 q1, q11
AESMC.8 q1, q1
// Round 8
AESE.8 q0, q12
AESMC.8 q0, q0
AESE.8 q1, q12
AESMC.8 q1, q1
// Round 9
AESE.8 q0, q13
AESMC.8 q0, q0
AESE.8 q1, q13
AESMC.8 q1, q1
// Round 10
AESE.8 q0, q14
PLD [r1, #64]
AESE.8 q1, q14
VEOR q0, q0, q15
SUBS r3, r3, #16
VST1.8 {d0-d1}, [r2]
ADD r2, r2, #16
BEQ aes128_ecb_enc_exit
VEOR q1, q1, q15
SUBS r3, r3, #16
VST1.8 {d2-d3}, [r2]
ADD r2, r2, #16
BGT aes128_ecb_enc_loop
aes128_ecb_enc_exit:
BX lr

63
Security Algo Accelerator/logical/testbench/execution_tb/tests/aarch64/crypto/Makefile.inc
View File

@ -1,63 +0,0 @@
#-------------------------------------------------------------------------------
# The confidential and proprietary information contained in this file may
# only be used by a person authorised under and to the extent permitted
# by a subsisting licensing agreement from ARM Limited or its affiliates.
#
# (C) COPYRIGHT 2013-2020 ARM Limited or its affiliates.
# ALL RIGHTS RESERVED
#
# This entire notice must be reproduced on all copies of this file
# and copies of this file may only be made by a person if such person is
# permitted to do so under the terms of a subsisting license agreement
# from ARM Limited or its affiliates.
#
# Release Information : HERCULESAE-MP106-r0p1-00eac0
#
#-------------------------------------------------------------------------------
# Makefile include file for AArch64 crypto. This must be included from the
# top-level Makefile; it is not a standalone Makefile.
#-------------------------------------------------------------------------------
# Note these variables must only be used in places where Make reads their
# immediate values rather than their deferred values. This is because all
# the include files use the same variables and the deferred evaluation will
# yield the last values set by the last include file. They can be used in the
# target and prerequisite sections of rule definitions, which are evaluated
# immediately, but not in the recipe, where evaluation is deferred.
srcdir := aarch64/crypto
common_srcdir := common/crypto
libdir := common/shared
dstdir := aarch64/crypto
target := $(dstdir)/crypto.elf
asmsrcs := $(wildcard $(srcdir)/*.s)
csrcs := $(wildcard $(common_srcdir)/*.c)
libsrcs := $(wildcard $(libdir)/*.c)
asmobjs := $(patsubst %.s,%.o,$(asmsrcs))
cobjs := $(patsubst $(common_srcdir)/%.c,$(dstdir)/%.o,$(csrcs)) \
$(patsubst $(libdir)/%.c,$(dstdir)/%.o,$(libsrcs))
# Find common C files (the source files are not in the build target directory)
vpath %.c $(common_srcdir) $(libdir)
# Change the CPU target to include crypto for all files that need compiling
$(cobjs) $(asmobjs): ARCH = armv8-a+crypto
$(asmobjs): %.o: %.s
@echo " [ASM ] $<"
@$(ASM64) $(ASM_OPTS_AARCH64) $< -o $@
$(cobjs): $(dstdir)/%.o: %.c
@echo " [CC ] $<"
@$(CC64) $(CC_OPTS_AARCH64) -I$(common_shared) $< -o $@
# Link. For C-based tests this is done through GCC to make sure that all
# standard libraries are set up correctly.
$(target): $(asmobjs) $(cobjs) $(aarch64_bootobj)
@echo " [LINK] $<"
ifeq ($(strip $(GCC)), yes)
@$(CC64) $(LINK_OPTS_CSRC_AARCH64) $^ -o $@
else
@$(LD64) $(LINK_OPTS_CSRC_AARCH64) $^ -o $@
endif
# ex: syntax=make:

BIN
Security Algo Accelerator/logical/testbench/execution_tb/tests/aarch64/crypto/crypto.elf
View File

Binary file not shown.

166
Security Algo Accelerator/logical/testbench/execution_tb/tests/aarch64/crypto/crypto_functions.s
View File

@ -1,166 +0,0 @@
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2012-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//------------------------------------------------------------------------------
// Description:
//
// This file defines assembler functions that are called from C in the main
// crypto test
//------------------------------------------------------------------------------
.section .text, "ax", %progbits
//------------------------------------------------------------------------------
// Macros
//------------------------------------------------------------------------------
.macro aes128_key_expand_step rcon
TBL v18.16B, {v16.16B}, v19.16B
AESE v18.16B, v17.16B
MOVI v20.4S, #\rcon
EOR v18.16B, v18.16B, v20.16B
EXT v20.16B, v17.16B, v16.16B, #12
EOR v16.16B, v16.16B, v20.16B
EXT v20.16B, v17.16B, v20.16B, #12
EOR v16.16B, v16.16B, v20.16B
EXT v20.16B, v17.16B, v20.16B, #12
EOR v16.16B, v16.16B, v20.16B
EOR v16.16B, v16.16B, v18.16B
.endm
//------------------------------------------------------------------------------
// Function: aes128_key_expand
//------------------------------------------------------------------------------
.global aes128_key_expand
.type aes128_key_expand, %function
aes128_key_expand:
// C arguments:
// r0: const unsigned char *key_in
// r1: unsigned char *key_out
// Return: void
LD1 {v16.16B}, [x0]
MOVZ w2, #0x0e0d
DUP v17.16B, wzr
movk w2, #0xc0f, lsl #16
DUP v19.4S, w2
ST1 {v16.16B}, [x1], #16
aes128_key_expand_step 0x01
ST1 {v16.16B}, [x1], #16
aes128_key_expand_step 0x02
ST1 {v16.16B}, [x1], #16
aes128_key_expand_step 0x04
ST1 {v16.16B}, [x1], #16
aes128_key_expand_step 0x08
ST1 {v16.16B}, [x1], #16
aes128_key_expand_step 0x10
ST1 {v16.16B}, [x1], #16
aes128_key_expand_step 0x20
ST1 {v16.16B}, [x1], #16
aes128_key_expand_step 0x40
ST1 {v16.16B}, [x1], #16
aes128_key_expand_step 0x80
ST1 {v16.16B}, [x1], #16
aes128_key_expand_step 0x1B
ST1 {v16.16B}, [x1], #16
aes128_key_expand_step 0x36
ST1 {v16.16B}, [x1]
RET
//------------------------------------------------------------------------------
// Function: aes128_ecb_encrypt
//------------------------------------------------------------------------------
.global aes128_ecb_encrypt
.type aes128_ecb_encrypt, %function
aes128_ecb_encrypt:
// C arguments:
// r0: const unsigned char *key
// r1: const unsigned char *in_data
// r2: unsigned char *out_data
// r3: unsigned int size
// Return: void
LD1 {v16.16B-v19.16B}, [x0], #64
LD1 {v20.16B-v23.16B}, [x0], #64
LD1 {v24.16B-v26.16B}, [x0]
aes128_ecb_enc_loop:
// Load data
LD1 {v0.16B-v1.16B}, [x1], #32
// Round 1
AESE v0.16B, v16.16B
AESMC v0.16B, v0.16B
AESE v1.16B, v16.16B
AESMC v1.16B, v1.16B
// Round 2
AESE v0.16B, v17.16B
AESMC v0.16B, v0.16B
AESE v1.16B, v17.16B
AESMC v1.16B, v1.16B
// Round 3
AESE v0.16B, v18.16B
AESMC v0.16B, v0.16B
AESE v1.16B, v18.16B
AESMC v1.16B, v1.16B
// Round 4
AESE v0.16B, v19.16B
AESMC v0.16B, v0.16B
AESE v1.16B, v19.16B
AESMC v1.16B, v1.16B
// Round 5
AESE v0.16B, v20.16B
AESMC v0.16B, v0.16B
AESE v1.16B, v20.16B
AESMC v1.16B, v1.16B
// Round 6
AESE v0.16B, v21.16B
AESMC v0.16B, v0.16B
AESE v1.16B, v21.16B
AESMC v1.16B, v1.16B
// Round 7
AESE v0.16B, v22.16B
AESMC v0.16B, v0.16B
AESE v1.16B, v22.16B
AESMC v1.16B, v1.16B
// Round 8
AESE v0.16B, v23.16B
AESMC v0.16B, v0.16B
AESE v1.16B, v23.16B
AESMC v1.16B, v1.16B
// Round 9
AESE v0.16B, v24.16B
AESMC v0.16B, v0.16B
AESE v1.16B, v24.16B
AESMC v1.16B, v1.16B
// Round 10
AESE v0.16B, v25.16B
PRFM PLDL1KEEP, [x1, #64]
AESE v1.16B, v25.16B
EOR v0.16B, v0.16B, v26.16B
SUBS x3, x3, #16
ST1 {v0.16B}, [x2], #16
B.EQ aes128_ecb_enc_exit
EOR v1.16B, v1.16B, v26.16B
SUBS x3, x3, #16
ST1 {v1.16B}, [x2], #16
B.GT aes128_ecb_enc_loop
aes128_ecb_enc_exit:
RET

1586
Security Algo Accelerator/logical/testbench/execution_tb/tests/common/crypto/aesdata.c
View File

File diff suppressed because it is too large Load Diff

72
Security Algo Accelerator/logical/testbench/execution_tb/tests/common/crypto/crypto_aes.c
View File

@ -1,72 +0,0 @@
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2012-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//------------------------------------------------------------------------------
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include "benchmark.h"
static const uint8_t key[] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff};
extern const uint8_t aes128_ecb_encrypt_input[][4096];
extern const uint8_t aes128_ecb_encrypt_ref_output[][4096];
extern uint8_t aes128_ecb_encrypt_output[][4096];
// Function prototypes for asm functions
extern void aes128_key_expand(const unsigned char *key_in, unsigned char *key_out);
extern void aes128_ecb_encrypt(const unsigned char *key, const unsigned char *in_data, unsigned char *out_data, unsigned int size);
extern uint32_t have_crypto;
int main()
{
int bs;
int i;
int fail = 0;
uint8_t kv[176];
started();
if ( !have_crypto ) {
printf("Cryptographic extension not available on this PE.\n");
exit(144); // something gross
}
aes128_key_expand(key, kv);
for (i = 0, bs = 16; bs <= 4096; i++, bs*=2) {
uint32_t cmpres;
aes128_ecb_encrypt(kv, aes128_ecb_encrypt_input[i], aes128_ecb_encrypt_output[i], bs);
cmpres = (memcmp(aes128_ecb_encrypt_output[i], aes128_ecb_encrypt_ref_output[i], bs) != 0);
aes128_ecb_encrypt(kv, aes128_ecb_encrypt_input[i], aes128_ecb_encrypt_output[i], bs);
cmpres |= (memcmp(aes128_ecb_encrypt_output[i], aes128_ecb_encrypt_ref_output[i], bs) != 0);
if (cmpres != 0)
fail = 1;
}
return fail;
}

41
Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/Makefile_A64.inc
View File

@ -1,41 +0,0 @@
###############################################################################
# The confidential and proprietary information contained in this file may
# only be used by a person authorised under and to the extent permitted
# by a subsisting licensing agreement from ARM Limited.
#
# (C) COPYRIGHT 2011-2013 ARM Limited.
# ALL RIGHTS RESERVED
#
# This entire notice must be reproduced on all copies of this file
# and copies of this file may only be made by a person if such person is
# permitted to do so under the terms of a subsisting license agreement
# from ARM Limited.
#
###############################################################################
# Makefile.inc for crypto64
# setup source paths (crypto64)
crypto64_base = crypto64
crypto64_src = $(crypto64_base)/src
crypto64_obj = $(crypto64_base)/obj
crypto64_elf = $(crypto64_base)/elf
#rules for crypto64
crypto64_asm_obj = $(incl_obj)/benchmark_boot_a64.o $(incl_obj)/vectors.o $(incl_obj)/num_cpus_a64.o $(crypto64_obj)/cryptolib_asm64.o
crypto64_c_obj = $(incl_obj)/sys_a64.o $(incl_obj)/stackheap_a64.o $(crypto64_obj)/cryptodata.o $(crypto64_obj)/crypto_test.o
crypto64: clean_crypto64 $(crypto64_elf)/crypto64.elf
$(crypto64_obj)/%.o: $(crypto64_src)/%.c
$(CC_A64) $(CC_A64_OPTS) $< -o $@
$(crypto64_obj)/%.o: $(crypto64_src)/%.s
$(AS_A64) $(AS_A64_OPTS) $< -o $@
$(crypto64_elf)/crypto64.elf: $(crypto64_asm_obj) $(crypto64_c_obj)
$(LINK_A64) $(LINK_A64_OPTS) $(crypto64_asm_obj) $(crypto64_c_obj) -o $@
clean_crypto64:
\rm -f $(crypto64_asm_obj) $(crypto64_c_obj) $(crypto64_elf)/crypto64.elf

BIN
Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/elf/crypto64.elf
View File

Binary file not shown.

80
Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/crypto_test.c
View File

@ -1,80 +0,0 @@
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
// (C) COPYRIGHT 2012-2013 ARM Limited.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//
// SVN Information
//
// Checked In : $Date: 2013-03-19 09:12:51 +0000 (Tue, 19 Mar 2013) $
//
// Revision : $Revision: 241584 $
//
// Release Information :
//
//-----------------------------------------------------------------------------
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include "cryptolib.h"
#include "cryptodata.h"
#include "benchmark.h"
#ifndef BLOCK_SIZE
#define BLOCK_SIZE 1024
#endif
#ifndef ITERATIONS
#define ITERATIONS 10
#endif
uint8_t get_aes_index( int block_size)
{
uint8_t index = 0;
uint8_t i;
for (i=4; i<13; i++)
{
if ((block_size >> i) & 0x1)
{
index = i-4;
break;
}
}
return index;
}
int main()
{
uint32_t block_size;
uint8_t index;
uint32_t cmpres = 0;
uint8_t i;
block_size = BLOCK_SIZE;
uint8_t kv[176];
printf("AES128-ECB encryption\n");
index = get_aes_index(block_size);
BENCHSTART
for ( i = 0; i < ITERATIONS; i++)
{
aes128_key_expand(aes128_ecb_encrypt_key[index], kv);
LOOPSTART
aes128_ecb_encrypt(kv, aes128_ecb_encrypt_input[index], aes128_ecb_encrypt_output[index], block_size);
LOOPEND
}
cmpres |= memcmp(aes128_ecb_encrypt_output[index], aes128_ecb_encrypt_ref_output[index], block_size);
if (cmpres)
printf("AES128-ECB encryption failed\n");
BENCHFINISHED
}

1591
Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptodata.c
View File

File diff suppressed because it is too large Load Diff

5
Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptodata.h
View File

@ -1,5 +0,0 @@
extern const unsigned char aes128_ecb_encrypt_key[][16];
extern const unsigned char aes128_ecb_encrypt_input[][4096];
extern const unsigned char aes128_ecb_encrypt_ref_output[][4096];
extern unsigned char aes128_ecb_encrypt_output[][4096];

26
Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptolib.h
View File

@ -1,26 +0,0 @@
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
// (C) COPYRIGHT 2012-2013 ARM Limited.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//
// SVN Information
//
// Checked In : $Date: 2013-03-19 09:12:51 +0000 (Tue, 19 Mar 2013) $
//
// Revision : $Revision: 241584 $
//
// Release Information :
//
//-----------------------------------------------------------------------------
extern void aes128_key_expand(const unsigned char *key_in, unsigned char *key_out);
extern void aes128_ecb_encrypt(const unsigned char *key, const unsigned char *in_data, unsigned char *out_data, unsigned int size);

138
Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptolib_asm64.s
View File

@ -1,138 +0,0 @@
;#-----------------------------------------------------------------------------
;# The confidential and proprietary information contained in this file may
;# only be used by a person authorised under and to the extent permitted
;# by a subsisting licensing agreement from ARM Limited.
;#
;# (C) COPYRIGHT 2012-2013 ARM Limited.
;# ALL RIGHTS RESERVED
;#
;# This entire notice must be reproduced on all copies of this file
;# and copies of this file may only be made by a person if such person is
;# permitted to do so under the terms of a subsisting license agreement
;# from ARM Limited.
;#
;# SVN Information
;#
;# Checked In : $Date: 2013-03-19 09:12:51 +0000 (Tue, 19 Mar 2013) $
;#
;# Revision : $Revision: 241584 $
;#
;# Release Information :
;#
;#-----------------------------------------------------------------------------
.section aes_code, "ax"
.global aes128_key_expand
.global aes128_ecb_encrypt
.align 6
rcon_array:
.word 0x00000001
.word 0x00000002
.word 0x00000004
.word 0x00000008
.word 0x00000010
.word 0x00000020
.word 0x00000040
.word 0x00000080
.word 0x0000001b
.word 0x00000036
.align 6
;# void aes128_key_expand(const unsigned char *key_in, unsigned char *key_out)
.type aes128_key_expand STT_FUNC
aes128_key_expand:
LD1 {v16.16B}, [x0]
MOVZ w2, #0x0e0d
DUP v17.16B, wzr
MOVK w2, #0x0c0f, lsl #16
DUP v19.4S, w2
ADR x3, rcon_array
MOV w4, #10
exp:
TBL v18.16B, {v16.16B}, v19.16B
LD1R {v21.4S}, [x3], #4
AESE v18.16B, v17.16B
EXT v20.16B, v17.16B, v16.16B, #12
SHA1SU0 v21.4S, v18.4S, v17.4S
EOR v22.16B, v16.16B, v20.16B
ST1 {v16.16B}, [x1], #16
SHA1SU0 v21.4S, v22.4S, v22.4S
TBL v18.16B, {v21.16B}, v19.16B
LD1R {v16.4S}, [x3], #4
AESE v18.16B, v17.16B
EXT v20.16B, v17.16B, v21.16B, #12
SHA1SU0 v16.4S, v18.4S, v17.4S
EOR v22.16B, v21.16B, v20.16B
ST1 {v21.16B}, [x1], #16
SUBS w4, w4, #2
SHA1SU0 v16.4S, v22.4S, v22.4S
B.NE exp
ST1 {v16.16B}, [x1]
RET
.macro aes_enc_round keyreg
AESE v0.16B, \keyreg
AESMC v0.16B, v0.16B
AESE v1.16B, \keyreg
AESMC v1.16B, v1.16B
AESE v2.16B, \keyreg
AESMC v2.16B, v2.16B
.endm
.macro aes_dec_round keyreg
AESD v0.16B, \keyreg
AESIMC v0.16B, v0.16B
AESD v1.16B, \keyreg
AESIMC v1.16B, v1.16B
AESD v2.16B, \keyreg
AESIMC v2.16B, v2.16B
.endm
;# void aes128_ecb_encrypt(const unsigned char *key, const unsigned char *in_data, unsigned char *out_data, unsigned int size)
.type aes128_ecb_encrypt STT_FUNC
aes128_ecb_encrypt:
;# Load the key
LD1 {v16.16B-v19.16B}, [x0], #64
LD1 {v20.16B-v23.16B}, [x0], #64
LD1 {v24.16B-v26.16B}, [x0]
load_ip:
;# Load data
LD1 {v0.16B-v2.16B}, [x1], #48
;# Rounds 1-9
aes_enc_round v16.16B
aes_enc_round v17.16B
aes_enc_round v18.16B
aes_enc_round v19.16B
aes_enc_round v20.16B
aes_enc_round v21.16B
aes_enc_round v22.16B
aes_enc_round v23.16B
aes_enc_round v24.16B
;# Round 10
AESE v0.16B, v25.16B
PRFM PLDL1KEEP, [x1, #64]
EOR v0.16B, v0.16B, v26.16B
SUBS x3, x3, #16
ST1 {v0.16B}, [x2], #16
B.EQ end_enc
AESE v1.16B, v25.16B
EOR v1.16B, v1.16B, v26.16B
SUBS x3, x3, #16
ST1 {v1.16B}, [x2], #16
B.EQ end_enc
AESE v2.16B, v25.16B
EOR v2.16B, v2.16B, v26.16B
SUBS x3, x3, #16
ST1 {v2.16B}, [x2], #16
B.GT load_ip
end_enc:
RET
.end

22
include/uapi/linux/loadpin.h Normal file
View File

@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
* Copyright (c) 2022, Google LLC
*/
#ifndef _UAPI_LINUX_LOOP_LOADPIN_H
#define _UAPI_LINUX_LOOP_LOADPIN_H
#define LOADPIN_IOC_MAGIC 'L'
/**
* LOADPIN_IOC_SET_TRUSTED_VERITY_DIGESTS - Set up the root digests of verity devices
* that loadpin should trust.
*
* Takes a file descriptor from which to read the root digests of trusted verity devices. The file
* is expected to contain a list of digests in ASCII format, with one line per digest. The ioctl
* must be issued on the securityfs attribute 'loadpin/dm-verity' (which can be typically found
* under /sys/kernel/security/loadpin/dm-verity).
*/
#define LOADPIN_IOC_SET_TRUSTED_VERITY_DIGESTS _IOW(LOADPIN_IOC_MAGIC, 0x00, unsigned int)
#endif /* _UAPI_LINUX_LOOP_LOADPIN_H */

80
include/uapi/linux/sev-guest.h Normal file
View File

@ -0,0 +1,80 @@
/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
/*
* Userspace interface for AMD SEV and SNP guest driver.
*
* Copyright (C) 2021 Advanced Micro Devices, Inc.
*
* Author: Brijesh Singh <brijesh.singh@amd.com>
*
* SEV API specification is available at: https://developer.amd.com/sev/
*/
#ifndef __UAPI_LINUX_SEV_GUEST_H_
#define __UAPI_LINUX_SEV_GUEST_H_
#include <linux/types.h>
struct snp_report_req {
/* user data that should be included in the report */
__u8 user_data[64];
/* The vmpl level to be included in the report */
__u32 vmpl;
/* Must be zero filled */
__u8 rsvd[28];
};
struct snp_report_resp {
/* response data, see SEV-SNP spec for the format */
__u8 data[4000];
};
struct snp_derived_key_req {
__u32 root_key_select;
__u32 rsvd;
__u64 guest_field_select;
__u32 vmpl;
__u32 guest_svn;
__u64 tcb_version;
};
struct snp_derived_key_resp {
/* response data, see SEV-SNP spec for the format */
__u8 data[64];
};
struct snp_guest_request_ioctl {
/* message version number (must be non-zero) */
__u8 msg_version;
/* Request and response structure address */
__u64 req_data;
__u64 resp_data;
/* firmware error code on failure (see psp-sev.h) */
__u64 fw_err;
};
struct snp_ext_report_req {
struct snp_report_req data;
/* where to copy the certificate blob */
__u64 certs_address;
/* length of the certificate blob */
__u32 certs_len;
};
#define SNP_GUEST_REQ_IOC_TYPE 'S'
/* Get SNP attestation report */
#define SNP_GET_REPORT _IOWR(SNP_GUEST_REQ_IOC_TYPE, 0x0, struct snp_guest_request_ioctl)
/* Get a derived key from the root */
#define SNP_GET_DERIVED_KEY _IOWR(SNP_GUEST_REQ_IOC_TYPE, 0x1, struct snp_guest_request_ioctl)
/* Get SNP extended report as defined in the GHCB specification version 2. */
#define SNP_GET_EXT_REPORT _IOWR(SNP_GUEST_REQ_IOC_TYPE, 0x2, struct snp_guest_request_ioctl)
#endif /* __UAPI_LINUX_SEV_GUEST_H_ */

227
include/uapi/linux/ublk_cmd.h Normal file
View File

@ -0,0 +1,227 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
#ifndef USER_BLK_DRV_CMD_INC_H
#define USER_BLK_DRV_CMD_INC_H
#include <linux/types.h>
/* ublk server command definition */
/*
* Admin commands, issued by ublk server, and handled by ublk driver.
*/
#define UBLK_CMD_GET_QUEUE_AFFINITY 0x01
#define UBLK_CMD_GET_DEV_INFO 0x02
#define UBLK_CMD_ADD_DEV 0x04
#define UBLK_CMD_DEL_DEV 0x05
#define UBLK_CMD_START_DEV 0x06
#define UBLK_CMD_STOP_DEV 0x07
#define UBLK_CMD_SET_PARAMS 0x08
#define UBLK_CMD_GET_PARAMS 0x09
/*
* IO commands, issued by ublk server, and handled by ublk driver.
*
* FETCH_REQ: issued via sqe(URING_CMD) beforehand for fetching IO request
* from ublk driver, should be issued only when starting device. After
* the associated cqe is returned, request's tag can be retrieved via
* cqe->userdata.
*
* COMMIT_AND_FETCH_REQ: issued via sqe(URING_CMD) after ublkserver handled
* this IO request, request's handling result is committed to ublk
* driver, meantime FETCH_REQ is piggyback, and FETCH_REQ has to be
* handled before completing io request.
*
* NEED_GET_DATA: only used for write requests to set io addr and copy data
* When NEED_GET_DATA is set, ublksrv has to issue UBLK_IO_NEED_GET_DATA
* command after ublk driver returns UBLK_IO_RES_NEED_GET_DATA.
*
* It is only used if ublksrv set UBLK_F_NEED_GET_DATA flag
* while starting a ublk device.
*/
#define UBLK_IO_FETCH_REQ 0x20
#define UBLK_IO_COMMIT_AND_FETCH_REQ 0x21
#define UBLK_IO_NEED_GET_DATA 0x22
/* only ABORT means that no re-fetch */
#define UBLK_IO_RES_OK 0
#define UBLK_IO_RES_NEED_GET_DATA 1
#define UBLK_IO_RES_ABORT (-ENODEV)
#define UBLKSRV_CMD_BUF_OFFSET 0
#define UBLKSRV_IO_BUF_OFFSET 0x80000000
/* tag bit is 12bit, so at most 4096 IOs for each queue */
#define UBLK_MAX_QUEUE_DEPTH 4096
/*
* zero copy requires 4k block size, and can remap ublk driver's io
* request into ublksrv's vm space
*/
#define UBLK_F_SUPPORT_ZERO_COPY (1ULL << 0)
/*
* Force to complete io cmd via io_uring_cmd_complete_in_task so that
* performance comparison is done easily with using task_work_add
*/
#define UBLK_F_URING_CMD_COMP_IN_TASK (1ULL << 1)
/*
* User should issue io cmd again for write requests to
* set io buffer address and copy data from bio vectors
* to the userspace io buffer.
*
* In this mode, task_work is not used.
*/
#define UBLK_F_NEED_GET_DATA (1UL << 2)
/* device state */
#define UBLK_S_DEV_DEAD 0
#define UBLK_S_DEV_LIVE 1
/* shipped via sqe->cmd of io_uring command */
struct ublksrv_ctrl_cmd {
/* sent to which device, must be valid */
__u32 dev_id;
/* sent to which queue, must be -1 if the cmd isn't for queue */
__u16 queue_id;
/*
* cmd specific buffer, can be IN or OUT.
*/
__u16 len;
__u64 addr;
/* inline data */
__u64 data[2];
};
struct ublksrv_ctrl_dev_info {
__u16 nr_hw_queues;
__u16 queue_depth;
__u16 state;
__u16 pad0;
__u32 max_io_buf_bytes;
__u32 dev_id;
__s32 ublksrv_pid;
__u32 pad1;
__u64 flags;
/* For ublksrv internal use, invisible to ublk driver */
__u64 ublksrv_flags;
__u64 reserved0;
__u64 reserved1;
__u64 reserved2;
};
#define UBLK_IO_OP_READ 0
#define UBLK_IO_OP_WRITE 1
#define UBLK_IO_OP_FLUSH 2
#define UBLK_IO_OP_DISCARD 3
#define UBLK_IO_OP_WRITE_SAME 4
#define UBLK_IO_OP_WRITE_ZEROES 5
#define UBLK_IO_F_FAILFAST_DEV (1U << 8)
#define UBLK_IO_F_FAILFAST_TRANSPORT (1U << 9)
#define UBLK_IO_F_FAILFAST_DRIVER (1U << 10)
#define UBLK_IO_F_META (1U << 11)
#define UBLK_IO_F_FUA (1U << 13)
#define UBLK_IO_F_NOUNMAP (1U << 15)
#define UBLK_IO_F_SWAP (1U << 16)
/*
* io cmd is described by this structure, and stored in share memory, indexed
* by request tag.
*
* The data is stored by ublk driver, and read by ublksrv after one fetch command
* returns.
*/
struct ublksrv_io_desc {
/* op: bit 0-7, flags: bit 8-31 */
__u32 op_flags;
__u32 nr_sectors;
/* start sector for this io */
__u64 start_sector;
/* buffer address in ublksrv daemon vm space, from ublk driver */
__u64 addr;
};
static inline __u8 ublksrv_get_op(const struct ublksrv_io_desc *iod)
{
return iod->op_flags & 0xff;
}
static inline __u32 ublksrv_get_flags(const struct ublksrv_io_desc *iod)
{
return iod->op_flags >> 8;
}
/* issued to ublk driver via /dev/ublkcN */
struct ublksrv_io_cmd {
__u16 q_id;
/* for fetch/commit which result */
__u16 tag;
/* io result, it is valid for COMMIT* command only */
__s32 result;
/*
* userspace buffer address in ublksrv daemon process, valid for
* FETCH* command only
*/
__u64 addr;
};
struct ublk_param_basic {
#define UBLK_ATTR_READ_ONLY (1 << 0)
#define UBLK_ATTR_ROTATIONAL (1 << 1)
#define UBLK_ATTR_VOLATILE_CACHE (1 << 2)
#define UBLK_ATTR_FUA (1 << 3)
__u32 attrs;
__u8 logical_bs_shift;
__u8 physical_bs_shift;
__u8 io_opt_shift;
__u8 io_min_shift;
__u32 max_sectors;
__u32 chunk_sectors;
__u64 dev_sectors;
__u64 virt_boundary_mask;
};
struct ublk_param_discard {
__u32 discard_alignment;
__u32 discard_granularity;
__u32 max_discard_sectors;
__u32 max_write_zeroes_sectors;
__u16 max_discard_segments;
__u16 reserved0;
};
struct ublk_params {
/*
* Total length of parameters, userspace has to set 'len' for both
* SET_PARAMS and GET_PARAMS command, and driver may update len
* if two sides use different version of 'ublk_params', same with
* 'types' fields.
*/
__u32 len;
#define UBLK_PARAM_TYPE_BASIC (1 << 0)
#define UBLK_PARAM_TYPE_DISCARD (1 << 1)
__u32 types; /* types of parameter included */
struct ublk_param_basic basic;
struct ublk_param_discard discard;
};
#endif

49
include/uapi/rdma/erdma-abi.h Normal file
View File

@ -0,0 +1,49 @@
/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
/*
* Copyright (c) 2020-2022, Alibaba Group.
*/
#ifndef __ERDMA_USER_H__
#define __ERDMA_USER_H__
#include <linux/types.h>
#define ERDMA_ABI_VERSION 1
struct erdma_ureq_create_cq {
__aligned_u64 db_record_va;
__aligned_u64 qbuf_va;
__u32 qbuf_len;
__u32 rsvd0;
};
struct erdma_uresp_create_cq {
__u32 cq_id;
__u32 num_cqe;
};
struct erdma_ureq_create_qp {
__aligned_u64 db_record_va;
__aligned_u64 qbuf_va;
__u32 qbuf_len;
__u32 rsvd0;
};
struct erdma_uresp_create_qp {
__u32 qp_id;
__u32 num_sqe;
__u32 num_rqe;
__u32 rq_offset;
};
struct erdma_uresp_alloc_ctx {
__u32 dev_id;
__u32 pad;
__u32 sdb_type;
__u32 sdb_offset;
__aligned_u64 sdb;
__aligned_u64 rdb;
__aligned_u64 cdb;
};
#endif

582
include/uapi/scsi/scsi_bsg_mpi3mr.h Normal file
View File

@ -0,0 +1,582 @@
/* SPDX-License-Identifier: GPL-2.0-or-later WITH Linux-syscall-note */
/*
* Driver for Broadcom MPI3 Storage Controllers
*
* Copyright (C) 2017-2022 Broadcom Inc.
* (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
*
*/
#ifndef SCSI_BSG_MPI3MR_H_INCLUDED
#define SCSI_BSG_MPI3MR_H_INCLUDED
#include <linux/types.h>
/* Definitions for BSG commands */
#define MPI3MR_IOCTL_VERSION 0x06
#define MPI3MR_APP_DEFAULT_TIMEOUT (60) /*seconds*/
#define MPI3MR_BSG_ADPTYPE_UNKNOWN 0
#define MPI3MR_BSG_ADPTYPE_AVGFAMILY 1
#define MPI3MR_BSG_ADPSTATE_UNKNOWN 0
#define MPI3MR_BSG_ADPSTATE_OPERATIONAL 1
#define MPI3MR_BSG_ADPSTATE_FAULT 2
#define MPI3MR_BSG_ADPSTATE_IN_RESET 3
#define MPI3MR_BSG_ADPSTATE_UNRECOVERABLE 4
#define MPI3MR_BSG_ADPRESET_UNKNOWN 0
#define MPI3MR_BSG_ADPRESET_SOFT 1
#define MPI3MR_BSG_ADPRESET_DIAG_FAULT 2
#define MPI3MR_BSG_LOGDATA_MAX_ENTRIES 400
#define MPI3MR_BSG_LOGDATA_ENTRY_HEADER_SZ 4
#define MPI3MR_DRVBSG_OPCODE_UNKNOWN 0
#define MPI3MR_DRVBSG_OPCODE_ADPINFO 1
#define MPI3MR_DRVBSG_OPCODE_ADPRESET 2
#define MPI3MR_DRVBSG_OPCODE_ALLTGTDEVINFO 4
#define MPI3MR_DRVBSG_OPCODE_GETCHGCNT 5
#define MPI3MR_DRVBSG_OPCODE_LOGDATAENABLE 6
#define MPI3MR_DRVBSG_OPCODE_PELENABLE 7
#define MPI3MR_DRVBSG_OPCODE_GETLOGDATA 8
#define MPI3MR_DRVBSG_OPCODE_QUERY_HDB 9
#define MPI3MR_DRVBSG_OPCODE_REPOST_HDB 10
#define MPI3MR_DRVBSG_OPCODE_UPLOAD_HDB 11
#define MPI3MR_DRVBSG_OPCODE_REFRESH_HDB_TRIGGERS 12
#define MPI3MR_BSG_BUFTYPE_UNKNOWN 0
#define MPI3MR_BSG_BUFTYPE_RAIDMGMT_CMD 1
#define MPI3MR_BSG_BUFTYPE_RAIDMGMT_RESP 2
#define MPI3MR_BSG_BUFTYPE_DATA_IN 3
#define MPI3MR_BSG_BUFTYPE_DATA_OUT 4
#define MPI3MR_BSG_BUFTYPE_MPI_REPLY 5
#define MPI3MR_BSG_BUFTYPE_ERR_RESPONSE 6
#define MPI3MR_BSG_BUFTYPE_MPI_REQUEST 0xFE
#define MPI3MR_BSG_MPI_REPLY_BUFTYPE_UNKNOWN 0
#define MPI3MR_BSG_MPI_REPLY_BUFTYPE_STATUS 1
#define MPI3MR_BSG_MPI_REPLY_BUFTYPE_ADDRESS 2
#define MPI3MR_HDB_BUFTYPE_UNKNOWN 0
#define MPI3MR_HDB_BUFTYPE_TRACE 1
#define MPI3MR_HDB_BUFTYPE_FIRMWARE 2
#define MPI3MR_HDB_BUFTYPE_RESERVED 3
#define MPI3MR_HDB_BUFSTATUS_UNKNOWN 0
#define MPI3MR_HDB_BUFSTATUS_NOT_ALLOCATED 1
#define MPI3MR_HDB_BUFSTATUS_POSTED_UNPAUSED 2
#define MPI3MR_HDB_BUFSTATUS_POSTED_PAUSED 3
#define MPI3MR_HDB_BUFSTATUS_RELEASED 4
#define MPI3MR_HDB_TRIGGER_TYPE_UNKNOWN 0
#define MPI3MR_HDB_TRIGGER_TYPE_DIAGFAULT 1
#define MPI3MR_HDB_TRIGGER_TYPE_ELEMENT 2
#define MPI3MR_HDB_TRIGGER_TYPE_MASTER 3
/* Supported BSG commands */
enum command {
MPI3MR_DRV_CMD = 1,
MPI3MR_MPT_CMD = 2,
};
/**
* struct mpi3_driver_info_layout - Information about driver
*
* @information_length: Length of this structure in bytes
* @driver_signature: Driver Vendor name
* @os_name: Operating System Name
* @driver_name: Driver name
* @driver_version: Driver version
* @driver_release_date: Driver release date
* @driver_capabilities: Driver capabilities
*/
struct mpi3_driver_info_layout {
__le32 information_length;
__u8 driver_signature[12];
__u8 os_name[16];
__u8 os_version[12];
__u8 driver_name[20];
__u8 driver_version[32];
__u8 driver_release_date[20];
__le32 driver_capabilities;
};
/**
* struct mpi3mr_bsg_in_adpinfo - Adapter information request
* data returned by the driver.
*
* @adp_type: Adapter type
* @rsvd1: Reserved
* @pci_dev_id: PCI device ID of the adapter
* @pci_dev_hw_rev: PCI revision of the adapter
* @pci_subsys_dev_id: PCI subsystem device ID of the adapter
* @pci_subsys_ven_id: PCI subsystem vendor ID of the adapter
* @pci_dev: PCI device
* @pci_func: PCI function
* @pci_bus: PCI bus
* @rsvd2: Reserved
* @pci_seg_id: PCI segment ID
* @app_intfc_ver: version of the application interface definition
* @rsvd3: Reserved
* @rsvd4: Reserved
* @rsvd5: Reserved
* @driver_info: Driver Information (Version/Name)
*/
struct mpi3mr_bsg_in_adpinfo {
__u32 adp_type;
__u32 rsvd1;
__u32 pci_dev_id;
__u32 pci_dev_hw_rev;
__u32 pci_subsys_dev_id;
__u32 pci_subsys_ven_id;
__u32 pci_dev:5;
__u32 pci_func:3;
__u32 pci_bus:8;
__u16 rsvd2;
__u32 pci_seg_id;
__u32 app_intfc_ver;
__u8 adp_state;
__u8 rsvd3;
__u16 rsvd4;
__u32 rsvd5[2];
struct mpi3_driver_info_layout driver_info;
};
/**
* struct mpi3mr_bsg_adp_reset - Adapter reset request
* payload data to the driver.
*
* @reset_type: Reset type
* @rsvd1: Reserved
* @rsvd2: Reserved
*/
struct mpi3mr_bsg_adp_reset {
__u8 reset_type;
__u8 rsvd1;
__u16 rsvd2;
};
/**
* struct mpi3mr_change_count - Topology change count
* returned by the driver.
*
* @change_count: Topology change count
* @rsvd: Reserved
*/
struct mpi3mr_change_count {
__u16 change_count;
__u16 rsvd;
};
/**
* struct mpi3mr_device_map_info - Target device mapping
* information
*
* @handle: Firmware device handle
* @perst_id: Persistent ID assigned by the firmware
* @target_id: Target ID assigned by the driver
* @bus_id: Bus ID assigned by the driver
* @rsvd1: Reserved
* @rsvd2: Reserved
*/
struct mpi3mr_device_map_info {
__u16 handle;
__u16 perst_id;
__u32 target_id;
__u8 bus_id;
__u8 rsvd1;
__u16 rsvd2;
};
/**
* struct mpi3mr_all_tgt_info - Target device mapping
* information returned by the driver
*
* @num_devices: The number of devices in driver's inventory
* @rsvd1: Reserved
* @rsvd2: Reserved
* @dmi: Variable length array of mapping information of targets
*/
struct mpi3mr_all_tgt_info {
__u16 num_devices;
__u16 rsvd1;
__u32 rsvd2;
struct mpi3mr_device_map_info dmi[1];
};
/**
* struct mpi3mr_logdata_enable - Number of log data
* entries saved by the driver returned as payload data for
* enable logdata BSG request by the driver.
*
* @max_entries: Number of log data entries cached by the driver
* @rsvd: Reserved
*/
struct mpi3mr_logdata_enable {
__u16 max_entries;
__u16 rsvd;
};
/**
* struct mpi3mr_bsg_out_pel_enable - PEL enable request payload
* data to the driver.
*
* @pel_locale: PEL locale to the firmware
* @pel_class: PEL class to the firmware
* @rsvd: Reserved
*/
struct mpi3mr_bsg_out_pel_enable {
__u16 pel_locale;
__u8 pel_class;
__u8 rsvd;
};
/**
* struct mpi3mr_logdata_entry - Log data entry cached by the
* driver.
*
* @valid_entry: Is the entry valid
* @rsvd1: Reserved
* @rsvd2: Reserved
* @data: Variable length Log entry data
*/
struct mpi3mr_logdata_entry {
__u8 valid_entry;
__u8 rsvd1;
__u16 rsvd2;
__u8 data[1]; /* Variable length Array */
};
/**
* struct mpi3mr_bsg_in_log_data - Log data entries saved by
* the driver returned as payload data for Get logdata request
* by the driver.
*
* @entry: Variable length Log data entry array
*/
struct mpi3mr_bsg_in_log_data {
struct mpi3mr_logdata_entry entry[1];
};
/**
* struct mpi3mr_hdb_entry - host diag buffer entry.
*
* @buf_type: Buffer type
* @status: Buffer status
* @trigger_type: Trigger type
* @rsvd1: Reserved
* @size: Buffer size
* @rsvd2: Reserved
* @trigger_data: Trigger specific data
* @rsvd3: Reserved
* @rsvd4: Reserved
*/
struct mpi3mr_hdb_entry {
__u8 buf_type;
__u8 status;
__u8 trigger_type;
__u8 rsvd1;
__u16 size;
__u16 rsvd2;
__u64 trigger_data;
__u32 rsvd3;
__u32 rsvd4;
};
/**
* struct mpi3mr_bsg_in_hdb_status - This structure contains
* return data for the BSG request to retrieve the number of host
* diagnostic buffers supported by the driver and their current
* status and additional status specific data if any in forms of
* multiple hdb entries.
*
* @num_hdb_types: Number of host diag buffer types supported
* @rsvd1: Reserved
* @rsvd2: Reserved
* @rsvd3: Reserved
* @entry: Variable length Diag buffer status entry array
*/
struct mpi3mr_bsg_in_hdb_status {
__u8 num_hdb_types;
__u8 rsvd1;
__u16 rsvd2;
__u32 rsvd3;
struct mpi3mr_hdb_entry entry[1];
};
/**
* struct mpi3mr_bsg_out_repost_hdb - Repost host diagnostic
* buffer request payload data to the driver.
*
* @buf_type: Buffer type
* @rsvd1: Reserved
* @rsvd2: Reserved
*/
struct mpi3mr_bsg_out_repost_hdb {
__u8 buf_type;
__u8 rsvd1;
__u16 rsvd2;
};
/**
* struct mpi3mr_bsg_out_upload_hdb - Upload host diagnostic
* buffer request payload data to the driver.
*
* @buf_type: Buffer type
* @rsvd1: Reserved
* @rsvd2: Reserved
* @start_offset: Start offset of the buffer from where to copy
* @length: Length of the buffer to copy
*/
struct mpi3mr_bsg_out_upload_hdb {
__u8 buf_type;
__u8 rsvd1;
__u16 rsvd2;
__u32 start_offset;
__u32 length;
};
/**
* struct mpi3mr_bsg_out_refresh_hdb_triggers - Refresh host
* diagnostic buffer triggers request payload data to the driver.
*
* @page_type: Page type
* @rsvd1: Reserved
* @rsvd2: Reserved
*/
struct mpi3mr_bsg_out_refresh_hdb_triggers {
__u8 page_type;
__u8 rsvd1;
__u16 rsvd2;
};
/**
* struct mpi3mr_bsg_drv_cmd - Generic bsg data
* structure for all driver specific requests.
*
* @mrioc_id: Controller ID
* @opcode: Driver specific opcode
* @rsvd1: Reserved
* @rsvd2: Reserved
*/
struct mpi3mr_bsg_drv_cmd {
__u8 mrioc_id;
__u8 opcode;
__u16 rsvd1;
__u32 rsvd2[4];
};
/**
* struct mpi3mr_bsg_in_reply_buf - MPI reply buffer returned
* for MPI Passthrough request .
*
* @mpi_reply_type: Type of MPI reply
* @rsvd1: Reserved
* @rsvd2: Reserved
* @reply_buf: Variable Length buffer based on mpirep type
*/
struct mpi3mr_bsg_in_reply_buf {
__u8 mpi_reply_type;
__u8 rsvd1;
__u16 rsvd2;
__u8 reply_buf[1];
};
/**
* struct mpi3mr_buf_entry - User buffer descriptor for MPI
* Passthrough requests.
*
* @buf_type: Buffer type
* @rsvd1: Reserved
* @rsvd2: Reserved
* @buf_len: Buffer length
*/
struct mpi3mr_buf_entry {
__u8 buf_type;
__u8 rsvd1;
__u16 rsvd2;
__u32 buf_len;
};
/**
* struct mpi3mr_bsg_buf_entry_list - list of user buffer
* descriptor for MPI Passthrough requests.
*
* @num_of_entries: Number of buffer descriptors
* @rsvd1: Reserved
* @rsvd2: Reserved
* @rsvd3: Reserved
* @buf_entry: Variable length array of buffer descriptors
*/
struct mpi3mr_buf_entry_list {
__u8 num_of_entries;
__u8 rsvd1;
__u16 rsvd2;
__u32 rsvd3;
struct mpi3mr_buf_entry buf_entry[1];
};
/**
* struct mpi3mr_bsg_mptcmd - Generic bsg data
* structure for all MPI Passthrough requests .
*
* @mrioc_id: Controller ID
* @rsvd1: Reserved
* @timeout: MPI request timeout
* @buf_entry_list: Buffer descriptor list
*/
struct mpi3mr_bsg_mptcmd {
__u8 mrioc_id;
__u8 rsvd1;
__u16 timeout;
__u32 rsvd2;
struct mpi3mr_buf_entry_list buf_entry_list;
};
/**
* struct mpi3mr_bsg_packet - Generic bsg data
* structure for all supported requests .
*
* @cmd_type: represents drvrcmd or mptcmd
* @rsvd1: Reserved
* @rsvd2: Reserved
* @drvrcmd: driver request structure
* @mptcmd: mpt request structure
*/
struct mpi3mr_bsg_packet {
__u8 cmd_type;
__u8 rsvd1;
__u16 rsvd2;
__u32 rsvd3;
union {
struct mpi3mr_bsg_drv_cmd drvrcmd;
struct mpi3mr_bsg_mptcmd mptcmd;
} cmd;
};
/* MPI3: NVMe Encasulation related definitions */
#ifndef MPI3_NVME_ENCAP_CMD_MAX
#define MPI3_NVME_ENCAP_CMD_MAX (1)
#endif
struct mpi3_nvme_encapsulated_request {
__le16 host_tag;
__u8 ioc_use_only02;
__u8 function;
__le16 ioc_use_only04;
__u8 ioc_use_only06;
__u8 msg_flags;
__le16 change_count;
__le16 dev_handle;
__le16 encapsulated_command_length;
__le16 flags;
__le32 data_length;
__le32 reserved14[3];
__le32 command[MPI3_NVME_ENCAP_CMD_MAX];
};
struct mpi3_nvme_encapsulated_error_reply {
__le16 host_tag;
__u8 ioc_use_only02;
__u8 function;
__le16 ioc_use_only04;
__u8 ioc_use_only06;
__u8 msg_flags;
__le16 ioc_use_only08;
__le16 ioc_status;
__le32 ioc_log_info;
__le32 nvme_completion_entry[4];
};
#define MPI3MR_NVME_PRP_SIZE 8 /* PRP size */
#define MPI3MR_NVME_CMD_PRP1_OFFSET 24 /* PRP1 offset in NVMe cmd */
#define MPI3MR_NVME_CMD_PRP2_OFFSET 32 /* PRP2 offset in NVMe cmd */
#define MPI3MR_NVME_CMD_SGL_OFFSET 24 /* SGL offset in NVMe cmd */
#define MPI3MR_NVME_DATA_FORMAT_PRP 0
#define MPI3MR_NVME_DATA_FORMAT_SGL1 1
#define MPI3MR_NVME_DATA_FORMAT_SGL2 2
/* MPI3: task management related definitions */
struct mpi3_scsi_task_mgmt_request {
__le16 host_tag;
__u8 ioc_use_only02;
__u8 function;
__le16 ioc_use_only04;
__u8 ioc_use_only06;
__u8 msg_flags;
__le16 change_count;
__le16 dev_handle;
__le16 task_host_tag;
__u8 task_type;
__u8 reserved0f;
__le16 task_request_queue_id;
__le16 reserved12;
__le32 reserved14;
__u8 lun[8];
};
#define MPI3_SCSITASKMGMT_MSGFLAGS_DO_NOT_SEND_TASK_IU (0x08)
#define MPI3_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01)
#define MPI3_SCSITASKMGMT_TASKTYPE_ABORT_TASK_SET (0x02)
#define MPI3_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03)
#define MPI3_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05)
#define MPI3_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06)
#define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07)
#define MPI3_SCSITASKMGMT_TASKTYPE_CLEAR_ACA (0x08)
#define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_TASK_SET (0x09)
#define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_ASYNC_EVENT (0x0a)
#define MPI3_SCSITASKMGMT_TASKTYPE_I_T_NEXUS_RESET (0x0b)
struct mpi3_scsi_task_mgmt_reply {
__le16 host_tag;
__u8 ioc_use_only02;
__u8 function;
__le16 ioc_use_only04;
__u8 ioc_use_only06;
__u8 msg_flags;
__le16 ioc_use_only08;
__le16 ioc_status;
__le32 ioc_log_info;
__le32 termination_count;
__le32 response_data;
__le32 reserved18;
};
#define MPI3_SCSITASKMGMT_RSPCODE_TM_COMPLETE (0x00)
#define MPI3_SCSITASKMGMT_RSPCODE_INVALID_FRAME (0x02)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_FUNCTION_NOT_SUPPORTED (0x04)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_FAILED (0x05)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_SUCCEEDED (0x08)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_INVALID_LUN (0x09)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_OVERLAPPED_TAG (0x0a)
#define MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC (0x80)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_NVME_DENIED (0x81)
/* MPI3: PEL related definitions */
#define MPI3_PEL_LOCALE_FLAGS_NON_BLOCKING_BOOT_EVENT (0x0200)
#define MPI3_PEL_LOCALE_FLAGS_BLOCKING_BOOT_EVENT (0x0100)
#define MPI3_PEL_LOCALE_FLAGS_PCIE (0x0080)
#define MPI3_PEL_LOCALE_FLAGS_CONFIGURATION (0x0040)
#define MPI3_PEL_LOCALE_FLAGS_CONTROLER (0x0020)
#define MPI3_PEL_LOCALE_FLAGS_SAS (0x0010)
#define MPI3_PEL_LOCALE_FLAGS_EPACK (0x0008)
#define MPI3_PEL_LOCALE_FLAGS_ENCLOSURE (0x0004)
#define MPI3_PEL_LOCALE_FLAGS_PD (0x0002)
#define MPI3_PEL_LOCALE_FLAGS_VD (0x0001)
#define MPI3_PEL_CLASS_DEBUG (0x00)
#define MPI3_PEL_CLASS_PROGRESS (0x01)
#define MPI3_PEL_CLASS_INFORMATIONAL (0x02)
#define MPI3_PEL_CLASS_WARNING (0x03)
#define MPI3_PEL_CLASS_CRITICAL (0x04)
#define MPI3_PEL_CLASS_FATAL (0x05)
#define MPI3_PEL_CLASS_FAULT (0x06)
/* MPI3: Function definitions */
#define MPI3_BSG_FUNCTION_MGMT_PASSTHROUGH (0x0a)
#define MPI3_BSG_FUNCTION_SCSI_IO (0x20)
#define MPI3_BSG_FUNCTION_SCSI_TASK_MGMT (0x21)
#define MPI3_BSG_FUNCTION_SMP_PASSTHROUGH (0x22)
#define MPI3_BSG_FUNCTION_NVME_ENCAPSULATED (0x24)
#endif

126
include/uapi/sound/intel/avs/tokens.h Normal file
View File

@ -0,0 +1,126 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
* Copyright(c) 2021 Intel Corporation. All rights reserved.
*
* Authors: Cezary Rojewski <cezary.rojewski@intel.com>
* Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
*/
#ifndef __UAPI_SOUND_INTEL_AVS_TOKENS_H
#define __UAPI_SOUND_INTEL_AVS_TOKENS_H
enum avs_tplg_token {
/* struct avs_tplg */
AVS_TKN_MANIFEST_NAME_STRING = 1,
AVS_TKN_MANIFEST_VERSION_U32 = 2,
AVS_TKN_MANIFEST_NUM_LIBRARIES_U32 = 3,
AVS_TKN_MANIFEST_NUM_AFMTS_U32 = 4,
AVS_TKN_MANIFEST_NUM_MODCFGS_BASE_U32 = 5,
AVS_TKN_MANIFEST_NUM_MODCFGS_EXT_U32 = 6,
AVS_TKN_MANIFEST_NUM_PPLCFGS_U32 = 7,
AVS_TKN_MANIFEST_NUM_BINDINGS_U32 = 8,
/* struct avs_tplg_library */
AVS_TKN_LIBRARY_ID_U32 = 101,
AVS_TKN_LIBRARY_NAME_STRING = 102,
/* struct avs_audio_format */
AVS_TKN_AFMT_ID_U32 = 201,
AVS_TKN_AFMT_SAMPLE_RATE_U32 = 202,
AVS_TKN_AFMT_BIT_DEPTH_U32 = 203,
AVS_TKN_AFMT_CHANNEL_MAP_U32 = 204,
AVS_TKN_AFMT_CHANNEL_CFG_U32 = 205,
AVS_TKN_AFMT_INTERLEAVING_U32 = 206,
AVS_TKN_AFMT_NUM_CHANNELS_U32 = 207,
AVS_TKN_AFMT_VALID_BIT_DEPTH_U32 = 208,
AVS_TKN_AFMT_SAMPLE_TYPE_U32 = 209,
/* struct avs_tplg_modcfg_base */
AVS_TKN_MODCFG_BASE_ID_U32 = 301,
AVS_TKN_MODCFG_BASE_CPC_U32 = 302,
AVS_TKN_MODCFG_BASE_IBS_U32 = 303,
AVS_TKN_MODCFG_BASE_OBS_U32 = 304,
AVS_TKN_MODCFG_BASE_PAGES_U32 = 305,
/* struct avs_tplg_modcfg_ext */
AVS_TKN_MODCFG_EXT_ID_U32 = 401,
AVS_TKN_MODCFG_EXT_TYPE_UUID = 402,
AVS_TKN_MODCFG_CPR_OUT_AFMT_ID_U32 = 403,
AVS_TKN_MODCFG_CPR_FEATURE_MASK_U32 = 404,
AVS_TKN_MODCFG_CPR_DMA_TYPE_U32 = 405,
AVS_TKN_MODCFG_CPR_DMABUFF_SIZE_U32 = 406,
AVS_TKN_MODCFG_CPR_VINDEX_U8 = 407,
AVS_TKN_MODCFG_CPR_BLOB_FMT_ID_U32 = 408,
AVS_TKN_MODCFG_MICSEL_OUT_AFMT_ID_U32 = 409,
AVS_TKN_MODCFG_INTELWOV_CPC_LP_MODE_U32 = 410,
AVS_TKN_MODCFG_SRC_OUT_FREQ_U32 = 411,
AVS_TKN_MODCFG_MUX_REF_AFMT_ID_U32 = 412,
AVS_TKN_MODCFG_MUX_OUT_AFMT_ID_U32 = 413,
AVS_TKN_MODCFG_AEC_REF_AFMT_ID_U32 = 414,
AVS_TKN_MODCFG_AEC_OUT_AFMT_ID_U32 = 415,
AVS_TKN_MODCFG_AEC_CPC_LP_MODE_U32 = 416,
AVS_TKN_MODCFG_ASRC_OUT_FREQ_U32 = 417,
AVS_TKN_MODCFG_ASRC_MODE_U8 = 418,
AVS_TKN_MODCFG_ASRC_DISABLE_JITTER_U8 = 419,
AVS_TKN_MODCFG_UPDOWN_MIX_OUT_CHAN_CFG_U32 = 420,
AVS_TKN_MODCFG_UPDOWN_MIX_COEFF_SELECT_U32 = 421,
AVS_TKN_MODCFG_UPDOWN_MIX_COEFF_0_S32 = 422,
AVS_TKN_MODCFG_UPDOWN_MIX_COEFF_1_S32 = 423,
AVS_TKN_MODCFG_UPDOWN_MIX_COEFF_2_S32 = 424,
AVS_TKN_MODCFG_UPDOWN_MIX_COEFF_3_S32 = 425,
AVS_TKN_MODCFG_UPDOWN_MIX_COEFF_4_S32 = 426,
AVS_TKN_MODCFG_UPDOWN_MIX_COEFF_5_S32 = 427,
AVS_TKN_MODCFG_UPDOWN_MIX_COEFF_6_S32 = 428,
AVS_TKN_MODCFG_UPDOWN_MIX_COEFF_7_S32 = 429,
AVS_TKN_MODCFG_UPDOWN_MIX_CHAN_MAP_U32 = 430,
AVS_TKN_MODCFG_EXT_NUM_INPUT_PINS_U16 = 431,
AVS_TKN_MODCFG_EXT_NUM_OUTPUT_PINS_U16 = 432,
/* struct avs_tplg_pplcfg */
AVS_TKN_PPLCFG_ID_U32 = 1401,
AVS_TKN_PPLCFG_REQ_SIZE_U16 = 1402,
AVS_TKN_PPLCFG_PRIORITY_U8 = 1403,
AVS_TKN_PPLCFG_LOW_POWER_BOOL = 1404,
AVS_TKN_PPLCFG_ATTRIBUTES_U16 = 1405,
AVS_TKN_PPLCFG_TRIGGER_U32 = 1406,
/* struct avs_tplg_binding */
AVS_TKN_BINDING_ID_U32 = 1501,
AVS_TKN_BINDING_TARGET_TPLG_NAME_STRING = 1502,
AVS_TKN_BINDING_TARGET_PATH_TMPL_ID_U32 = 1503,
AVS_TKN_BINDING_TARGET_PPL_ID_U32 = 1504,
AVS_TKN_BINDING_TARGET_MOD_ID_U32 = 1505,
AVS_TKN_BINDING_TARGET_MOD_PIN_U8 = 1506,
AVS_TKN_BINDING_MOD_ID_U32 = 1507,
AVS_TKN_BINDING_MOD_PIN_U8 = 1508,
AVS_TKN_BINDING_IS_SINK_U8 = 1509,
/* struct avs_tplg_pipeline */
AVS_TKN_PPL_ID_U32 = 1601,
AVS_TKN_PPL_PPLCFG_ID_U32 = 1602,
AVS_TKN_PPL_NUM_BINDING_IDS_U32 = 1603,
AVS_TKN_PPL_BINDING_ID_U32 = 1604,
/* struct avs_tplg_module */
AVS_TKN_MOD_ID_U32 = 1701,
AVS_TKN_MOD_MODCFG_BASE_ID_U32 = 1702,
AVS_TKN_MOD_IN_AFMT_ID_U32 = 1703,
AVS_TKN_MOD_CORE_ID_U8 = 1704,
AVS_TKN_MOD_PROC_DOMAIN_U8 = 1705,
AVS_TKN_MOD_MODCFG_EXT_ID_U32 = 1706,
/* struct avs_tplg_path_template */
AVS_TKN_PATH_TMPL_ID_U32 = 1801,
/* struct avs_tplg_path */
AVS_TKN_PATH_ID_U32 = 1901,
AVS_TKN_PATH_FE_FMT_ID_U32 = 1902,
AVS_TKN_PATH_BE_FMT_ID_U32 = 1903,
/* struct avs_tplg_pin_format */
AVS_TKN_PIN_FMT_INDEX_U32 = 2201,
AVS_TKN_PIN_FMT_IOBS_U32 = 2202,
AVS_TKN_PIN_FMT_AFMT_ID_U32 = 2203,
};
#endif

623
include/ufs/ufs.h Normal file
View File

@ -0,0 +1,623 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Universal Flash Storage Host controller driver
* Copyright (C) 2011-2013 Samsung India Software Operations
*
* Authors:
* Santosh Yaraganavi <santosh.sy@samsung.com>
* Vinayak Holikatti <h.vinayak@samsung.com>
*/
#ifndef _UFS_H
#define _UFS_H
#include <linux/mutex.h>
#include <linux/types.h>
#include <uapi/scsi/scsi_bsg_ufs.h>
#define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req))
#define QUERY_DESC_MAX_SIZE 255
#define QUERY_DESC_MIN_SIZE 2
#define QUERY_DESC_HDR_SIZE 2
#define QUERY_OSF_SIZE (GENERAL_UPIU_REQUEST_SIZE - \
(sizeof(struct utp_upiu_header)))
#define UFS_SENSE_SIZE 18
#define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\
cpu_to_be32((byte3 << 24) | (byte2 << 16) |\
(byte1 << 8) | (byte0))
/*
* UFS device may have standard LUs and LUN id could be from 0x00 to
* 0x7F. Standard LUs use "Peripheral Device Addressing Format".
* UFS device may also have the Well Known LUs (also referred as W-LU)
* which again could be from 0x00 to 0x7F. For W-LUs, device only use
* the "Extended Addressing Format" which means the W-LUNs would be
* from 0xc100 (SCSI_W_LUN_BASE) onwards.
* This means max. LUN number reported from UFS device could be 0xC17F.
*/
#define UFS_UPIU_MAX_UNIT_NUM_ID 0x7F
#define UFS_MAX_LUNS (SCSI_W_LUN_BASE + UFS_UPIU_MAX_UNIT_NUM_ID)
#define UFS_UPIU_WLUN_ID (1 << 7)
#define UFS_RPMB_UNIT 0xC4
/* WriteBooster buffer is available only for the logical unit from 0 to 7 */
#define UFS_UPIU_MAX_WB_LUN_ID 8
/*
* WriteBooster buffer lifetime has a limit setted by vendor.
* If it is over the limit, WriteBooster feature will be disabled.
*/
#define UFS_WB_EXCEED_LIFETIME 0x0B
/* Well known logical unit id in LUN field of UPIU */
enum {
UFS_UPIU_REPORT_LUNS_WLUN = 0x81,
UFS_UPIU_UFS_DEVICE_WLUN = 0xD0,
UFS_UPIU_BOOT_WLUN = 0xB0,
UFS_UPIU_RPMB_WLUN = 0xC4,
};
/*
* UFS Protocol Information Unit related definitions
*/
/* Task management functions */
enum {
UFS_ABORT_TASK = 0x01,
UFS_ABORT_TASK_SET = 0x02,
UFS_CLEAR_TASK_SET = 0x04,
UFS_LOGICAL_RESET = 0x08,
UFS_QUERY_TASK = 0x80,
UFS_QUERY_TASK_SET = 0x81,
};
/* UTP UPIU Transaction Codes Initiator to Target */
enum {
UPIU_TRANSACTION_NOP_OUT = 0x00,
UPIU_TRANSACTION_COMMAND = 0x01,
UPIU_TRANSACTION_DATA_OUT = 0x02,
UPIU_TRANSACTION_TASK_REQ = 0x04,
UPIU_TRANSACTION_QUERY_REQ = 0x16,
};
/* UTP UPIU Transaction Codes Target to Initiator */
enum {
UPIU_TRANSACTION_NOP_IN = 0x20,
UPIU_TRANSACTION_RESPONSE = 0x21,
UPIU_TRANSACTION_DATA_IN = 0x22,
UPIU_TRANSACTION_TASK_RSP = 0x24,
UPIU_TRANSACTION_READY_XFER = 0x31,
UPIU_TRANSACTION_QUERY_RSP = 0x36,
UPIU_TRANSACTION_REJECT_UPIU = 0x3F,
};
/* UPIU Read/Write flags */
enum {
UPIU_CMD_FLAGS_NONE = 0x00,
UPIU_CMD_FLAGS_WRITE = 0x20,
UPIU_CMD_FLAGS_READ = 0x40,
};
/* UPIU Task Attributes */
enum {
UPIU_TASK_ATTR_SIMPLE = 0x00,
UPIU_TASK_ATTR_ORDERED = 0x01,
UPIU_TASK_ATTR_HEADQ = 0x02,
UPIU_TASK_ATTR_ACA = 0x03,
};
/* UPIU Query request function */
enum {
UPIU_QUERY_FUNC_STANDARD_READ_REQUEST = 0x01,
UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST = 0x81,
};
/* Flag idn for Query Requests*/
enum flag_idn {
QUERY_FLAG_IDN_FDEVICEINIT = 0x01,
QUERY_FLAG_IDN_PERMANENT_WPE = 0x02,
QUERY_FLAG_IDN_PWR_ON_WPE = 0x03,
QUERY_FLAG_IDN_BKOPS_EN = 0x04,
QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE = 0x05,
QUERY_FLAG_IDN_PURGE_ENABLE = 0x06,
QUERY_FLAG_IDN_RESERVED2 = 0x07,
QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 0x08,
QUERY_FLAG_IDN_BUSY_RTC = 0x09,
QUERY_FLAG_IDN_RESERVED3 = 0x0A,
QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE = 0x0B,
QUERY_FLAG_IDN_WB_EN = 0x0E,
QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN = 0x0F,
QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8 = 0x10,
QUERY_FLAG_IDN_HPB_RESET = 0x11,
QUERY_FLAG_IDN_HPB_EN = 0x12,
};
/* Attribute idn for Query requests */
enum attr_idn {
QUERY_ATTR_IDN_BOOT_LU_EN = 0x00,
QUERY_ATTR_IDN_MAX_HPB_SINGLE_CMD = 0x01,
QUERY_ATTR_IDN_POWER_MODE = 0x02,
QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03,
QUERY_ATTR_IDN_OOO_DATA_EN = 0x04,
QUERY_ATTR_IDN_BKOPS_STATUS = 0x05,
QUERY_ATTR_IDN_PURGE_STATUS = 0x06,
QUERY_ATTR_IDN_MAX_DATA_IN = 0x07,
QUERY_ATTR_IDN_MAX_DATA_OUT = 0x08,
QUERY_ATTR_IDN_DYN_CAP_NEEDED = 0x09,
QUERY_ATTR_IDN_REF_CLK_FREQ = 0x0A,
QUERY_ATTR_IDN_CONF_DESC_LOCK = 0x0B,
QUERY_ATTR_IDN_MAX_NUM_OF_RTT = 0x0C,
QUERY_ATTR_IDN_EE_CONTROL = 0x0D,
QUERY_ATTR_IDN_EE_STATUS = 0x0E,
QUERY_ATTR_IDN_SECONDS_PASSED = 0x0F,
QUERY_ATTR_IDN_CNTX_CONF = 0x10,
QUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 0x11,
QUERY_ATTR_IDN_RESERVED2 = 0x12,
QUERY_ATTR_IDN_RESERVED3 = 0x13,
QUERY_ATTR_IDN_FFU_STATUS = 0x14,
QUERY_ATTR_IDN_PSA_STATE = 0x15,
QUERY_ATTR_IDN_PSA_DATA_SIZE = 0x16,
QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME = 0x17,
QUERY_ATTR_IDN_CASE_ROUGH_TEMP = 0x18,
QUERY_ATTR_IDN_HIGH_TEMP_BOUND = 0x19,
QUERY_ATTR_IDN_LOW_TEMP_BOUND = 0x1A,
QUERY_ATTR_IDN_WB_FLUSH_STATUS = 0x1C,
QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE = 0x1D,
QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST = 0x1E,
QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE = 0x1F,
};
/* Descriptor idn for Query requests */
enum desc_idn {
QUERY_DESC_IDN_DEVICE = 0x0,
QUERY_DESC_IDN_CONFIGURATION = 0x1,
QUERY_DESC_IDN_UNIT = 0x2,
QUERY_DESC_IDN_RFU_0 = 0x3,
QUERY_DESC_IDN_INTERCONNECT = 0x4,
QUERY_DESC_IDN_STRING = 0x5,
QUERY_DESC_IDN_RFU_1 = 0x6,
QUERY_DESC_IDN_GEOMETRY = 0x7,
QUERY_DESC_IDN_POWER = 0x8,
QUERY_DESC_IDN_HEALTH = 0x9,
QUERY_DESC_IDN_MAX,
};
enum desc_header_offset {
QUERY_DESC_LENGTH_OFFSET = 0x00,
QUERY_DESC_DESC_TYPE_OFFSET = 0x01,
};
/* Unit descriptor parameters offsets in bytes*/
enum unit_desc_param {
UNIT_DESC_PARAM_LEN = 0x0,
UNIT_DESC_PARAM_TYPE = 0x1,
UNIT_DESC_PARAM_UNIT_INDEX = 0x2,
UNIT_DESC_PARAM_LU_ENABLE = 0x3,
UNIT_DESC_PARAM_BOOT_LUN_ID = 0x4,
UNIT_DESC_PARAM_LU_WR_PROTECT = 0x5,
UNIT_DESC_PARAM_LU_Q_DEPTH = 0x6,
UNIT_DESC_PARAM_PSA_SENSITIVE = 0x7,
UNIT_DESC_PARAM_MEM_TYPE = 0x8,
UNIT_DESC_PARAM_DATA_RELIABILITY = 0x9,
UNIT_DESC_PARAM_LOGICAL_BLK_SIZE = 0xA,
UNIT_DESC_PARAM_LOGICAL_BLK_COUNT = 0xB,
UNIT_DESC_PARAM_ERASE_BLK_SIZE = 0x13,
UNIT_DESC_PARAM_PROVISIONING_TYPE = 0x17,
UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT = 0x18,
UNIT_DESC_PARAM_CTX_CAPABILITIES = 0x20,
UNIT_DESC_PARAM_LARGE_UNIT_SIZE_M1 = 0x22,
UNIT_DESC_PARAM_HPB_LU_MAX_ACTIVE_RGNS = 0x23,
UNIT_DESC_PARAM_HPB_PIN_RGN_START_OFF = 0x25,
UNIT_DESC_PARAM_HPB_NUM_PIN_RGNS = 0x27,
UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS = 0x29,
};
/* Device descriptor parameters offsets in bytes*/
enum device_desc_param {
DEVICE_DESC_PARAM_LEN = 0x0,
DEVICE_DESC_PARAM_TYPE = 0x1,
DEVICE_DESC_PARAM_DEVICE_TYPE = 0x2,
DEVICE_DESC_PARAM_DEVICE_CLASS = 0x3,
DEVICE_DESC_PARAM_DEVICE_SUB_CLASS = 0x4,
DEVICE_DESC_PARAM_PRTCL = 0x5,
DEVICE_DESC_PARAM_NUM_LU = 0x6,
DEVICE_DESC_PARAM_NUM_WLU = 0x7,
DEVICE_DESC_PARAM_BOOT_ENBL = 0x8,
DEVICE_DESC_PARAM_DESC_ACCSS_ENBL = 0x9,
DEVICE_DESC_PARAM_INIT_PWR_MODE = 0xA,
DEVICE_DESC_PARAM_HIGH_PR_LUN = 0xB,
DEVICE_DESC_PARAM_SEC_RMV_TYPE = 0xC,
DEVICE_DESC_PARAM_SEC_LU = 0xD,
DEVICE_DESC_PARAM_BKOP_TERM_LT = 0xE,
DEVICE_DESC_PARAM_ACTVE_ICC_LVL = 0xF,
DEVICE_DESC_PARAM_SPEC_VER = 0x10,
DEVICE_DESC_PARAM_MANF_DATE = 0x12,
DEVICE_DESC_PARAM_MANF_NAME = 0x14,
DEVICE_DESC_PARAM_PRDCT_NAME = 0x15,
DEVICE_DESC_PARAM_SN = 0x16,
DEVICE_DESC_PARAM_OEM_ID = 0x17,
DEVICE_DESC_PARAM_MANF_ID = 0x18,
DEVICE_DESC_PARAM_UD_OFFSET = 0x1A,
DEVICE_DESC_PARAM_UD_LEN = 0x1B,
DEVICE_DESC_PARAM_RTT_CAP = 0x1C,
DEVICE_DESC_PARAM_FRQ_RTC = 0x1D,
DEVICE_DESC_PARAM_UFS_FEAT = 0x1F,
DEVICE_DESC_PARAM_FFU_TMT = 0x20,
DEVICE_DESC_PARAM_Q_DPTH = 0x21,
DEVICE_DESC_PARAM_DEV_VER = 0x22,
DEVICE_DESC_PARAM_NUM_SEC_WPA = 0x24,
DEVICE_DESC_PARAM_PSA_MAX_DATA = 0x25,
DEVICE_DESC_PARAM_PSA_TMT = 0x29,
DEVICE_DESC_PARAM_PRDCT_REV = 0x2A,
DEVICE_DESC_PARAM_HPB_VER = 0x40,
DEVICE_DESC_PARAM_HPB_CONTROL = 0x42,
DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP = 0x4F,
DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN = 0x53,
DEVICE_DESC_PARAM_WB_TYPE = 0x54,
DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS = 0x55,
};
/* Interconnect descriptor parameters offsets in bytes*/
enum interconnect_desc_param {
INTERCONNECT_DESC_PARAM_LEN = 0x0,
INTERCONNECT_DESC_PARAM_TYPE = 0x1,
INTERCONNECT_DESC_PARAM_UNIPRO_VER = 0x2,
INTERCONNECT_DESC_PARAM_MPHY_VER = 0x4,
};
/* Geometry descriptor parameters offsets in bytes*/
enum geometry_desc_param {
GEOMETRY_DESC_PARAM_LEN = 0x0,
GEOMETRY_DESC_PARAM_TYPE = 0x1,
GEOMETRY_DESC_PARAM_DEV_CAP = 0x4,
GEOMETRY_DESC_PARAM_MAX_NUM_LUN = 0xC,
GEOMETRY_DESC_PARAM_SEG_SIZE = 0xD,
GEOMETRY_DESC_PARAM_ALLOC_UNIT_SIZE = 0x11,
GEOMETRY_DESC_PARAM_MIN_BLK_SIZE = 0x12,
GEOMETRY_DESC_PARAM_OPT_RD_BLK_SIZE = 0x13,
GEOMETRY_DESC_PARAM_OPT_WR_BLK_SIZE = 0x14,
GEOMETRY_DESC_PARAM_MAX_IN_BUF_SIZE = 0x15,
GEOMETRY_DESC_PARAM_MAX_OUT_BUF_SIZE = 0x16,
GEOMETRY_DESC_PARAM_RPMB_RW_SIZE = 0x17,
GEOMETRY_DESC_PARAM_DYN_CAP_RSRC_PLC = 0x18,
GEOMETRY_DESC_PARAM_DATA_ORDER = 0x19,
GEOMETRY_DESC_PARAM_MAX_NUM_CTX = 0x1A,
GEOMETRY_DESC_PARAM_TAG_UNIT_SIZE = 0x1B,
GEOMETRY_DESC_PARAM_TAG_RSRC_SIZE = 0x1C,
GEOMETRY_DESC_PARAM_SEC_RM_TYPES = 0x1D,
GEOMETRY_DESC_PARAM_MEM_TYPES = 0x1E,
GEOMETRY_DESC_PARAM_SCM_MAX_NUM_UNITS = 0x20,
GEOMETRY_DESC_PARAM_SCM_CAP_ADJ_FCTR = 0x24,
GEOMETRY_DESC_PARAM_NPM_MAX_NUM_UNITS = 0x26,
GEOMETRY_DESC_PARAM_NPM_CAP_ADJ_FCTR = 0x2A,
GEOMETRY_DESC_PARAM_ENM1_MAX_NUM_UNITS = 0x2C,
GEOMETRY_DESC_PARAM_ENM1_CAP_ADJ_FCTR = 0x30,
GEOMETRY_DESC_PARAM_ENM2_MAX_NUM_UNITS = 0x32,
GEOMETRY_DESC_PARAM_ENM2_CAP_ADJ_FCTR = 0x36,
GEOMETRY_DESC_PARAM_ENM3_MAX_NUM_UNITS = 0x38,
GEOMETRY_DESC_PARAM_ENM3_CAP_ADJ_FCTR = 0x3C,
GEOMETRY_DESC_PARAM_ENM4_MAX_NUM_UNITS = 0x3E,
GEOMETRY_DESC_PARAM_ENM4_CAP_ADJ_FCTR = 0x42,
GEOMETRY_DESC_PARAM_OPT_LOG_BLK_SIZE = 0x44,
GEOMETRY_DESC_PARAM_HPB_REGION_SIZE = 0x48,
GEOMETRY_DESC_PARAM_HPB_NUMBER_LU = 0x49,
GEOMETRY_DESC_PARAM_HPB_SUBREGION_SIZE = 0x4A,
GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS = 0x4B,
GEOMETRY_DESC_PARAM_WB_MAX_ALLOC_UNITS = 0x4F,
GEOMETRY_DESC_PARAM_WB_MAX_WB_LUNS = 0x53,
GEOMETRY_DESC_PARAM_WB_BUFF_CAP_ADJ = 0x54,
GEOMETRY_DESC_PARAM_WB_SUP_RED_TYPE = 0x55,
GEOMETRY_DESC_PARAM_WB_SUP_WB_TYPE = 0x56,
};
/* Health descriptor parameters offsets in bytes*/
enum health_desc_param {
HEALTH_DESC_PARAM_LEN = 0x0,
HEALTH_DESC_PARAM_TYPE = 0x1,
HEALTH_DESC_PARAM_EOL_INFO = 0x2,
HEALTH_DESC_PARAM_LIFE_TIME_EST_A = 0x3,
HEALTH_DESC_PARAM_LIFE_TIME_EST_B = 0x4,
};
/* WriteBooster buffer mode */
enum {
WB_BUF_MODE_LU_DEDICATED = 0x0,
WB_BUF_MODE_SHARED = 0x1,
};
/*
* Logical Unit Write Protect
* 00h: LU not write protected
* 01h: LU write protected when fPowerOnWPEn =1
* 02h: LU permanently write protected when fPermanentWPEn =1
*/
enum ufs_lu_wp_type {
UFS_LU_NO_WP = 0x00,
UFS_LU_POWER_ON_WP = 0x01,
UFS_LU_PERM_WP = 0x02,
};
/* bActiveICCLevel parameter current units */
enum {
UFSHCD_NANO_AMP = 0,
UFSHCD_MICRO_AMP = 1,
UFSHCD_MILI_AMP = 2,
UFSHCD_AMP = 3,
};
/* Possible values for dExtendedUFSFeaturesSupport */
enum {
UFS_DEV_LOW_TEMP_NOTIF = BIT(4),
UFS_DEV_HIGH_TEMP_NOTIF = BIT(5),
UFS_DEV_EXT_TEMP_NOTIF = BIT(6),
UFS_DEV_HPB_SUPPORT = BIT(7),
UFS_DEV_WRITE_BOOSTER_SUP = BIT(8),
};
#define UFS_DEV_HPB_SUPPORT_VERSION 0x310
#define POWER_DESC_MAX_ACTV_ICC_LVLS 16
/* Attribute bActiveICCLevel parameter bit masks definitions */
#define ATTR_ICC_LVL_UNIT_OFFSET 14
#define ATTR_ICC_LVL_UNIT_MASK (0x3 << ATTR_ICC_LVL_UNIT_OFFSET)
#define ATTR_ICC_LVL_VALUE_MASK 0x3FF
/* Power descriptor parameters offsets in bytes */
enum power_desc_param_offset {
PWR_DESC_LEN = 0x0,
PWR_DESC_TYPE = 0x1,
PWR_DESC_ACTIVE_LVLS_VCC_0 = 0x2,
PWR_DESC_ACTIVE_LVLS_VCCQ_0 = 0x22,
PWR_DESC_ACTIVE_LVLS_VCCQ2_0 = 0x42,
};
/* Exception event mask values */
enum {
MASK_EE_STATUS = 0xFFFF,
MASK_EE_DYNCAP_EVENT = BIT(0),
MASK_EE_SYSPOOL_EVENT = BIT(1),
MASK_EE_URGENT_BKOPS = BIT(2),
MASK_EE_TOO_HIGH_TEMP = BIT(3),
MASK_EE_TOO_LOW_TEMP = BIT(4),
MASK_EE_WRITEBOOSTER_EVENT = BIT(5),
MASK_EE_PERFORMANCE_THROTTLING = BIT(6),
};
#define MASK_EE_URGENT_TEMP (MASK_EE_TOO_HIGH_TEMP | MASK_EE_TOO_LOW_TEMP)
/* Background operation status */
enum bkops_status {
BKOPS_STATUS_NO_OP = 0x0,
BKOPS_STATUS_NON_CRITICAL = 0x1,
BKOPS_STATUS_PERF_IMPACT = 0x2,
BKOPS_STATUS_CRITICAL = 0x3,
BKOPS_STATUS_MAX = BKOPS_STATUS_CRITICAL,
};
/* UTP QUERY Transaction Specific Fields OpCode */
enum query_opcode {
UPIU_QUERY_OPCODE_NOP = 0x0,
UPIU_QUERY_OPCODE_READ_DESC = 0x1,
UPIU_QUERY_OPCODE_WRITE_DESC = 0x2,
UPIU_QUERY_OPCODE_READ_ATTR = 0x3,
UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4,
UPIU_QUERY_OPCODE_READ_FLAG = 0x5,
UPIU_QUERY_OPCODE_SET_FLAG = 0x6,
UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7,
UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8,
};
/* bRefClkFreq attribute values */
enum ufs_ref_clk_freq {
REF_CLK_FREQ_19_2_MHZ = 0,
REF_CLK_FREQ_26_MHZ = 1,
REF_CLK_FREQ_38_4_MHZ = 2,
REF_CLK_FREQ_52_MHZ = 3,
REF_CLK_FREQ_INVAL = -1,
};
/* Query response result code */
enum {
QUERY_RESULT_SUCCESS = 0x00,
QUERY_RESULT_NOT_READABLE = 0xF6,
QUERY_RESULT_NOT_WRITEABLE = 0xF7,
QUERY_RESULT_ALREADY_WRITTEN = 0xF8,
QUERY_RESULT_INVALID_LENGTH = 0xF9,
QUERY_RESULT_INVALID_VALUE = 0xFA,
QUERY_RESULT_INVALID_SELECTOR = 0xFB,
QUERY_RESULT_INVALID_INDEX = 0xFC,
QUERY_RESULT_INVALID_IDN = 0xFD,
QUERY_RESULT_INVALID_OPCODE = 0xFE,
QUERY_RESULT_GENERAL_FAILURE = 0xFF,
};
/* UTP Transfer Request Command Type (CT) */
enum {
UPIU_COMMAND_SET_TYPE_SCSI = 0x0,
UPIU_COMMAND_SET_TYPE_UFS = 0x1,
UPIU_COMMAND_SET_TYPE_QUERY = 0x2,
};
/* UTP Transfer Request Command Offset */
#define UPIU_COMMAND_TYPE_OFFSET 28
/* Offset of the response code in the UPIU header */
#define UPIU_RSP_CODE_OFFSET 8
enum {
MASK_SCSI_STATUS = 0xFF,
MASK_TASK_RESPONSE = 0xFF00,
MASK_RSP_UPIU_RESULT = 0xFFFF,
MASK_QUERY_DATA_SEG_LEN = 0xFFFF,
MASK_RSP_UPIU_DATA_SEG_LEN = 0xFFFF,
MASK_RSP_EXCEPTION_EVENT = 0x10000,
MASK_TM_SERVICE_RESP = 0xFF,
MASK_TM_FUNC = 0xFF,
};
/* Task management service response */
enum {
UPIU_TASK_MANAGEMENT_FUNC_COMPL = 0x00,
UPIU_TASK_MANAGEMENT_FUNC_NOT_SUPPORTED = 0x04,
UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED = 0x08,
UPIU_TASK_MANAGEMENT_FUNC_FAILED = 0x05,
UPIU_INCORRECT_LOGICAL_UNIT_NO = 0x09,
};
/* UFS device power modes */
enum ufs_dev_pwr_mode {
UFS_ACTIVE_PWR_MODE = 1,
UFS_SLEEP_PWR_MODE = 2,
UFS_POWERDOWN_PWR_MODE = 3,
UFS_DEEPSLEEP_PWR_MODE = 4,
};
#define UFS_WB_BUF_REMAIN_PERCENT(val) ((val) / 10)
/**
* struct utp_cmd_rsp - Response UPIU structure
* @residual_transfer_count: Residual transfer count DW-3
* @reserved: Reserved double words DW-4 to DW-7
* @sense_data_len: Sense data length DW-8 U16
* @sense_data: Sense data field DW-8 to DW-12
*/
struct utp_cmd_rsp {
__be32 residual_transfer_count;
__be32 reserved[4];
__be16 sense_data_len;
u8 sense_data[UFS_SENSE_SIZE];
};
struct ufshpb_active_field {
__be16 active_rgn;
__be16 active_srgn;
};
#define HPB_ACT_FIELD_SIZE 4
/**
* struct utp_hpb_rsp - Response UPIU structure
* @residual_transfer_count: Residual transfer count DW-3
* @reserved1: Reserved double words DW-4 to DW-7
* @sense_data_len: Sense data length DW-8 U16
* @desc_type: Descriptor type of sense data
* @additional_len: Additional length of sense data
* @hpb_op: HPB operation type
* @lun: LUN of response UPIU
* @active_rgn_cnt: Active region count
* @inactive_rgn_cnt: Inactive region count
* @hpb_active_field: Recommended to read HPB region and subregion
* @hpb_inactive_field: To be inactivated HPB region and subregion
*/
struct utp_hpb_rsp {
__be32 residual_transfer_count;
__be32 reserved1[4];
__be16 sense_data_len;
u8 desc_type;
u8 additional_len;
u8 hpb_op;
u8 lun;
u8 active_rgn_cnt;
u8 inactive_rgn_cnt;
struct ufshpb_active_field hpb_active_field[2];
__be16 hpb_inactive_field[2];
};
#define UTP_HPB_RSP_SIZE 40
/**
* struct utp_upiu_rsp - general upiu response structure
* @header: UPIU header structure DW-0 to DW-2
* @sr: fields structure for scsi command DW-3 to DW-12
* @qr: fields structure for query request DW-3 to DW-7
*/
struct utp_upiu_rsp {
struct utp_upiu_header header;
union {
struct utp_cmd_rsp sr;
struct utp_hpb_rsp hr;
struct utp_upiu_query qr;
};
};
/**
* struct ufs_query_req - parameters for building a query request
* @query_func: UPIU header query function
* @upiu_req: the query request data
*/
struct ufs_query_req {
u8 query_func;
struct utp_upiu_query upiu_req;
};
/**
* struct ufs_query_resp - UPIU QUERY
* @response: device response code
* @upiu_res: query response data
*/
struct ufs_query_res {
u8 response;
struct utp_upiu_query upiu_res;
};
/*
* VCCQ & VCCQ2 current requirement when UFS device is in sleep state
* and link is in Hibern8 state.
*/
#define UFS_VREG_LPM_LOAD_UA 1000 /* uA */
struct ufs_vreg {
struct regulator *reg;
const char *name;
bool always_on;
bool enabled;
int max_uA;
};
struct ufs_vreg_info {
struct ufs_vreg *vcc;
struct ufs_vreg *vccq;
struct ufs_vreg *vccq2;
struct ufs_vreg *vdd_hba;
};
struct ufs_dev_info {
bool f_power_on_wp_en;
/* Keeps information if any of the LU is power on write protected */
bool is_lu_power_on_wp;
/* Maximum number of general LU supported by the UFS device */
u8 max_lu_supported;
u16 wmanufacturerid;
/*UFS device Product Name */
u8 *model;
u16 wspecversion;
u32 clk_gating_wait_us;
/* UFS HPB related flag */
bool hpb_enabled;
/* UFS WB related flags */
bool wb_enabled;
bool wb_buf_flush_enabled;
u8 wb_dedicated_lu;
u8 wb_buffer_type;
bool b_rpm_dev_flush_capable;
u8 b_presrv_uspc_en;
};
/*
* This enum is used in string mapping in include/trace/events/ufs.h.
*/
enum ufs_trace_str_t {
UFS_CMD_SEND, UFS_CMD_COMP, UFS_DEV_COMP,
UFS_QUERY_SEND, UFS_QUERY_COMP, UFS_QUERY_ERR,
UFS_TM_SEND, UFS_TM_COMP, UFS_TM_ERR
};
/*
* Transaction Specific Fields (TSF) type in the UPIU package, this enum is
* used in include/trace/events/ufs.h for UFS command trace.
*/
enum ufs_trace_tsf_t {
UFS_TSF_CDB, UFS_TSF_OSF, UFS_TSF_TM_INPUT, UFS_TSF_TM_OUTPUT
};
#endif /* End of Header */

116
include/ufs/ufs_quirks.h Normal file
View File

@ -0,0 +1,116 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
*/
#ifndef _UFS_QUIRKS_H_
#define _UFS_QUIRKS_H_
/* return true if s1 is a prefix of s2 */
#define STR_PRFX_EQUAL(s1, s2) !strncmp(s1, s2, strlen(s1))
#define UFS_ANY_VENDOR 0xFFFF
#define UFS_ANY_MODEL "ANY_MODEL"
#define UFS_VENDOR_MICRON 0x12C
#define UFS_VENDOR_SAMSUNG 0x1CE
#define UFS_VENDOR_SKHYNIX 0x1AD
#define UFS_VENDOR_TOSHIBA 0x198
#define UFS_VENDOR_WDC 0x145
/**
* ufs_dev_quirk - ufs device quirk info
* @card: ufs card details
* @quirk: device quirk
*/
struct ufs_dev_quirk {
u16 wmanufacturerid;
const u8 *model;
unsigned int quirk;
};
/*
* Some vendor's UFS device sends back to back NACs for the DL data frames
* causing the host controller to raise the DFES error status. Sometimes
* such UFS devices send back to back NAC without waiting for new
* retransmitted DL frame from the host and in such cases it might be possible
* the Host UniPro goes into bad state without raising the DFES error
* interrupt. If this happens then all the pending commands would timeout
* only after respective SW command (which is generally too large).
*
* We can workaround such device behaviour like this:
* - As soon as SW sees the DL NAC error, it should schedule the error handler
* - Error handler would sleep for 50ms to see if there are any fatal errors
* raised by UFS controller.
* - If there are fatal errors then SW does normal error recovery.
* - If there are no fatal errors then SW sends the NOP command to device
* to check if link is alive.
* - If NOP command times out, SW does normal error recovery
* - If NOP command succeed, skip the error handling.
*
* If DL NAC error is seen multiple times with some vendor's UFS devices then
* enable this quirk to initiate quick error recovery and also silence related
* error logs to reduce spamming of kernel logs.
*/
#define UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS (1 << 2)
/*
* Few Toshiba UFS device models advertise RX_MIN_ACTIVATETIME_CAPABILITY as
* 600us which may not be enough for reliable hibern8 exit hardware sequence
* from UFS device.
* To workaround this issue, host should set its PA_TACTIVATE time to 1ms even
* if device advertises RX_MIN_ACTIVATETIME_CAPABILITY less than 1ms.
*/
#define UFS_DEVICE_QUIRK_PA_TACTIVATE (1 << 4)
/*
* It seems some UFS devices may keep drawing more than sleep current
* (atleast for 500us) from UFS rails (especially from VCCQ rail).
* To avoid this situation, add 2ms delay before putting these UFS
* rails in LPM mode.
*/
#define UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM (1 << 6)
/*
* Some UFS devices require host PA_TACTIVATE to be lower than device
* PA_TACTIVATE, enabling this quirk ensure this.
*/
#define UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE (1 << 7)
/*
* The max. value PA_SaveConfigTime is 250 (10us) but this is not enough for
* some vendors.
* Gear switch from PWM to HS may fail even with this max. PA_SaveConfigTime.
* Gear switch can be issued by host controller as an error recovery and any
* software delay will not help on this case so we need to increase
* PA_SaveConfigTime to >32us as per vendor recommendation.
*/
#define UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME (1 << 8)
/*
* Some UFS devices require VS_DebugSaveConfigTime is 0x10,
* enabling this quirk ensure this.
*/
#define UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME (1 << 9)
/*
* Some pre-3.1 UFS devices can support extended features by upgrading
* the firmware. Enable this quirk to make UFS core driver probe and enable
* supported features on such devices.
*/
#define UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES (1 << 10)
/*
* Some UFS devices require delay after VCC power rail is turned-off.
* Enable this quirk to introduce 5ms delays after VCC power-off during
* suspend flow.
*/
#define UFS_DEVICE_QUIRK_DELAY_AFTER_LPM (1 << 11)
/*
* Some UFS devices require L2P entry should be swapped before being sent to the
* UFS device for HPB READ command.
*/
#define UFS_DEVICE_QUIRK_SWAP_L2P_ENTRY_FOR_HPB_READ (1 << 12)
#endif /* UFS_QUIRKS_H_ */

1245
include/ufs/ufshcd.h Normal file
View File

File diff suppressed because it is too large Load Diff

506
include/ufs/ufshci.h Normal file
View File

@ -0,0 +1,506 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Universal Flash Storage Host controller driver
* Copyright (C) 2011-2013 Samsung India Software Operations
*
* Authors:
* Santosh Yaraganavi <santosh.sy@samsung.com>
* Vinayak Holikatti <h.vinayak@samsung.com>
*/
#ifndef _UFSHCI_H
#define _UFSHCI_H
#include <scsi/scsi_host.h>
enum {
TASK_REQ_UPIU_SIZE_DWORDS = 8,
TASK_RSP_UPIU_SIZE_DWORDS = 8,
ALIGNED_UPIU_SIZE = 512,
};
/* UFSHCI Registers */
enum {
REG_CONTROLLER_CAPABILITIES = 0x00,
REG_UFS_VERSION = 0x08,
REG_CONTROLLER_DEV_ID = 0x10,
REG_CONTROLLER_PROD_ID = 0x14,
REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
REG_INTERRUPT_STATUS = 0x20,
REG_INTERRUPT_ENABLE = 0x24,
REG_CONTROLLER_STATUS = 0x30,
REG_CONTROLLER_ENABLE = 0x34,
REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
REG_UIC_ERROR_CODE_DME = 0x48,
REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
REG_UIC_COMMAND = 0x90,
REG_UIC_COMMAND_ARG_1 = 0x94,
REG_UIC_COMMAND_ARG_2 = 0x98,
REG_UIC_COMMAND_ARG_3 = 0x9C,
UFSHCI_REG_SPACE_SIZE = 0xA0,
REG_UFS_CCAP = 0x100,
REG_UFS_CRYPTOCAP = 0x104,
UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
};
/* Controller capability masks */
enum {
MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
MASK_64_ADDRESSING_SUPPORT = 0x01000000,
MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
MASK_CRYPTO_SUPPORT = 0x10000000,
};
#define UFS_MASK(mask, offset) ((mask) << (offset))
/* UFS Version 08h */
#define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0)
#define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16)
/*
* Controller UFSHCI version
* - 2.x and newer use the following scheme:
* major << 8 + minor << 4
* - 1.x has been converted to match this in
* ufshcd_get_ufs_version()
*/
static inline u32 ufshci_version(u32 major, u32 minor)
{
return (major << 8) + (minor << 4);
}
/*
* HCDDID - Host Controller Identification Descriptor
* - Device ID and Device Class 10h
*/
#define DEVICE_CLASS UFS_MASK(0xFFFF, 0)
#define DEVICE_ID UFS_MASK(0xFF, 24)
/*
* HCPMID - Host Controller Identification Descriptor
* - Product/Manufacturer ID 14h
*/
#define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0)
#define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16)
/* AHIT - Auto-Hibernate Idle Timer */
#define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0)
#define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10)
#define UFSHCI_AHIBERN8_SCALE_FACTOR 10
#define UFSHCI_AHIBERN8_MAX (1023 * 100000)
/*
* IS - Interrupt Status - 20h
*/
#define UTP_TRANSFER_REQ_COMPL 0x1
#define UIC_DME_END_PT_RESET 0x2
#define UIC_ERROR 0x4
#define UIC_TEST_MODE 0x8
#define UIC_POWER_MODE 0x10
#define UIC_HIBERNATE_EXIT 0x20
#define UIC_HIBERNATE_ENTER 0x40
#define UIC_LINK_LOST 0x80
#define UIC_LINK_STARTUP 0x100
#define UTP_TASK_REQ_COMPL 0x200
#define UIC_COMMAND_COMPL 0x400
#define DEVICE_FATAL_ERROR 0x800
#define CONTROLLER_FATAL_ERROR 0x10000
#define SYSTEM_BUS_FATAL_ERROR 0x20000
#define CRYPTO_ENGINE_FATAL_ERROR 0x40000
#define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\
UIC_HIBERNATE_EXIT)
#define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\
UIC_POWER_MODE)
#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
#define UFSHCD_ERROR_MASK (UIC_ERROR | INT_FATAL_ERRORS)
#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
CONTROLLER_FATAL_ERROR |\
SYSTEM_BUS_FATAL_ERROR |\
CRYPTO_ENGINE_FATAL_ERROR |\
UIC_LINK_LOST)
/* HCS - Host Controller Status 30h */
#define DEVICE_PRESENT 0x1
#define UTP_TRANSFER_REQ_LIST_READY 0x2
#define UTP_TASK_REQ_LIST_READY 0x4
#define UIC_COMMAND_READY 0x8
#define HOST_ERROR_INDICATOR 0x10
#define DEVICE_ERROR_INDICATOR 0x20
#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
#define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
UTP_TASK_REQ_LIST_READY |\
UIC_COMMAND_READY)
enum {
PWR_OK = 0x0,
PWR_LOCAL = 0x01,
PWR_REMOTE = 0x02,
PWR_BUSY = 0x03,
PWR_ERROR_CAP = 0x04,
PWR_FATAL_ERROR = 0x05,
};
/* HCE - Host Controller Enable 34h */
#define CONTROLLER_ENABLE 0x1
#define CONTROLLER_DISABLE 0x0
#define CRYPTO_GENERAL_ENABLE 0x2
/* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
#define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000
#define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F
#define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF
#define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10
/* UECDL - Host UIC Error Code Data Link Layer 3Ch */
#define UIC_DATA_LINK_LAYER_ERROR 0x80000000
#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF
#define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2
#define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4
#define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8
#define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20
#define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000
#define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001
#define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
/* UECN - Host UIC Error Code Network Layer 40h */
#define UIC_NETWORK_LAYER_ERROR 0x80000000
#define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7
#define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1
#define UIC_NETWORK_BAD_DEVICEID_ENC 0x2
#define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4
/* UECT - Host UIC Error Code Transport Layer 44h */
#define UIC_TRANSPORT_LAYER_ERROR 0x80000000
#define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
#define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1
#define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2
#define UIC_TRANSPORT_NO_CONNECTION_RX 0x4
#define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8
#define UIC_TRANSPORT_BAD_TC 0x10
#define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20
#define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40
/* UECDME - Host UIC Error Code DME 48h */
#define UIC_DME_ERROR 0x80000000
#define UIC_DME_ERROR_CODE_MASK 0x1
/* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
#define INT_AGGR_TIMEOUT_VAL_MASK 0xFF
#define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)
#define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000
#define INT_AGGR_STATUS_BIT 0x100000
#define INT_AGGR_PARAM_WRITE 0x1000000
#define INT_AGGR_ENABLE 0x80000000
/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
/* UICCMD - UIC Command */
#define COMMAND_OPCODE_MASK 0xFF
#define GEN_SELECTOR_INDEX_MASK 0xFFFF
#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
#define RESET_LEVEL 0xFF
#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
#define CONFIG_RESULT_CODE_MASK 0xFF
#define GENERIC_ERROR_CODE_MASK 0xFF
/* GenSelectorIndex calculation macros for M-PHY attributes */
#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
((sel) & 0xFFFF))
#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
/* Link Status*/
enum link_status {
UFSHCD_LINK_IS_DOWN = 1,
UFSHCD_LINK_IS_UP = 2,
};
/* UIC Commands */
enum uic_cmd_dme {
UIC_CMD_DME_GET = 0x01,
UIC_CMD_DME_SET = 0x02,
UIC_CMD_DME_PEER_GET = 0x03,
UIC_CMD_DME_PEER_SET = 0x04,
UIC_CMD_DME_POWERON = 0x10,
UIC_CMD_DME_POWEROFF = 0x11,
UIC_CMD_DME_ENABLE = 0x12,
UIC_CMD_DME_RESET = 0x14,
UIC_CMD_DME_END_PT_RST = 0x15,
UIC_CMD_DME_LINK_STARTUP = 0x16,
UIC_CMD_DME_HIBER_ENTER = 0x17,
UIC_CMD_DME_HIBER_EXIT = 0x18,
UIC_CMD_DME_TEST_MODE = 0x1A,
};
/* UIC Config result code / Generic error code */
enum {
UIC_CMD_RESULT_SUCCESS = 0x00,
UIC_CMD_RESULT_INVALID_ATTR = 0x01,
UIC_CMD_RESULT_FAILURE = 0x01,
UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
UIC_CMD_RESULT_BAD_INDEX = 0x05,
UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
UIC_CMD_RESULT_BUSY = 0x09,
UIC_CMD_RESULT_DME_FAILURE = 0x0A,
};
#define MASK_UIC_COMMAND_RESULT 0xFF
#define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8)
#define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0)
/* Interrupt disable masks */
enum {
/* Interrupt disable mask for UFSHCI v1.0 */
INTERRUPT_MASK_ALL_VER_10 = 0x30FFF,
INTERRUPT_MASK_RW_VER_10 = 0x30000,
/* Interrupt disable mask for UFSHCI v1.1 */
INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,
/* Interrupt disable mask for UFSHCI v2.1 */
INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
};
/* CCAP - Crypto Capability 100h */
union ufs_crypto_capabilities {
__le32 reg_val;
struct {
u8 num_crypto_cap;
u8 config_count;
u8 reserved;
u8 config_array_ptr;
};
};
enum ufs_crypto_key_size {
UFS_CRYPTO_KEY_SIZE_INVALID = 0x0,
UFS_CRYPTO_KEY_SIZE_128 = 0x1,
UFS_CRYPTO_KEY_SIZE_192 = 0x2,
UFS_CRYPTO_KEY_SIZE_256 = 0x3,
UFS_CRYPTO_KEY_SIZE_512 = 0x4,
};
enum ufs_crypto_alg {
UFS_CRYPTO_ALG_AES_XTS = 0x0,
UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1,
UFS_CRYPTO_ALG_AES_ECB = 0x2,
UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3,
};
/* x-CRYPTOCAP - Crypto Capability X */
union ufs_crypto_cap_entry {
__le32 reg_val;
struct {
u8 algorithm_id;
u8 sdus_mask; /* Supported data unit size mask */
u8 key_size;
u8 reserved;
};
};
#define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
#define UFS_CRYPTO_KEY_MAX_SIZE 64
/* x-CRYPTOCFG - Crypto Configuration X */
union ufs_crypto_cfg_entry {
__le32 reg_val[32];
struct {
u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE];
u8 data_unit_size;
u8 crypto_cap_idx;
u8 reserved_1;
u8 config_enable;
u8 reserved_multi_host;
u8 reserved_2;
u8 vsb[2];
u8 reserved_3[56];
};
};
/*
* Request Descriptor Definitions
*/
/* Transfer request command type */
enum {
UTP_CMD_TYPE_SCSI = 0x0,
UTP_CMD_TYPE_UFS = 0x1,
UTP_CMD_TYPE_DEV_MANAGE = 0x2,
};
/* To accommodate UFS2.0 required Command type */
enum {
UTP_CMD_TYPE_UFS_STORAGE = 0x1,
};
enum {
UTP_SCSI_COMMAND = 0x00000000,
UTP_NATIVE_UFS_COMMAND = 0x10000000,
UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
UTP_REQ_DESC_INT_CMD = 0x01000000,
UTP_REQ_DESC_CRYPTO_ENABLE_CMD = 0x00800000,
};
/* UTP Transfer Request Data Direction (DD) */
enum {
UTP_NO_DATA_TRANSFER = 0x00000000,
UTP_HOST_TO_DEVICE = 0x02000000,
UTP_DEVICE_TO_HOST = 0x04000000,
};
/* Overall command status values */
enum utp_ocs {
OCS_SUCCESS = 0x0,
OCS_INVALID_CMD_TABLE_ATTR = 0x1,
OCS_INVALID_PRDT_ATTR = 0x2,
OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
OCS_PEER_COMM_FAILURE = 0x5,
OCS_ABORTED = 0x6,
OCS_FATAL_ERROR = 0x7,
OCS_DEVICE_FATAL_ERROR = 0x8,
OCS_INVALID_CRYPTO_CONFIG = 0x9,
OCS_GENERAL_CRYPTO_ERROR = 0xA,
OCS_INVALID_COMMAND_STATUS = 0x0F,
};
enum {
MASK_OCS = 0x0F,
};
/* The maximum length of the data byte count field in the PRDT is 256KB */
#define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024)
/* The granularity of the data byte count field in the PRDT is 32-bit */
#define PRDT_DATA_BYTE_COUNT_PAD 4
/**
* struct ufshcd_sg_entry - UFSHCI PRD Entry
* @addr: Physical address; DW-0 and DW-1.
* @reserved: Reserved for future use DW-2
* @size: size of physical segment DW-3
*/
struct ufshcd_sg_entry {
__le64 addr;
__le32 reserved;
__le32 size;
};
/**
* struct utp_transfer_cmd_desc - UTP Command Descriptor (UCD)
* @command_upiu: Command UPIU Frame address
* @response_upiu: Response UPIU Frame address
* @prd_table: Physical Region Descriptor
*/
struct utp_transfer_cmd_desc {
u8 command_upiu[ALIGNED_UPIU_SIZE];
u8 response_upiu[ALIGNED_UPIU_SIZE];
struct ufshcd_sg_entry prd_table[SG_ALL];
};
/**
* struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
* @dword0: Descriptor Header DW0
* @dword1: Descriptor Header DW1
* @dword2: Descriptor Header DW2
* @dword3: Descriptor Header DW3
*/
struct request_desc_header {
__le32 dword_0;
__le32 dword_1;
__le32 dword_2;
__le32 dword_3;
};
/**
* struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD)
* @header: UTRD header DW-0 to DW-3
* @command_desc_base_addr_lo: UCD base address low DW-4
* @command_desc_base_addr_hi: UCD base address high DW-5
* @response_upiu_length: response UPIU length DW-6
* @response_upiu_offset: response UPIU offset DW-6
* @prd_table_length: Physical region descriptor length DW-7
* @prd_table_offset: Physical region descriptor offset DW-7
*/
struct utp_transfer_req_desc {
/* DW 0-3 */
struct request_desc_header header;
/* DW 4-5*/
__le32 command_desc_base_addr_lo;
__le32 command_desc_base_addr_hi;
/* DW 6 */
__le16 response_upiu_length;
__le16 response_upiu_offset;
/* DW 7 */
__le16 prd_table_length;
__le16 prd_table_offset;
};
/*
* UTMRD structure.
*/
struct utp_task_req_desc {
/* DW 0-3 */
struct request_desc_header header;
/* DW 4-11 - Task request UPIU structure */
struct {
struct utp_upiu_header req_header;
__be32 input_param1;
__be32 input_param2;
__be32 input_param3;
__be32 __reserved1[2];
} upiu_req;
/* DW 12-19 - Task Management Response UPIU structure */
struct {
struct utp_upiu_header rsp_header;
__be32 output_param1;
__be32 output_param2;
__be32 __reserved2[3];
} upiu_rsp;
};
#endif /* End of Header */

316
include/ufs/unipro.h Normal file
View File

@ -0,0 +1,316 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2013 Samsung Electronics Co., Ltd.
*/
#ifndef _UNIPRO_H_
#define _UNIPRO_H_
/*
* M-TX Configuration Attributes
*/
#define TX_HIBERN8TIME_CAPABILITY 0x000F
#define TX_MODE 0x0021
#define TX_HSRATE_SERIES 0x0022
#define TX_HSGEAR 0x0023
#define TX_PWMGEAR 0x0024
#define TX_AMPLITUDE 0x0025
#define TX_HS_SLEWRATE 0x0026
#define TX_SYNC_SOURCE 0x0027
#define TX_HS_SYNC_LENGTH 0x0028
#define TX_HS_PREPARE_LENGTH 0x0029
#define TX_LS_PREPARE_LENGTH 0x002A
#define TX_HIBERN8_CONTROL 0x002B
#define TX_LCC_ENABLE 0x002C
#define TX_PWM_BURST_CLOSURE_EXTENSION 0x002D
#define TX_BYPASS_8B10B_ENABLE 0x002E
#define TX_DRIVER_POLARITY 0x002F
#define TX_HS_UNTERMINATED_LINE_DRIVE_ENABLE 0x0030
#define TX_LS_TERMINATED_LINE_DRIVE_ENABLE 0x0031
#define TX_LCC_SEQUENCER 0x0032
#define TX_MIN_ACTIVATETIME 0x0033
#define TX_PWM_G6_G7_SYNC_LENGTH 0x0034
#define TX_REFCLKFREQ 0x00EB
#define TX_CFGCLKFREQVAL 0x00EC
#define CFGEXTRATTR 0x00F0
#define DITHERCTRL2 0x00F1
/*
* M-RX Configuration Attributes
*/
#define RX_HS_G1_SYNC_LENGTH_CAP 0x008B
#define RX_HS_G1_PREP_LENGTH_CAP 0x008C
#define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F
#define RX_HIBERN8TIME_CAPABILITY 0x0092
#define RX_HS_G2_SYNC_LENGTH_CAP 0x0094
#define RX_HS_G3_SYNC_LENGTH_CAP 0x0095
#define RX_HS_G2_PREP_LENGTH_CAP 0x0096
#define RX_HS_G3_PREP_LENGTH_CAP 0x0097
#define RX_ADV_GRANULARITY_CAP 0x0098
#define RX_HIBERN8TIME_CAP 0x0092
#define RX_ADV_HIBERN8TIME_CAP 0x0099
#define RX_ADV_MIN_ACTIVATETIME_CAP 0x009A
#define RX_MODE 0x00A1
#define RX_HSRATE_SERIES 0x00A2
#define RX_HSGEAR 0x00A3
#define RX_PWMGEAR 0x00A4
#define RX_LS_TERMINATED_ENABLE 0x00A5
#define RX_HS_UNTERMINATED_ENABLE 0x00A6
#define RX_ENTER_HIBERN8 0x00A7
#define RX_BYPASS_8B10B_ENABLE 0x00A8
#define RX_TERMINATION_FORCE_ENABLE 0x00A9
#define RXCALCTRL 0x00B4
#define RXSQCTRL 0x00B5
#define CFGRXCDR8 0x00BA
#define CFGRXOVR8 0x00BD
#define CFGRXOVR6 0x00BF
#define RXDIRECTCTRL2 0x00C7
#define CFGRXOVR4 0x00E9
#define RX_REFCLKFREQ 0x00EB
#define RX_CFGCLKFREQVAL 0x00EC
#define CFGWIDEINLN 0x00F0
#define ENARXDIRECTCFG4 0x00F2
#define ENARXDIRECTCFG3 0x00F3
#define ENARXDIRECTCFG2 0x00F4
#define is_mphy_tx_attr(attr) (attr < RX_MODE)
#define RX_ADV_FINE_GRAN_STEP(x) ((((x) & 0x3) << 1) | 0x1)
#define SYNC_LEN_FINE(x) ((x) & 0x3F)
#define SYNC_LEN_COARSE(x) ((1 << 6) | ((x) & 0x3F))
#define PREP_LEN(x) ((x) & 0xF)
#define RX_MIN_ACTIVATETIME_UNIT_US 100
#define HIBERN8TIME_UNIT_US 100
/*
* Common Block Attributes
*/
#define TX_GLOBALHIBERNATE UNIPRO_CB_OFFSET(0x002B)
#define REFCLKMODE UNIPRO_CB_OFFSET(0x00BF)
#define DIRECTCTRL19 UNIPRO_CB_OFFSET(0x00CD)
#define DIRECTCTRL10 UNIPRO_CB_OFFSET(0x00E6)
#define CDIRECTCTRL6 UNIPRO_CB_OFFSET(0x00EA)
#define RTOBSERVESELECT UNIPRO_CB_OFFSET(0x00F0)
#define CBDIVFACTOR UNIPRO_CB_OFFSET(0x00F1)
#define CBDCOCTRL5 UNIPRO_CB_OFFSET(0x00F3)
#define CBPRGPLL2 UNIPRO_CB_OFFSET(0x00F8)
#define CBPRGTUNING UNIPRO_CB_OFFSET(0x00FB)
#define UNIPRO_CB_OFFSET(x) (0x8000 | x)
/*
* PHY Adapter attributes
*/
#define PA_PHY_TYPE 0x1500
#define PA_AVAILTXDATALANES 0x1520
#define PA_MAXTXSPEEDFAST 0x1521
#define PA_MAXTXSPEEDSLOW 0x1522
#define PA_MAXRXSPEEDFAST 0x1541
#define PA_MAXRXSPEEDSLOW 0x1542
#define PA_TXLINKSTARTUPHS 0x1544
#define PA_AVAILRXDATALANES 0x1540
#define PA_MINRXTRAILINGCLOCKS 0x1543
#define PA_LOCAL_TX_LCC_ENABLE 0x155E
#define PA_ACTIVETXDATALANES 0x1560
#define PA_CONNECTEDTXDATALANES 0x1561
#define PA_TXFORCECLOCK 0x1562
#define PA_TXPWRMODE 0x1563
#define PA_TXTRAILINGCLOCKS 0x1564
#define PA_TXSPEEDFAST 0x1565
#define PA_TXSPEEDSLOW 0x1566
#define PA_TXPWRSTATUS 0x1567
#define PA_TXGEAR 0x1568
#define PA_TXTERMINATION 0x1569
#define PA_HSSERIES 0x156A
#define PA_LEGACYDPHYESCDL 0x1570
#define PA_PWRMODE 0x1571
#define PA_ACTIVERXDATALANES 0x1580
#define PA_CONNECTEDRXDATALANES 0x1581
#define PA_RXPWRSTATUS 0x1582
#define PA_RXGEAR 0x1583
#define PA_RXTERMINATION 0x1584
#define PA_MAXRXPWMGEAR 0x1586
#define PA_MAXRXHSGEAR 0x1587
#define PA_PACPREQTIMEOUT 0x1590
#define PA_PACPREQEOBTIMEOUT 0x1591
#define PA_REMOTEVERINFO 0x15A0
#define PA_LOGICALLANEMAP 0x15A1
#define PA_SLEEPNOCONFIGTIME 0x15A2
#define PA_STALLNOCONFIGTIME 0x15A3
#define PA_SAVECONFIGTIME 0x15A4
#define PA_RXHSUNTERMCAP 0x15A5
#define PA_RXLSTERMCAP 0x15A6
#define PA_GRANULARITY 0x15AA
#define PA_HIBERN8TIME 0x15A7
#define PA_LOCALVERINFO 0x15A9
#define PA_GRANULARITY 0x15AA
#define PA_TACTIVATE 0x15A8
#define PA_PWRMODEUSERDATA0 0x15B0
#define PA_PWRMODEUSERDATA1 0x15B1
#define PA_PWRMODEUSERDATA2 0x15B2
#define PA_PWRMODEUSERDATA3 0x15B3
#define PA_PWRMODEUSERDATA4 0x15B4
#define PA_PWRMODEUSERDATA5 0x15B5
#define PA_PWRMODEUSERDATA6 0x15B6
#define PA_PWRMODEUSERDATA7 0x15B7
#define PA_PWRMODEUSERDATA8 0x15B8
#define PA_PWRMODEUSERDATA9 0x15B9
#define PA_PWRMODEUSERDATA10 0x15BA
#define PA_PWRMODEUSERDATA11 0x15BB
#define PA_PACPFRAMECOUNT 0x15C0
#define PA_PACPERRORCOUNT 0x15C1
#define PA_PHYTESTCONTROL 0x15C2
#define PA_TXHSADAPTTYPE 0x15D4
/* Adpat type for PA_TXHSADAPTTYPE attribute */
#define PA_REFRESH_ADAPT 0x00
#define PA_INITIAL_ADAPT 0x01
#define PA_NO_ADAPT 0x03
#define PA_TACTIVATE_TIME_UNIT_US 10
#define PA_HIBERN8_TIME_UNIT_US 100
/*Other attributes*/
#define VS_POWERSTATE 0xD083
#define VS_MPHYCFGUPDT 0xD085
#define VS_DEBUGOMC 0xD09E
#define PA_GRANULARITY_MIN_VAL 1
#define PA_GRANULARITY_MAX_VAL 6
/* PHY Adapter Protocol Constants */
#define PA_MAXDATALANES 4
#define DL_FC0ProtectionTimeOutVal_Default 8191
#define DL_TC0ReplayTimeOutVal_Default 65535
#define DL_AFC0ReqTimeOutVal_Default 32767
#define DL_FC1ProtectionTimeOutVal_Default 8191
#define DL_TC1ReplayTimeOutVal_Default 65535
#define DL_AFC1ReqTimeOutVal_Default 32767
#define DME_LocalFC0ProtectionTimeOutVal 0xD041
#define DME_LocalTC0ReplayTimeOutVal 0xD042
#define DME_LocalAFC0ReqTimeOutVal 0xD043
/* PA power modes */
enum {
FAST_MODE = 1,
SLOW_MODE = 2,
FASTAUTO_MODE = 4,
SLOWAUTO_MODE = 5,
UNCHANGED = 7,
};
#define PWRMODE_MASK 0xF
#define PWRMODE_RX_OFFSET 4
/* PA TX/RX Frequency Series */
enum {
PA_HS_MODE_A = 1,
PA_HS_MODE_B = 2,
};
enum ufs_pwm_gear_tag {
UFS_PWM_DONT_CHANGE, /* Don't change Gear */
UFS_PWM_G1, /* PWM Gear 1 (default for reset) */
UFS_PWM_G2, /* PWM Gear 2 */
UFS_PWM_G3, /* PWM Gear 3 */
UFS_PWM_G4, /* PWM Gear 4 */
UFS_PWM_G5, /* PWM Gear 5 */
UFS_PWM_G6, /* PWM Gear 6 */
UFS_PWM_G7, /* PWM Gear 7 */
};
enum ufs_hs_gear_tag {
UFS_HS_DONT_CHANGE, /* Don't change Gear */
UFS_HS_G1, /* HS Gear 1 (default for reset) */
UFS_HS_G2, /* HS Gear 2 */
UFS_HS_G3, /* HS Gear 3 */
UFS_HS_G4, /* HS Gear 4 */
UFS_HS_G5 /* HS Gear 5 */
};
enum ufs_unipro_ver {
UFS_UNIPRO_VER_RESERVED = 0,
UFS_UNIPRO_VER_1_40 = 1, /* UniPro version 1.40 */
UFS_UNIPRO_VER_1_41 = 2, /* UniPro version 1.41 */
UFS_UNIPRO_VER_1_6 = 3, /* UniPro version 1.6 */
UFS_UNIPRO_VER_1_61 = 4, /* UniPro version 1.61 */
UFS_UNIPRO_VER_1_8 = 5, /* UniPro version 1.8 */
UFS_UNIPRO_VER_MAX = 6, /* UniPro unsupported version */
/* UniPro version field mask in PA_LOCALVERINFO */
UFS_UNIPRO_VER_MASK = 0xF,
};
/*
* Data Link Layer Attributes
*/
#define DL_TXPREEMPTIONCAP 0x2000
#define DL_TC0TXMAXSDUSIZE 0x2001
#define DL_TC0RXINITCREDITVAL 0x2002
#define DL_TC1TXMAXSDUSIZE 0x2003
#define DL_TC1RXINITCREDITVAL 0x2004
#define DL_TC0TXBUFFERSIZE 0x2005
#define DL_TC1TXBUFFERSIZE 0x2006
#define DL_TC0TXFCTHRESHOLD 0x2040
#define DL_FC0PROTTIMEOUTVAL 0x2041
#define DL_TC0REPLAYTIMEOUTVAL 0x2042
#define DL_AFC0REQTIMEOUTVAL 0x2043
#define DL_AFC0CREDITTHRESHOLD 0x2044
#define DL_TC0OUTACKTHRESHOLD 0x2045
#define DL_PEERTC0PRESENT 0x2046
#define DL_PEERTC0RXINITCREVAL 0x2047
#define DL_TC1TXFCTHRESHOLD 0x2060
#define DL_FC1PROTTIMEOUTVAL 0x2061
#define DL_TC1REPLAYTIMEOUTVAL 0x2062
#define DL_AFC1REQTIMEOUTVAL 0x2063
#define DL_AFC1CREDITTHRESHOLD 0x2064
#define DL_TC1OUTACKTHRESHOLD 0x2065
#define DL_PEERTC1PRESENT 0x2066
#define DL_PEERTC1RXINITCREVAL 0x2067
/*
* Network Layer Attributes
*/
#define N_DEVICEID 0x3000
#define N_DEVICEID_VALID 0x3001
#define N_TC0TXMAXSDUSIZE 0x3020
#define N_TC1TXMAXSDUSIZE 0x3021
/*
* Transport Layer Attributes
*/
#define T_NUMCPORTS 0x4000
#define T_NUMTESTFEATURES 0x4001
#define T_CONNECTIONSTATE 0x4020
#define T_PEERDEVICEID 0x4021
#define T_PEERCPORTID 0x4022
#define T_TRAFFICCLASS 0x4023
#define T_PROTOCOLID 0x4024
#define T_CPORTFLAGS 0x4025
#define T_TXTOKENVALUE 0x4026
#define T_RXTOKENVALUE 0x4027
#define T_LOCALBUFFERSPACE 0x4028
#define T_PEERBUFFERSPACE 0x4029
#define T_CREDITSTOSEND 0x402A
#define T_CPORTMODE 0x402B
#define T_TC0TXMAXSDUSIZE 0x4060
#define T_TC1TXMAXSDUSIZE 0x4061
/* CPort setting */
#define E2EFC_ON (1 << 0)
#define E2EFC_OFF (0 << 0)
#define CSD_N_ON (0 << 1)
#define CSD_N_OFF (1 << 1)
#define CSV_N_ON (0 << 2)
#define CSV_N_OFF (1 << 2)
#define CPORT_DEF_FLAGS (CSV_N_OFF | CSD_N_OFF | E2EFC_OFF)
/* CPort connection state */
enum {
CPORT_IDLE = 0,
CPORT_CONNECTED,
};
#endif /* _UNIPRO_H_ */

18
include/xen/arm/xen-ops.h Normal file
View File

@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_ARM_XEN_OPS_H
#define _ASM_ARM_XEN_OPS_H
#include <xen/swiotlb-xen.h>
#include <xen/xen-ops.h>
static inline void xen_setup_dma_ops(struct device *dev)
{
#ifdef CONFIG_XEN
if (xen_is_grant_dma_device(dev))
xen_grant_setup_dma_ops(dev);
else if (xen_swiotlb_detect())
dev->dma_ops = &xen_swiotlb_dma_ops;
#endif
}
#endif /* _ASM_ARM_XEN_OPS_H */

23
rdp-acceleraed/.github/workflows/c-cpp.yml vendored
View File

@ -1,23 +0,0 @@
name: C/C++ CI
on:
push:
branches: [ master ]
pull_request:
branches: [ master ]
jobs:
build:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
- name: configure
run: ./configure
- name: make
run: make
- name: make check
run: make check
- name: make distcheck
run: make distcheck

18
rdp-acceleraed/.gitignore vendored
View File

@ -1,18 +0,0 @@
# Compiled Object files
*.slo
*.lo
*.o
# Compiled Dynamic libraries
*.so
*.dylib
# Compiled Static libraries
*.lai
*.la
*.a
/Server/build
/nbproject/private/
/nbproject
/Server/config.h
/ffmpeg

21
rdp-acceleraed/LICENSE
View File

@ -1,21 +0,0 @@
The MIT License (MIT)
Copyright (c) 2014 jean343
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.

71
rdp-acceleraed/README.md
View File

@ -1,71 +0,0 @@
RPI-GPU-rdpClient
=================
Video on youtube: http://youtu.be/3HJuHhiXxuE
Hardware accelerated raspberry pi client for windows PC.
It is more a proof-of-concept to show that OpenMAX can be used as a RDP viewer rather than a finished product.
There is no authentication, use at your own risk.
It uses a NVIDIA graphic card to encode H.264 video, and OpenMAX to display the video. It can achieve 1080P 60FPS RDP on a RPI with a relatively low latency of ~200ms on two monitors.
When the GPU is not accessible on the server, it falls back to CPU encoding at a lower FPS, around 10FPS depending on the CPU.
It uses DXGI for accelerated desktop capture in Windows 8
It can work in a Virtual machine in order to be a true thin client.
### To compile the client on the Raspberry PI ###
It needs the following packages. I started on a clean version of the Raspberian OS.
```
sudo apt-get install cmake
sudo apt-get install libboost-thread-dev libboost-system-dev
sudo apt-get install libx11-dev
```
To compile ilclient:
```
cd /opt/vc/src/hello_pi
sudo ./rebuild.sh
```
To compile the RDP client:
```
git clone https://github.com/jean343/RPI-GPU-rdpClient.git
cd RPI-GPU-rdpClient/RPI-Client
mkdir build && cd build/
cmake ..
make
```
### To run the client ###
./client <host> <port>
###To compile the server in windows###
- See the guide at https://github.com/jean343/RPI-GPU-rdpClient/blob/master/WindowsCompileGuide.md
- Optional, FFMPEG for a CPU fallback if the graphic card is unavailable
- Download FFMPEG from http://ffmpeg.zeranoe.com/builds/, need the dev and shared
- Set FFMPEG_ROOT to the root of FFMPEG dev folder
- Add the bin folder of the shared zip to your path, or copy the DLLs
### To run the server ###
./server monitor 0 port 8080
### Contribute ###
Want to be part of the project? Great! All are welcome! We will get there quicker together :)
Whether you find a bug, have a great feature request feel free to get in touch.
### Known issues and limitations ###
- There is no audio
- There is no authentication, use only in a local LAN or under a VPN.
- The software falls back to CPU encoding in a Virtual Machine, it is fast as it uses the x264 superfast preset, but the H.264 quality is reduced.
### NOTES ###
From https://github.com/Hexxeh/rpi-update, update your pi:
```
sudo rpi-update
```
Update software:
```
sudo apt-get update && sudo apt-get upgrade
```

11
rdp-acceleraed/RPI-Client/CMakeLists.txt
View File

@ -1,11 +0,0 @@
cmake_minimum_required(VERSION 2.8)
project( client )
FIND_PACKAGE( Boost REQUIRED COMPONENTS thread )
include_directories("/opt/vc/include/interface/vcos/pthreads/;/opt/vc/include/interface/vmcs_host/linux")
add_executable( client client.cpp )
include_directories(/opt/vc/include /opt/vc/src/hello_pi/libs/ilclient/ ${Boost_INCLUDE_DIR})
target_link_libraries( client X11 /opt/vc/src/hello_pi/libs/ilclient/libilclient.a boost_system /opt/vc/lib/libbcm_host.so /opt/vc/lib/libopenmaxil.so /opt/vc/lib/libvcos.so /opt/vc/lib/libGLESv2.so /opt/vc/lib/libEGL.so ${Boost_LIBRARIES} )

371
rdp-acceleraed/RPI-Client/client.cpp
View File

@ -1,371 +0,0 @@
/*
Copyright (c) 2012, Broadcom Europe Ltd
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the copyright holder nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//
// Copyright (c) 2003-2013 Christopher M. Kohlhoff (chris at kohlhoff dot com)
//
// Distributed under the Boost Software License, Version 1.0. (See accompanying
// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
//
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "bcm_host.h"
extern "C" {
#include "ilclient.h"
}
#include <cstdlib>
#include <cstring>
#include <iostream>
#include <boost/asio.hpp>
#include <boost/thread.hpp>
#include <stdio.h>
#include <X11/Xlib.h>
#include <X11/XKBlib.h>
#include "mouse.h"
using boost::asio::ip::tcp;
using namespace std;
enum {
max_length = 1024
};
static int start_decode_video(char* host, char* port) {
OMX_VIDEO_PARAM_PORTFORMATTYPE format;
OMX_TIME_CONFIG_CLOCKSTATETYPE cstate;
COMPONENT_T *video_decode = NULL, *video_scheduler = NULL, *video_render = NULL, *clock = NULL;
COMPONENT_T * list[5];
TUNNEL_T tunnel[4];
ILCLIENT_T *client;
int status = 0;
unsigned int data_len = 0;
memset(list, 0, sizeof (list));
memset(tunnel, 0, sizeof (tunnel));
if ((client = ilclient_init()) == NULL) {
return -3;
}
if (OMX_Init() != OMX_ErrorNone) {
ilclient_destroy(client);
return -4;
}
// create video_decode
if (ilclient_create_component(client, &video_decode, "video_decode", (ILCLIENT_CREATE_FLAGS_T)(ILCLIENT_DISABLE_ALL_PORTS | ILCLIENT_ENABLE_INPUT_BUFFERS)) != 0)
status = -14;
list[0] = video_decode;
// create video_render
if (status == 0 && ilclient_create_component(client, &video_render, "video_render", ILCLIENT_DISABLE_ALL_PORTS) != 0)
status = -14;
list[1] = video_render;
// create clock
if (status == 0 && ilclient_create_component(client, &clock, "clock", ILCLIENT_DISABLE_ALL_PORTS) != 0)
status = -14;
list[2] = clock;
memset(&cstate, 0, sizeof (cstate));
cstate.nSize = sizeof (cstate);
cstate.nVersion.nVersion = OMX_VERSION;
cstate.eState = OMX_TIME_ClockStateWaitingForStartTime;
cstate.nWaitMask = 1;
if (clock != NULL && OMX_SetParameter(ILC_GET_HANDLE(clock), OMX_IndexConfigTimeClockState, &cstate) != OMX_ErrorNone)
status = -13;
// create video_scheduler
if (status == 0 && ilclient_create_component(client, &video_scheduler, "video_scheduler", ILCLIENT_DISABLE_ALL_PORTS) != 0)
status = -14;
list[3] = video_scheduler;
set_tunnel(tunnel, video_decode, 131, video_scheduler, 10);
set_tunnel(tunnel + 1, video_scheduler, 11, video_render, 90);
set_tunnel(tunnel + 2, clock, 80, video_scheduler, 12);
// setup clock tunnel first
if (status == 0 && ilclient_setup_tunnel(tunnel + 2, 0, 0) != 0)
status = -15;
else
ilclient_change_component_state(clock, OMX_StateExecuting);
if (status == 0)
ilclient_change_component_state(video_decode, OMX_StateIdle);
memset(&format, 0, sizeof (OMX_VIDEO_PARAM_PORTFORMATTYPE));
format.nSize = sizeof (OMX_VIDEO_PARAM_PORTFORMATTYPE);
format.nVersion.nVersion = OMX_VERSION;
format.nPortIndex = 130;
format.eCompressionFormat = OMX_VIDEO_CodingAVC;
if (status == 0 &&
OMX_SetParameter(ILC_GET_HANDLE(video_decode), OMX_IndexParamVideoPortFormat, &format) == OMX_ErrorNone &&
ilclient_enable_port_buffers(video_decode, 130, NULL, NULL, NULL) == 0) {
OMX_BUFFERHEADERTYPE *buf;
int port_settings_changed = 0;
int first_packet = 1;
ilclient_change_component_state(video_decode, OMX_StateExecuting);
boost::asio::io_service io_service;
tcp::resolver resolver(io_service);
tcp::resolver::query query(tcp::v4(), host, port);
tcp::resolver::iterator iterator = resolver.resolve(query);
tcp::socket s(io_service);
boost::asio::connect(s, iterator);
s.set_option(tcp::no_delay(true));
boost::asio::write(s, boost::asio::buffer("a", 2));
while ((buf = ilclient_get_input_buffer(video_decode, 130, 1)) != NULL) {
// feed data and wait until we get port settings changed
unsigned char *dest = buf->pBuffer;
int bufferSize = std::min((int)buf->nAllocLen, 10 * 1024);
data_len += boost::asio::read(s, boost::asio::buffer(dest, bufferSize));
if (port_settings_changed == 0 &&
((data_len > 0 && ilclient_remove_event(video_decode, OMX_EventPortSettingsChanged, 131, 0, 0, 1) == 0) ||
(data_len == 0 && ilclient_wait_for_event(video_decode, OMX_EventPortSettingsChanged, 131, 0, 0, 1,
ILCLIENT_EVENT_ERROR | ILCLIENT_PARAMETER_CHANGED, 10000) == 0))) {
port_settings_changed = 1;
if (ilclient_setup_tunnel(tunnel, 0, 0) != 0) {
status = -7;
break;
}
ilclient_change_component_state(video_scheduler, OMX_StateExecuting);
// now setup tunnel to video_render
if (ilclient_setup_tunnel(tunnel + 1, 0, 1000) != 0) {
status = -12;
break;
}
ilclient_change_component_state(video_render, OMX_StateExecuting);
}
if (!data_len)
break;
buf->nFilledLen = data_len;
data_len = 0;
buf->nOffset = 0;
if (first_packet) {
buf->nFlags = OMX_BUFFERFLAG_STARTTIME;
first_packet = 0;
} else
buf->nFlags = OMX_BUFFERFLAG_TIME_UNKNOWN;
if (OMX_EmptyThisBuffer(ILC_GET_HANDLE(video_decode), buf) != OMX_ErrorNone) {
status = -6;
break;
}
}
buf->nFilledLen = 0;
buf->nFlags = OMX_BUFFERFLAG_TIME_UNKNOWN | OMX_BUFFERFLAG_EOS;
if (OMX_EmptyThisBuffer(ILC_GET_HANDLE(video_decode), buf) != OMX_ErrorNone)
status = -20;
// wait for EOS from render
ilclient_wait_for_event(video_render, OMX_EventBufferFlag, 90, 0, OMX_BUFFERFLAG_EOS, 0,
ILCLIENT_BUFFER_FLAG_EOS, 10000);
// need to flush the renderer to allow video_decode to disable its input port
ilclient_flush_tunnels(tunnel, 0);
ilclient_disable_port_buffers(video_decode, 130, NULL, NULL, NULL);
}
ilclient_disable_tunnel(tunnel);
ilclient_disable_tunnel(tunnel + 1);
ilclient_disable_tunnel(tunnel + 2);
ilclient_teardown_tunnels(tunnel);
ilclient_state_transition(list, OMX_StateIdle);
ilclient_state_transition(list, OMX_StateLoaded);
ilclient_cleanup_components(list);
OMX_Deinit();
ilclient_destroy(client);
return status;
}
char *key_name[] = {
"first",
"second (or middle)",
"third"
};
struct SendStruct {
int type;
int x;
int y;
int button;
int keycode;
};
static void FillRect( void *image, int pitch, int x, int y, int w, int h, int val )
{
int row;
int col;
uint32_t *line = (uint32_t *)image + y * (pitch>>2) + x;
for ( row = 0; row < h; row++ )
{
for ( col = 0; col < w; col++ )
{
line[col] = val;
}
line += (pitch>>2);
}
}
void mouseKeyboardThread(char* host, char* port)
{
boost::asio::io_service io_service;
tcp::resolver resolver(io_service);
tcp::resolver::query query(tcp::v4(), host, port);
tcp::resolver::iterator iterator = resolver.resolve(query);
tcp::socket s(io_service);
boost::asio::connect(s, iterator);
s.set_option(tcp::no_delay(true));
boost::asio::write(s, boost::asio::buffer("b", 2));
Display *display;
XEvent xevent;
Window window;
if( (display = XOpenDisplay(NULL)) == NULL )
return;
window = DefaultRootWindow(display);
XAllowEvents(display, AsyncBoth, CurrentTime);
XGrabPointer(display,
window,
1,
PointerMotionMask | ButtonPressMask | ButtonReleaseMask ,
GrabModeAsync,
GrabModeAsync,
None,
None,
CurrentTime);
XGrabKeyboard(display, window, false, GrabModeAsync, GrabModeAsync, CurrentTime);
Mouse mouse;
while(1) {
XNextEvent(display, &xevent);
int mykey;
SendStruct send;
SendStruct* sendPtr = &send;
switch (xevent.type) {
case MotionNotify:
send.type = 0;
send.x = xevent.xmotion.x_root;
send.y = xevent.xmotion.y_root;
mouse.move(send.x, send.y);
//printf("Mouse move : [%d, %d]\n", xevent.xmotion.x_root, xevent.xmotion.y_root);
break;
case ButtonPress:
send.type = 1;
send.button = xevent.xbutton.button;
//printf("Button pressed : %s\n", key_name[xevent.xbutton.button - 1]);
break;
case ButtonRelease:
send.type = 2;
send.button = xevent.xbutton.button;
//printf("Button released : %s\n", key_name[xevent.xbutton.button - 1]);
break;
case KeyPress:
mykey = XKeycodeToKeysym(display, xevent.xkey.keycode, 0);
//printf("KeyPress : %s, %d\n", XKeysymToString(mykey), mykey);
send.type = 3;
send.keycode = mykey;
if (xevent.xkey.keycode == 27 || xevent.xkey.keycode == 9) {
return;
}
break;
case KeyRelease:
mykey = XKeycodeToKeysym(display, xevent.xkey.keycode, 0);
send.type = 4;
send.keycode = mykey;
//printf("KeyRelease : %s, %d\n", XKeysymToString(mykey), mykey);
break;
}
boost::asio::write(s, boost::asio::buffer(sendPtr, sizeof(SendStruct)));
}
mouse.close();
}
int main(int argc, char **argv) {
std::cout << "Version 0.9" << endl;
if (argc != 3)
{
std::cerr << "Usage: ./client <host> <port>\n";
return 1;
}
char* host = argv[1];
char* port = argv[2];
bcm_host_init();
boost::thread t(&mouseKeyboardThread, host, port);
start_decode_video(host, port);
t.join();
}

71
rdp-acceleraed/RPI-Client/events.cpp
View File

@ -1,71 +0,0 @@
#include <stdio.h>
#include <X11/Xlib.h>
#include <X11/XKBlib.h>
char *key_name[] = {
"first",
"second (or middle)",
"third"
};
struct SendStruct {
int type;
int x;
int y;
};
int main(int argc, char **argv)
{
Display *display;
XEvent xevent;
Window window;
if( (display = XOpenDisplay(NULL)) == NULL )
return -1;
window = DefaultRootWindow(display);
XAllowEvents(display, AsyncBoth, CurrentTime);
XGrabPointer(display,
window,
1,
PointerMotionMask | ButtonPressMask | ButtonReleaseMask ,
GrabModeAsync,
GrabModeAsync,
None,
None,
CurrentTime);
XGrabKeyboard(display, window, false, GrabModeAsync, GrabModeAsync, CurrentTime);
while(1) {
XNextEvent(display, &xevent);
int mykey;
switch (xevent.type) {
case MotionNotify:
printf("Mouse move : [%d, %d]\n", xevent.xmotion.x_root, xevent.xmotion.y_root);
break;
case ButtonPress:
printf("Button pressed : %s, %d\n", key_name[xevent.xbutton.button - 1], xevent.xbutton.button);
break;
case ButtonRelease:
printf("Button released : %s, %d\n", key_name[xevent.xbutton.button - 1], xevent.xbutton.button);
break;
case KeyPress:
mykey = XKeycodeToKeysym(display, xevent.xkey.keycode, 0);
printf("KeyPress : %s, %d\n", XKeysymToString(mykey), mykey);
if (xevent.xkey.keycode == 27 || xevent.xkey.keycode == 9) {
return 0;
}
break;
case KeyRelease:
mykey = XKeycodeToKeysym(display, xevent.xkey.keycode, 0);
printf("KeyRelease : %s, %d\n", XKeysymToString(mykey), mykey);
break;
}
}
return 0;
}

127
rdp-acceleraed/RPI-Client/mouse.h
View File

@ -1,127 +0,0 @@
#pragma once
#include "bcm_host.h"
typedef struct
{
DISPMANX_DISPLAY_HANDLE_T display;
DISPMANX_MODEINFO_T info;
void *image;
DISPMANX_UPDATE_HANDLE_T update;
DISPMANX_RESOURCE_HANDLE_T resource;
DISPMANX_ELEMENT_HANDLE_T element;
uint32_t vc_image_ptr;
} RECT_VARS_T;
static RECT_VARS_T gRectVars;
class Mouse {
public:
RECT_VARS_T *vars;
VC_IMAGE_TYPE_T type;
Mouse(){
type = VC_IMAGE_ARGB8888;
int width=6;
int height=6;
uint32_t screen = 0;
int ret;
VC_RECT_T src_rect;
VC_RECT_T dst_rect;
VC_DISPMANX_ALPHA_T alpha = { (DISPMANX_FLAGS_ALPHA_T)(DISPMANX_FLAGS_ALPHA_FROM_SOURCE | DISPMANX_FLAGS_ALPHA_FIXED_ALL_PIXELS) ,
255, //alpha 0->255
0 };
vars = &gRectVars;
bcm_host_init();
printf("Open display[%i]...\n", screen );
vars->display = vc_dispmanx_display_open( screen );
ret = vc_dispmanx_display_get_info( vars->display, &vars->info);
assert(ret == 0);
printf( "Display is %d x %d\n", vars->info.width, vars->info.height );
vars->resource = vc_dispmanx_resource_create( type,
width,
height,
&vars->vc_image_ptr );
assert( vars->resource );
vars->update = vc_dispmanx_update_start( 10 );
assert( vars->update );
vc_dispmanx_rect_set( &src_rect, 0, 0, width << 16, height << 16 );
// Full screen
vc_dispmanx_rect_set( &dst_rect, 0, 0, width, height );
vars->element = vc_dispmanx_element_add( vars->update,
vars->display,
2000, // layer
&dst_rect,
vars->resource,
&src_rect,
DISPMANX_PROTECTION_NONE,
&alpha,
NULL, // clamp
DISPMANX_NO_ROTATE );
vc_dispmanx_rect_set( &dst_rect, 0, 0, width, height);
uint16_t *image = (uint16_t *)calloc( 1, width*4*height );
memset(image, 0xFF, width*4*height);
ret = vc_dispmanx_resource_write_data( vars->resource,
type,
width*4,//image.step,
image,
&dst_rect );
ret = vc_dispmanx_update_submit_sync( vars->update );
assert( ret == 0 );
}
void move(int x, int y){
int ret;
VC_RECT_T dst_rect;
vars->update = vc_dispmanx_update_start( 10 );
vc_dispmanx_rect_set( &dst_rect, x, y, 6, 6);
ret = vc_dispmanx_element_change_attributes(
vars->update,
vars->element,
/*ELEMENT_CHANGE_DEST_RECT*/ (1<<2),
0,
0,
&dst_rect,
NULL,
DISPMANX_NO_HANDLE,
DISPMANX_NO_ROTATE);
assert( ret == DISPMANX_SUCCESS );
/* Submit asynchronously, otherwise the performance suffers a lot */
ret = vc_dispmanx_update_submit( vars->update, 0, NULL );
assert( ret == DISPMANX_SUCCESS );
}
void close(){
int ret;
vars->update = vc_dispmanx_update_start( 10 );
assert( vars->update );
ret = vc_dispmanx_element_remove( vars->update, vars->element );
assert( ret == 0 );
ret = vc_dispmanx_update_submit_sync( vars->update );
assert( ret == 0 );
ret = vc_dispmanx_resource_delete( vars->resource );
assert( ret == 0 );
ret = vc_dispmanx_display_close( vars->display );
assert( ret == 0 );
}
};

121
rdp-acceleraed/Server/CMakeLists.txt
View File

@ -1,121 +0,0 @@
cmake_minimum_required(VERSION 2.8)
set(CMAKE_MODULE_PATH "${CMAKE_MODULE_PATH};${CMAKE_CURRENT_SOURCE_DIR}")
project( server )
include_directories(${CMAKE_CURRENT_SOURCE_DIR})
SET(USE_CUDA on CACHE BOOL "Use CUDA")
SET(USE_WDDM on CACHE BOOL "Use WDDM for screen capture")
SET(USE_NVENC on CACHE BOOL "Use Nvidia encoder")
# BOOST
set(Boost_USE_STATIC_LIBS ON)
set(Boost_USE_MULTITHREADED ON)
find_package( Boost REQUIRED COMPONENTS thread )
if(Boost_FOUND)
message("Boost found!")
endif()
include_directories(${Boost_INCLUDE_DIR})
LINK_DIRECTORIES(${Boost_LIBRARY_DIRS})
# FFMPEG
set(FFMPEG_ROOT "" CACHE FILEPATH "Root of the FFMPEG directory, which has README.txt")
if (FFMPEG_ROOT)
FIND_PATH( FFMPEG_INCLUDE_DIR libavcodec/avcodec.h
${FFMPEG_ROOT}/include
)
include_directories(${FFMPEG_INCLUDE_DIR})
FIND_LIBRARY( FFMPEG_LIBRARY_avcodec avcodec
${FFMPEG_ROOT}/lib
)
FIND_LIBRARY( FFMPEG_LIBRARY_avutil avutil
${FFMPEG_ROOT}/lib
)
if (FFMPEG_LIBRARY_avcodec AND FFMPEG_LIBRARY_avutil)
set (FFMPEG_FOUND 1)
set (FFMPEG_LIBRARIES "${FFMPEG_LIBRARY_avcodec};${FFMPEG_LIBRARY_avutil}")
message("FFMPEG found!")
endif()
endif()
# DXGI and CUDA
if (USE_CUDA)
find_package(CUDA)
endif()
if(CUDA_FOUND)
set (HAS_CUDA 1)
message("CUDA found!")
include_directories(${CUDA_TOOLKIT_INCLUDE})
CUDA_ADD_LIBRARY(cudalib STATIC
color_conversion.h
color_conversion.cu
OPTIONS -arch sm_30
)
TARGET_LINK_LIBRARIES(cudalib ${CUDA_LIBRARIES})
set (CUDA_LINK_LIBRARIES "${CUDA_CUDA_LIBRARY};${CUDA_CUDART_LIBRARY};cudalib")
endif()
if (USE_WDDM OR USE_NVENC)
find_package( DirectX )
endif()
include_directories(${DXGI_INCLUDES})
include_directories(${Boost_INCLUDE_DIRS})
if (USE_WDDM AND DIRECTX_FOUND)
set (HAS_WDDM 1)
SET(Capture_HEADER
wddm.h
WDDMCapture.h
)
SET(Capture_LIBRARIES
"${DXGI_LIBRARIES}"
)
else()
SET(Capture_HEADER
GDICapture.h
)
endif()
if (DIRECTX_FOUND AND USE_NVENC)
set (HAS_NVENC 1)
#files for NVEncoder
SET(ENCODER_SOURCE
NvEncoder/NvHWEncoder.cpp
)
SET(ENCODER_HEADERS
NV_encoding.hpp
NvEncoder/NvEncoder.h
NvEncoder/NvHWEncoder.h
NvEncoder/nvEncodeAPI.h
)
elseif (FFMPEG_FOUND)
set (HAS_FFMPEG 1)
SET(ENCODER_SOURCE
)
SET(ENCODER_HEADERS
FFMPEG_encoding.hpp
)
SET(ENCODER_LIBRARIES
"${FFMPEG_LIBRARIES}"
)
endif()
SET(COMMON_SOURCE
config.h
bounded_buffer.h
Capture.h
fps.h
monitor.h
params.h
)
add_executable( server server.cpp ${COMMON_SOURCE} ${ENCODER_SOURCE} ${ENCODER_HEADERS} ${Capture_HEADER} )
target_link_libraries( server ${Boost_LIBRARIES} ${ENCODER_LIBRARIES} ${Capture_LIBRARIES} ${CUDA_LINK_LIBRARIES})
CONFIGURE_FILE(${CMAKE_CURRENT_SOURCE_DIR}/config.h.in ${CMAKE_CURRENT_SOURCE_DIR}/config.h)

8
rdp-acceleraed/Server/Capture.h
View File

@ -1,8 +0,0 @@
#pragma once
class Capture {
public:
virtual void init(UINT monitorID, RECT screen) = 0;
virtual int getNextFrame(RGBQUAD**) = 0;
virtual void doneNextFrame() = 0;
};

194
rdp-acceleraed/Server/FFMPEG_encoding.hpp
View File

@ -1,194 +0,0 @@
/*
* Copyright (c) 2001 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include <math.h>
#define __STDC_CONSTANT_MACROS
extern "C" {
#include <libavutil/opt.h>
#include <libavcodec/avcodec.h>
#include <libavutil/channel_layout.h>
#include <libavutil/common.h>
#include <libavutil/imgutils.h>
#include <libavutil/mathematics.h>
#include <libavutil/samplefmt.h>
};
using namespace boost::asio;
using ip::tcp;
typedef boost::shared_ptr<tcp::socket> socket_ptr;
uint8_t endcode[] = { 0, 0, 1, 0xb7 };
class FFMPEG_encoding {
public:
void load(int width, int height, socket_ptr sock) {
this->sock = sock;
c = NULL;
codec_id = AV_CODEC_ID_H264;
i=0;
avcodec_register_all();
/* find the mpeg1 video encoder */
codec = avcodec_find_encoder(codec_id);
if (!codec) {
fprintf(stderr, "Codec not found\n");
exit(1);
}
c = avcodec_alloc_context3(codec);
if (!c) {
fprintf(stderr, "Could not allocate video codec context\n");
exit(1);
}
/* put sample parameters */
c->bit_rate = 400000;
/* resolution must be a multiple of two */
c->width = width;
c->height = height;
/* frames per second */
AVRational r;
r.den=1;
r.num=25;
c->time_base = r;
/* emit one intra frame every ten frames
* check frame pict_type before passing frame
* to encoder, if frame->pict_type is AV_PICTURE_TYPE_I
* then gop_size is ignored and the output of encoder
* will always be I frame irrespective to gop_size
*/
c->gop_size = 10;
c->max_b_frames = 0;
c->refs = 0;
c->pix_fmt = AV_PIX_FMT_YUV420P;//AV_PIX_FMT_YUV444P;
// ultrafast,superfast, veryfast, faster, fast, medium, slow, slower, veryslow
if (codec_id == AV_CODEC_ID_H264) {
av_opt_set(c->priv_data, "preset", "veryfast", 0);
av_opt_set(c->priv_data, "tune", "zerolatency", 0);
av_opt_set(c->priv_data, "movflags", "faststart", 0);
}
/* open it */
if (avcodec_open2(c, codec, NULL) < 0) {
fprintf(stderr, "Could not open codec\n");
exit(1);
}
frame = av_frame_alloc();
if (!frame) {
fprintf(stderr, "Could not allocate video frame\n");
exit(1);
}
frame->format = c->pix_fmt;
frame->width = c->width;
frame->height = c->height;
/* the image can be allocated by any means and av_image_alloc() is
* just the most convenient way if av_malloc() is to be used */
int ret = av_image_alloc(frame->data, frame->linesize, c->width, c->height,
c->pix_fmt, 32);
if (ret < 0) {
fprintf(stderr, "Could not allocate raw picture buffer\n");
exit(1);
}
}
void write(int width, int height, RGBQUAD *pPixels) {
av_init_packet(&pkt);
pkt.data = NULL; // packet data will be allocated by the encoder
pkt.size = 0;
fflush(stdout);
for (int y = 0; y < c->height; y++) {
for (int x = 0; x < c->width; x++) {
RGBQUAD px = pPixels[y*width+x];
int Y = ( ( 66 * px.rgbRed + 129 * px.rgbGreen + 25 * px.rgbBlue + 128) >> 8) + 16;
int U = ( ( -38 * px.rgbRed - 74 * px.rgbGreen + 112 * px.rgbBlue + 128) >> 8) + 128;
int V = ( ( 112 * px.rgbRed - 94 * px.rgbGreen - 18 * px.rgbBlue + 128) >> 8) + 128;
frame->data[0][y * frame->linesize[0] + x] = Y;
//frame->data[1][y * frame->linesize[0] + x] = U;
//frame->data[2][y * frame->linesize[0] + x] = V;
frame->data[1][(y >> 1) * frame->linesize[1] + (x >> 1)] = U;
frame->data[2][(y >> 1) * frame->linesize[2] + (x >> 1)] = V;
}
}
frame->pts = i;
i++;
/* encode the image */
int got_output;
int ret = avcodec_encode_video2(c, &pkt, frame, &got_output);
if (ret < 0) {
fprintf(stderr, "Error encoding frame\n");
exit(1);
}
if (got_output) {
printf("Write frame (size=%5d)\n", pkt.size);
//fwrite(pkt.data, 1, pkt.size, f);
boost::asio::write(*sock, buffer((char*)pkt.data, pkt.size));
av_free_packet(&pkt);
}
}
void close () {
/* get the delayed frames */
/*for (got_output = 1; got_output; i++) {
fflush(stdout);
int ret = avcodec_encode_video2(c, &pkt, NULL, &got_output);
if (ret < 0) {
fprintf(stderr, "Error encoding frame\n");
exit(1);
}
if (got_output) {
printf("Write frame %3d (size=%5d)\n", i, pkt.size);
fwrite(pkt.data, 1, pkt.size, f);
av_free_packet(&pkt);
}
}*/
/* add sequence end code to have a real mpeg file */
//fwrite(endcode, 1, sizeof(endcode), f);
//fclose(f);
avcodec_close(c);
av_free(c);
av_freep(&frame->data[0]);
av_frame_free(&frame);
}
private:
AVCodecID codec_id;
AVCodec *codec;
AVCodecContext *c;
AVFrame *frame;
AVPacket pkt;
socket_ptr sock;
int i;
};

31
rdp-acceleraed/Server/FindDirectX.cmake
View File

@ -1,31 +0,0 @@
FIND_PATH( DXGI_INCLUDE dxgi1_2.h
"C:/Program Files (x86)/Windows Kits/10/Include/10.0.17763.0/shared"
"C:/Program Files (x86)/Windows Kits/10/Include/10.0.17134.0/shared"
"C:/Program Files (x86)/Windows Kits/8.1/Include/shared"
"C:/Program Files (x86)/Windows Kits/8.0/Include/shared"
"C:/Program Files/Windows Kits/8.1/Include/shared"
"C:/Program Files/Windows Kits/8.0/Include/shared"
)
FIND_LIBRARY( DXGI_LIBRARY1 d3d11
"C:/Program Files (x86)/Windows Kits/10/Lib/10.0.17763.0/um/x64"
"C:/Program Files (x86)/Windows Kits/10/Lib/10.0.17134.0/um/x64"
"C:/Program Files (x86)/Windows Kits/8.1/Lib/winv6.3/um/x86"
"C:/Program Files (x86)/Windows Kits/8.0/Lib/winv6.3/um/x86"
"C:/Program Files/Windows Kits/8.1/Lib/winv6.3/um/x86"
"C:/Program Files/Windows Kits/8.0/Lib/winv6.3/um/x86"
)
FIND_LIBRARY( DXGI_LIBRARY2 Dxgi
"C:/Program Files (x86)/Windows Kits/10/Lib/10.0.17763.0/um/x64"
"C:/Program Files (x86)/Windows Kits/10/Lib/10.0.17134.0/um/x64"
"C:/Program Files (x86)/Windows Kits/8.1/Lib/winv6.3/um/x86"
"C:/Program Files (x86)/Windows Kits/8.0/Lib/winv6.3/um/x86"
"C:/Program Files/Windows Kits/8.1/Lib/winv6.3/um/x86"
"C:/Program Files/Windows Kits/8.0/Lib/winv6.3/um/x86"
)
if (DXGI_INCLUDE AND DXGI_LIBRARY1 AND DXGI_LIBRARY2 )
set (DIRECTX_FOUND 1)
set (DXGI_INCLUDES "${DXGI_INCLUDE}")
set (DXGI_LIBRARIES "${DXGI_LIBRARY1};${DXGI_LIBRARY2}")
message("DIRECTX found!")
endif()

63
rdp-acceleraed/Server/GDICapture.h
View File

@ -1,63 +0,0 @@
#pragma once
#include "Capture.h"
class GDICapture : public Capture {
public:
void init(UINT monitorID, RECT screen)
{
this->screen = screen;
hdc = GetDC(NULL); // get the desktop device context
hDest = CreateCompatibleDC(hdc); // create a device context to use yourself
// get the height and width of the screen
height = screen.bottom - screen.top;
width = screen.right - screen.left;
int virtualScreenHeight = GetSystemMetrics(SM_CYVIRTUALSCREEN);
int virtualScreenWidth = GetSystemMetrics(SM_CXVIRTUALSCREEN);
// create a bitmap
hbDesktop = CreateCompatibleBitmap( hdc, virtualScreenWidth, virtualScreenHeight);
// use the previously created device context with the bitmap
SelectObject(hDest, hbDesktop);
bmi.bmiHeader.biSize = sizeof(bmi.bmiHeader);
bmi.bmiHeader.biWidth = width;
bmi.bmiHeader.biHeight = -height;
bmi.bmiHeader.biPlanes = 1;
bmi.bmiHeader.biBitCount = 32;
bmi.bmiHeader.biCompression = BI_RGB;
pPixels = new RGBQUAD[width * height];
}
int getNextFrame(RGBQUAD** data)
{
// copy from the desktop device context to the bitmap device context
BitBlt( hDest, 0,0, width, height, hdc, screen.left, screen.top, SRCCOPY);
GetDIBits(
hDest,
hbDesktop,
0,
height,
pPixels,
&bmi,
DIB_RGB_COLORS
);
*data = pPixels;
return 0;
}
void doneNextFrame()
{
}
private:
HDC hdc, hDest;
int width, height;
RECT screen;
RGBQUAD *pPixels;
HBITMAP hbDesktop;
BITMAPINFO bmi;
};

100
rdp-acceleraed/Server/NV_encoding.hpp
View File

@ -1,100 +0,0 @@
using namespace boost::asio;
using ip::tcp;
typedef boost::shared_ptr<tcp::socket> socket_ptr;
#include "NvEncoder/NvEncoder.h"
#include "color_conversion.h"
class NV_encoding {
public:
void load(int width, int height, socket_ptr sock, UINT monitorID) {
NVENCSTATUS nvStatus = NV_ENC_SUCCESS;
this->sock = sock;
this->width = width;
this->height = height;
cNvEncoder = new CNvEncoder();
cNvEncoder->InitCuda();
nvStatus = cNvEncoder->Initialize(NV_ENC_DEVICE_TYPE_CUDA);
nvStatus = cNvEncoder->CreateEncoder(width, height);
nvStatus = cNvEncoder->AllocateIOBuffers(width, height, false);
dataPacket = new DataPacket();
dataPacket->data = new uint8_t[width*height];
yuv[0] = new uint8_t[width*height];
yuv[1] = new uint8_t[width*height / 4];
yuv[2] = new uint8_t[width*height / 4];
// Init avi file
//char buffer[255];
//sprintf(buffer, "C:\\Monitor%d.avi", monitorID);
//ofs.open(buffer, std::ofstream::out | std::ofstream::binary);
}
void write(int width, int height, RGBQUAD *pPixels) {
bool rc = RGB_to_YV12(width, height, pPixels, yuv[0], yuv[1], yuv[2]);
if (!rc){
// The Cuda function RGB_to_YV12 failed, do CPU conversion
for (int y = 0; y < height; y++) {
for (int x = 0; x < width; x++) {
RGBQUAD px = pPixels[y*width+x];
int Y = ( ( 66 * px.rgbRed + 129 * px.rgbGreen + 25 * px.rgbBlue + 128) >> 8) + 16;
int U = ( ( -38 * px.rgbRed - 74 * px.rgbGreen + 112 * px.rgbBlue + 128) >> 8) + 128;
int V = ( ( 112 * px.rgbRed - 94 * px.rgbGreen - 18 * px.rgbBlue + 128) >> 8) + 128;
yuv[0][y * width + x] = Y;
yuv[1][(y >> 1) * (width >> 1) + (x >> 1)] = U;
yuv[2][(y >> 1) * (width >> 1) + (x >> 1)] = V;
}
}
}
EncodeFrameConfig stEncodeFrame;
memset(&stEncodeFrame, 0, sizeof(stEncodeFrame));
stEncodeFrame.yuv[0] = yuv[0];
stEncodeFrame.yuv[1] = yuv[1];
stEncodeFrame.yuv[2] = yuv[2];
stEncodeFrame.stride[0] = width;
stEncodeFrame.stride[1] = width/2;
stEncodeFrame.stride[2] = width/2;
stEncodeFrame.width = width;
stEncodeFrame.height = height;
cNvEncoder->EncodeFrame(&stEncodeFrame, dataPacket, false, width, height);
if (dataPacket->size > 0) {
printf("Write frame (size=%5d)\n", dataPacket->size);
//ofs.write((char*)dataPacket->data, dataPacket->size);
boost::asio::write(*sock, buffer((char*)dataPacket->data, dataPacket->size));
}
}
void close () {
delete cNvEncoder;
delete dataPacket->data;
delete dataPacket;
for (int i = 0; i < 3; i ++)
{
if (yuv[i])
{
delete [] yuv[i];
}
}
}
private:
int width;
int height;
socket_ptr sock;
uint8_t *yuv[3];
CNvEncoder* cNvEncoder;
DataPacket* dataPacket;
//std::ofstream ofs;
};

503
rdp-acceleraed/Server/NvEncoder/NvEncoder.h
View File

@ -1,503 +0,0 @@
////////////////////////////////////////////////////////////////////////////
//
// Copyright 1993-2014 NVIDIA Corporation. All rights reserved.
//
// Please refer to the NVIDIA end user license agreement (EULA) associated
// with this source code for terms and conditions that govern your use of
// this software. Any use, reproduction, disclosure, or distribution of
// this software and related documentation outside the terms of the EULA
// is strictly prohibited.
//
////////////////////////////////////////////////////////////////////////////
#if defined(NV_WINDOWS)
#include <d3d9.h>
#include <d3d10_1.h>
#include <d3d11.h>
#pragma warning(disable : 4996)
#endif
//#pragma comment (lib, "cuda.lib")
#pragma comment (lib, "d3d9.lib")
#pragma comment (lib, "d3d10.lib")
#pragma comment (lib, "d3d11.lib")
#include "NvHWEncoder.h"
#include "nvEncodeAPI.h"
#include "nvUtils.h"
#define MAX_ENCODE_QUEUE 32
#define BITSTREAM_BUFFER_SIZE 2 * 1024 * 1024
#define SET_VER(configStruct, type) {configStruct.version = type##_VER;}
template<class T>
class CNvQueue {
T** m_pBuffer;
unsigned int m_uSize;
unsigned int m_uPendingCount;
unsigned int m_uAvailableIdx;
unsigned int m_uPendingndex;
public:
CNvQueue(): m_pBuffer(NULL), m_uSize(0), m_uPendingCount(0), m_uAvailableIdx(0),
m_uPendingndex(0)
{
}
~CNvQueue()
{
delete[] m_pBuffer;
}
bool Initialize(T *pItems, unsigned int uSize)
{
m_uSize = uSize;
m_uPendingCount = 0;
m_uAvailableIdx = 0;
m_uPendingndex = 0;
m_pBuffer = new T *[m_uSize];
for (unsigned int i = 0; i < m_uSize; i++)
{
m_pBuffer[i] = &pItems[i];
}
return true;
}
T * GetAvailable()
{
T *pItem = NULL;
if (m_uPendingCount == m_uSize)
{
return NULL;
}
pItem = m_pBuffer[m_uAvailableIdx];
m_uAvailableIdx = (m_uAvailableIdx+1)%m_uSize;
m_uPendingCount += 1;
return pItem;
}
T* GetPending()
{
if (m_uPendingCount == 0)
{
return NULL;
}
T *pItem = m_pBuffer[m_uPendingndex];
m_uPendingndex = (m_uPendingndex+1)%m_uSize;
m_uPendingCount -= 1;
return pItem;
}
};
typedef struct _EncodeFrameConfig
{
uint8_t *yuv[3];
uint32_t stride[3];
uint32_t width;
uint32_t height;
}EncodeFrameConfig;
typedef enum
{
NV_ENC_DX9 = 0,
NV_ENC_DX11 = 1,
NV_ENC_CUDA = 2,
NV_ENC_DX10 = 3,
} NvEncodeDeviceType;
class CNvEncoder
{
public:
CNvEncoder()
{
m_pNvHWEncoder = new CNvHWEncoder;
m_pDevice = NULL;
#if defined (NV_WINDOWS)
m_pD3D = NULL;
#endif
m_cuContext = NULL;
m_uEncodeBufferCount = 0;
memset(&m_stEncoderInput, 0, sizeof(m_stEncoderInput));
memset(&m_stEOSOutputBfr, 0, sizeof(m_stEOSOutputBfr));
memset(&m_stEncodeBuffer, 0, sizeof(m_stEncodeBuffer));
}
~CNvEncoder()
{
if (m_pNvHWEncoder)
{
delete m_pNvHWEncoder;
m_pNvHWEncoder = NULL;
}
}
NVENCSTATUS InitCuda(uint32_t deviceID = 0)
{
CUresult cuResult;
CUdevice device;
CUcontext cuContextCurr;
int deviceCount = 0;
int SMminor = 0, SMmajor = 0;
cuResult = cuInit(0);
if (cuResult != CUDA_SUCCESS)
{
PRINTERR("cuInit error:0x%x\n", cuResult);
assert(0);
return NV_ENC_ERR_NO_ENCODE_DEVICE;
}
cuResult = cuDeviceGetCount(&deviceCount);
if (cuResult != CUDA_SUCCESS)
{
PRINTERR("cuDeviceGetCount error:0x%x\n", cuResult);
assert(0);
return NV_ENC_ERR_NO_ENCODE_DEVICE;
}
// If dev is negative value, we clamp to 0
if ((int)deviceID < 0)
deviceID = 0;
if (deviceID >(unsigned int)deviceCount - 1)
{
PRINTERR("Invalid Device Id = %d\n", deviceID);
return NV_ENC_ERR_INVALID_ENCODERDEVICE;
}
cuResult = cuDeviceGet(&device, deviceID);
if (cuResult != CUDA_SUCCESS)
{
PRINTERR("cuDeviceGet error:0x%x\n", cuResult);
return NV_ENC_ERR_NO_ENCODE_DEVICE;
}
cuResult = cuDeviceComputeCapability(&SMmajor, &SMminor, deviceID);
if (cuResult != CUDA_SUCCESS)
{
PRINTERR("cuDeviceComputeCapability error:0x%x\n", cuResult);
return NV_ENC_ERR_NO_ENCODE_DEVICE;
}
if (((SMmajor << 4) + SMminor) < 0x30)
{
PRINTERR("GPU %d does not have NVENC capabilities exiting\n", deviceID);
return NV_ENC_ERR_NO_ENCODE_DEVICE;
}
cuResult = cuCtxCreate((CUcontext*)(&m_pDevice), 0, device);
if (cuResult != CUDA_SUCCESS)
{
PRINTERR("cuCtxCreate error:0x%x\n", cuResult);
assert(0);
return NV_ENC_ERR_NO_ENCODE_DEVICE;
}
cuResult = cuCtxPopCurrent(&cuContextCurr);
if (cuResult != CUDA_SUCCESS)
{
PRINTERR("cuCtxPopCurrent error:0x%x\n", cuResult);
assert(0);
return NV_ENC_ERR_NO_ENCODE_DEVICE;
}
return NV_ENC_SUCCESS;
}
NVENCSTATUS Initialize(NV_ENC_DEVICE_TYPE deviceType) {
NVENCSTATUS nvStatus = m_pNvHWEncoder->Initialize(m_pDevice, deviceType);
return nvStatus;
}
NVENCSTATUS CreateEncoder(int width, int height){
EncodeConfig encodeConfig;
memset(&encodeConfig, 0, sizeof(EncodeConfig));
encodeConfig.width = width;
encodeConfig.height = height;
// B = Encoding bitrate
int B = 1000 * 1024; // kbps
int fps = 20;
uint32_t maxFrameSize = B / fps; // bandwidth / frame rate
encodeConfig.vbvSize = maxFrameSize;
encodeConfig.endFrameIdx = INT_MAX;
encodeConfig.bitrate = encodeConfig.vbvSize * fps;
encodeConfig.vbvMaxBitrate = encodeConfig.vbvSize * fps;
encodeConfig.rcMode = NV_ENC_PARAMS_RC_VBR;//NV_ENC_PARAMS_RC_CONSTQP;
encodeConfig.gopLength = 200;//NVENC_INFINITE_GOPLENGTH;
encodeConfig.deviceType = NV_ENC_CUDA;
encodeConfig.codec = NV_ENC_H264;
encodeConfig.fps = fps;
encodeConfig.qp = 28;
encodeConfig.presetGUID = NV_ENC_PRESET_LOW_LATENCY_HQ_GUID;//NV_ENC_PRESET_LOW_LATENCY_HQ_GUID;//NV_ENC_PRESET_DEFAULT_GUID;
encodeConfig.pictureStruct = NV_ENC_PIC_STRUCT_FRAME;
encodeConfig.isYuv444 = 0;
encodeConfig.presetGUID = m_pNvHWEncoder->GetPresetGUID(encodeConfig.encoderPreset, encodeConfig.codec);
printf("Encoding input : \"%s\"\n", encodeConfig.inputFileName);
printf(" output : \"%s\"\n", encodeConfig.outputFileName);
printf(" codec : \"%s\"\n", encodeConfig.codec == NV_ENC_HEVC ? "HEVC" : "H264");
printf(" size : %dx%d\n", encodeConfig.width, encodeConfig.height);
printf(" bitrate : %d bits/sec\n", encodeConfig.bitrate);
printf(" vbvMaxBitrate : %d bits/sec\n", encodeConfig.vbvMaxBitrate);
printf(" vbvSize : %d bits\n", encodeConfig.vbvSize);
printf(" fps : %d frames/sec\n", encodeConfig.fps);
printf(" rcMode : %s\n", encodeConfig.rcMode == NV_ENC_PARAMS_RC_CONSTQP ? "CONSTQP" :
encodeConfig.rcMode == NV_ENC_PARAMS_RC_VBR ? "VBR" :
encodeConfig.rcMode == NV_ENC_PARAMS_RC_CBR ? "CBR" :
encodeConfig.rcMode == NV_ENC_PARAMS_RC_VBR_MINQP ? "VBR MINQP" :
encodeConfig.rcMode == NV_ENC_PARAMS_RC_2_PASS_QUALITY ? "TWO_PASS_QUALITY" :
encodeConfig.rcMode == NV_ENC_PARAMS_RC_2_PASS_FRAMESIZE_CAP ? "TWO_PASS_FRAMESIZE_CAP" :
encodeConfig.rcMode == NV_ENC_PARAMS_RC_2_PASS_VBR ? "TWO_PASS_VBR" : "UNKNOWN");
if (encodeConfig.gopLength == NVENC_INFINITE_GOPLENGTH)
printf(" goplength : INFINITE GOP \n");
else
printf(" goplength : %d \n", encodeConfig.gopLength);
printf(" B frames : %d \n", encodeConfig.numB);
printf(" QP : %d \n", encodeConfig.qp);
printf(" Input Format : %s\n", encodeConfig.isYuv444 ? "YUV 444" : "YUV 420");
printf(" preset : %s\n", (encodeConfig.presetGUID == NV_ENC_PRESET_LOW_LATENCY_HQ_GUID) ? "LOW_LATENCY_HQ" :
(encodeConfig.presetGUID == NV_ENC_PRESET_LOW_LATENCY_HP_GUID) ? "LOW_LATENCY_HP" :
(encodeConfig.presetGUID == NV_ENC_PRESET_HQ_GUID) ? "HQ_PRESET" :
(encodeConfig.presetGUID == NV_ENC_PRESET_HP_GUID) ? "HP_PRESET" :
(encodeConfig.presetGUID == NV_ENC_PRESET_LOSSLESS_HP_GUID) ? "LOSSLESS_HP" : "LOW_LATENCY_DEFAULT");
printf(" Picture Structure : %s\n", (encodeConfig.pictureStruct == NV_ENC_PIC_STRUCT_FRAME) ? "Frame Mode" :
(encodeConfig.pictureStruct == NV_ENC_PIC_STRUCT_FIELD_TOP_BOTTOM) ? "Top Field first" :
(encodeConfig.pictureStruct == NV_ENC_PIC_STRUCT_FIELD_BOTTOM_TOP) ? "Bottom Field first" : "INVALID");
printf(" devicetype : %s\n", encodeConfig.deviceType == NV_ENC_DX9 ? "DX9" :
encodeConfig.deviceType == NV_ENC_DX10 ? "DX10" :
encodeConfig.deviceType == NV_ENC_DX11 ? "DX11" :
encodeConfig.deviceType == NV_ENC_CUDA ? "CUDA" : "INVALID");
printf("\n");
NVENCSTATUS nvStatus = m_pNvHWEncoder->CreateEncoder(&encodeConfig);
m_uEncodeBufferCount = encodeConfig.numB + 1; // min buffers is numb + 1 + 3 pipelining
m_uPicStruct = encodeConfig.pictureStruct;
return nvStatus;
}
NVENCSTATUS EncodeFrame(EncodeFrameConfig *pEncodeFrame, DataPacket* dataPacket, bool bFlush=false, uint32_t width=0, uint32_t height=0) {
NVENCSTATUS nvStatus = NV_ENC_SUCCESS;
uint32_t lockedPitch = 0;
EncodeBuffer *pEncodeBuffer = NULL;
if (bFlush)
{
FlushEncoder(dataPacket);
return NV_ENC_SUCCESS;
}
if (!pEncodeFrame)
{
return NV_ENC_ERR_INVALID_PARAM;
}
pEncodeBuffer = m_EncodeBufferQueue.GetAvailable();
if(!pEncodeBuffer)
{
m_pNvHWEncoder->ProcessOutput(m_EncodeBufferQueue.GetPending(), dataPacket);
pEncodeBuffer = m_EncodeBufferQueue.GetAvailable();
}
unsigned char *pInputSurface;
nvStatus = m_pNvHWEncoder->NvEncLockInputBuffer(pEncodeBuffer->stInputBfr.hInputSurface, (void**)&pInputSurface, &lockedPitch);
if (nvStatus != NV_ENC_SUCCESS)
return nvStatus;
if (pEncodeBuffer->stInputBfr.bufferFmt == NV_ENC_BUFFER_FORMAT_NV12_PL)
{
unsigned char *pInputSurfaceCh = pInputSurface + (pEncodeBuffer->stInputBfr.dwHeight*lockedPitch);
convertYUVpitchtoNV12(pEncodeFrame->yuv[0], pEncodeFrame->yuv[1], pEncodeFrame->yuv[2], pInputSurface, pInputSurfaceCh, width, height, width, lockedPitch);
}
else
{
unsigned char *pInputSurfaceCb = pInputSurface + (pEncodeBuffer->stInputBfr.dwHeight * lockedPitch);
unsigned char *pInputSurfaceCr = pInputSurfaceCb + (pEncodeBuffer->stInputBfr.dwHeight * lockedPitch);
convertYUVpitchtoYUV444(pEncodeFrame->yuv[0], pEncodeFrame->yuv[1], pEncodeFrame->yuv[2], pInputSurface, pInputSurfaceCb, pInputSurfaceCr, width, height, width, lockedPitch);
}
nvStatus = m_pNvHWEncoder->NvEncUnlockInputBuffer(pEncodeBuffer->stInputBfr.hInputSurface);
if (nvStatus != NV_ENC_SUCCESS)
return nvStatus;
nvStatus = m_pNvHWEncoder->NvEncEncodeFrame(pEncodeBuffer, NULL, width, height, (NV_ENC_PIC_STRUCT)m_uPicStruct);
return nvStatus;
}
NVENCSTATUS AllocateIOBuffers(uint32_t uInputWidth, uint32_t uInputHeight, uint32_t isYuv444)
{
NVENCSTATUS nvStatus = NV_ENC_SUCCESS;
m_EncodeBufferQueue.Initialize(m_stEncodeBuffer, m_uEncodeBufferCount);
for (uint32_t i = 0; i < m_uEncodeBufferCount; i++)
{
nvStatus = m_pNvHWEncoder->NvEncCreateInputBuffer(uInputWidth, uInputHeight, &m_stEncodeBuffer[i].stInputBfr.hInputSurface, isYuv444);
if (nvStatus != NV_ENC_SUCCESS)
return nvStatus;
m_stEncodeBuffer[i].stInputBfr.bufferFmt = isYuv444 ? NV_ENC_BUFFER_FORMAT_YUV444_PL : NV_ENC_BUFFER_FORMAT_NV12_PL;
m_stEncodeBuffer[i].stInputBfr.dwWidth = uInputWidth;
m_stEncodeBuffer[i].stInputBfr.dwHeight = uInputHeight;
nvStatus = m_pNvHWEncoder->NvEncCreateBitstreamBuffer(BITSTREAM_BUFFER_SIZE, &m_stEncodeBuffer[i].stOutputBfr.hBitstreamBuffer);
if (nvStatus != NV_ENC_SUCCESS)
return nvStatus;
m_stEncodeBuffer[i].stOutputBfr.dwBitstreamBufferSize = BITSTREAM_BUFFER_SIZE;
#if defined (NV_WINDOWS)
nvStatus = m_pNvHWEncoder->NvEncRegisterAsyncEvent(&m_stEncodeBuffer[i].stOutputBfr.hOutputEvent);
if (nvStatus != NV_ENC_SUCCESS)
return nvStatus;
m_stEncodeBuffer[i].stOutputBfr.bWaitOnEvent = true;
#else
m_stEncodeBuffer[i].stOutputBfr.hOutputEvent = NULL;
#endif
}
m_stEOSOutputBfr.bEOSFlag = TRUE;
#if defined (NV_WINDOWS)
nvStatus = m_pNvHWEncoder->NvEncRegisterAsyncEvent(&m_stEOSOutputBfr.hOutputEvent);
if (nvStatus != NV_ENC_SUCCESS)
return nvStatus;
#else
m_stEOSOutputBfr.hOutputEvent = NULL;
#endif
return NV_ENC_SUCCESS;
}
NVENCSTATUS ReleaseIOBuffers()
{
for (uint32_t i = 0; i < m_uEncodeBufferCount; i++)
{
m_pNvHWEncoder->NvEncDestroyInputBuffer(m_stEncodeBuffer[i].stInputBfr.hInputSurface);
m_stEncodeBuffer[i].stInputBfr.hInputSurface = NULL;
m_pNvHWEncoder->NvEncDestroyBitstreamBuffer(m_stEncodeBuffer[i].stOutputBfr.hBitstreamBuffer);
m_stEncodeBuffer[i].stOutputBfr.hBitstreamBuffer = NULL;
#if defined(NV_WINDOWS)
m_pNvHWEncoder->NvEncUnregisterAsyncEvent(m_stEncodeBuffer[i].stOutputBfr.hOutputEvent);
nvCloseFile(m_stEncodeBuffer[i].stOutputBfr.hOutputEvent);
m_stEncodeBuffer[i].stOutputBfr.hOutputEvent = NULL;
#endif
}
if (m_stEOSOutputBfr.hOutputEvent)
{
#if defined(NV_WINDOWS)
m_pNvHWEncoder->NvEncUnregisterAsyncEvent(m_stEOSOutputBfr.hOutputEvent);
nvCloseFile(m_stEOSOutputBfr.hOutputEvent);
m_stEOSOutputBfr.hOutputEvent = NULL;
#endif
}
return NV_ENC_SUCCESS;
}
protected:
CNvHWEncoder *m_pNvHWEncoder;
uint32_t m_uEncodeBufferCount;
uint32_t m_uPicStruct;
void* m_pDevice;
#if defined(NV_WINDOWS)
IDirect3D9 *m_pD3D;
#endif
CUcontext m_cuContext;
EncodeConfig m_stEncoderInput;
EncodeBuffer m_stEncodeBuffer[MAX_ENCODE_QUEUE];
CNvQueue<EncodeBuffer> m_EncodeBufferQueue;
EncodeOutputBuffer m_stEOSOutputBfr;
void convertYUVpitchtoNV12( unsigned char *yuv_luma, unsigned char *yuv_cb, unsigned char *yuv_cr,
unsigned char *nv12_luma, unsigned char *nv12_chroma,
int width, int height , int srcStride, int dstStride)
{
int y;
int x;
if (srcStride == 0)
srcStride = width;
if (dstStride == 0)
dstStride = width;
for ( y = 0 ; y < height ; y++)
{
memcpy( nv12_luma + (dstStride*y), yuv_luma + (srcStride*y) , width );
}
for ( y = 0 ; y < height/2 ; y++)
{
for ( x= 0 ; x < width; x=x+2)
{
nv12_chroma[(y*dstStride) + x] = yuv_cb[((srcStride/2)*y) + (x >>1)];
nv12_chroma[(y*dstStride) +(x+1)] = yuv_cr[((srcStride/2)*y) + (x >>1)];
}
}
}
void convertYUVpitchtoYUV444(unsigned char *yuv_luma, unsigned char *yuv_cb, unsigned char *yuv_cr,
unsigned char *surf_luma, unsigned char *surf_cb, unsigned char *surf_cr, int width, int height, int srcStride, int dstStride)
{
int h;
for (h = 0; h < height; h++)
{
memcpy(surf_luma + dstStride * h, yuv_luma + srcStride * h, width);
memcpy(surf_cb + dstStride * h, yuv_cb + srcStride * h, width);
memcpy(surf_cr + dstStride * h, yuv_cr + srcStride * h, width);
}
}
protected:
NVENCSTATUS Deinitialize(uint32_t devicetype);
NVENCSTATUS InitD3D9(uint32_t deviceID = 0);
NVENCSTATUS InitD3D11(uint32_t deviceID = 0);
NVENCSTATUS InitD3D10(uint32_t deviceID = 0);
unsigned char* LockInputBuffer(void * hInputSurface, uint32_t *pLockedPitch);
NVENCSTATUS FlushEncoder(DataPacket* dataPacket) {
NVENCSTATUS nvStatus = m_pNvHWEncoder->NvEncFlushEncoderQueue(m_stEOSOutputBfr.hOutputEvent);
if (nvStatus != NV_ENC_SUCCESS)
{
assert(0);
return nvStatus;
}
EncodeBuffer *pEncodeBufer = m_EncodeBufferQueue.GetPending();
while (pEncodeBufer)
{
m_pNvHWEncoder->ProcessOutput(pEncodeBufer, dataPacket);
pEncodeBufer = m_EncodeBufferQueue.GetPending();
}
#if defined(NV_WINDOWS)
if (WaitForSingleObject(m_stEOSOutputBfr.hOutputEvent, 500) != WAIT_OBJECT_0)
{
assert(0);
nvStatus = NV_ENC_ERR_GENERIC;
}
#endif
return nvStatus;
}
};
// NVEncodeAPI entry point
typedef NVENCSTATUS (NVENCAPI *MYPROC)(NV_ENCODE_API_FUNCTION_LIST*);

1268
rdp-acceleraed/Server/NvEncoder/NvHWEncoder.cpp
View File

File diff suppressed because it is too large Load Diff

202
rdp-acceleraed/Server/NvEncoder/NvHWEncoder.h
View File

@ -1,202 +0,0 @@
////////////////////////////////////////////////////////////////////////////
//
// Copyright 1993-2014 NVIDIA Corporation. All rights reserved.
//
// Please refer to the NVIDIA end user license agreement (EULA) associated
// with this source code for terms and conditions that govern your use of
// this software. Any use, reproduction, disclosure, or distribution of
// this software and related documentation outside the terms of the EULA
// is strictly prohibited.
//
////////////////////////////////////////////////////////////////////////////
#include <stdlib.h>
#include <stdio.h>
#include <assert.h>
#include <cuda.h>
#include "nvEncodeAPI.h"
#include "nvUtils.h"
#define SET_VER(configStruct, type) {configStruct.version = type##_VER;}
#if defined (NV_WINDOWS)
#include "d3d9.h"
#define NVENCAPI __stdcall
#pragma warning(disable : 4996)
#elif defined (NV_UNIX)
#include <dlfcn.h>
#include <string.h>
#define NVENCAPI
#endif
typedef struct _EncodeConfig
{
int width;
int height;
int maxWidth;
int maxHeight;
int fps;
int bitrate;
int vbvMaxBitrate;
int vbvSize;
int rcMode;
int qp;
GUID presetGUID;
int codec;
int invalidateRefFramesEnableFlag;
int intraRefreshEnableFlag;
int intraRefreshPeriod;
int intraRefreshDuration;
int deviceType;
int startFrameIdx;
int endFrameIdx;
int gopLength;
int numB;
int pictureStruct;
int deviceID;
int isYuv444;
char *qpDeltaMapFile;
char* inputFileName;
char* outputFileName;
char* encoderPreset;
char* inputFilePath;
char *encCmdFileName;
}EncodeConfig;
typedef struct _DataPacket
{
uint8_t *data;
int size;
}DataPacket;
typedef struct _EncodeInputBuffer
{
unsigned int dwWidth;
unsigned int dwHeight;
#if defined (NV_WINDOWS)
IDirect3DSurface9 *pNV12Surface;
#endif
CUdeviceptr pNV12devPtr;
uint32_t uNV12Stride;
CUdeviceptr pNV12TempdevPtr;
uint32_t uNV12TempStride;
void* nvRegisteredResource;
NV_ENC_INPUT_PTR hInputSurface;
NV_ENC_BUFFER_FORMAT bufferFmt;
}EncodeInputBuffer;
typedef struct _EncodeOutputBuffer
{
unsigned int dwBitstreamBufferSize;
NV_ENC_OUTPUT_PTR hBitstreamBuffer;
HANDLE hOutputEvent;
bool bWaitOnEvent;
bool bEOSFlag;
}EncodeOutputBuffer;
typedef struct _EncodeBuffer
{
EncodeOutputBuffer stOutputBfr;
EncodeInputBuffer stInputBfr;
}EncodeBuffer;
typedef struct _NvEncPictureCommand
{
bool bResolutionChangePending;
bool bBitrateChangePending;
bool bForceIDR;
bool bForceIntraRefresh;
bool bInvalidateRefFrames;
uint32_t newWidth;
uint32_t newHeight;
uint32_t newBitrate;
uint32_t newVBVSize;
uint32_t intraRefreshDuration;
uint32_t numRefFramesToInvalidate;
uint32_t refFrameNumbers[16];
}NvEncPictureCommand;
enum
{
NV_ENC_H264 = 0,
NV_ENC_HEVC = 1,
};
class CNvHWEncoder
{
public:
uint32_t m_EncodeIdx;
uint32_t m_uMaxWidth;
uint32_t m_uMaxHeight;
uint32_t m_uCurWidth;
uint32_t m_uCurHeight;
protected:
bool m_bEncoderInitialized;
GUID codecGUID;
NV_ENCODE_API_FUNCTION_LIST* m_pEncodeAPI;
HINSTANCE m_hinstLib;
void *m_hEncoder;
NV_ENC_INITIALIZE_PARAMS m_stCreateEncodeParams;
NV_ENC_CONFIG m_stEncodeConfig;
public:
NVENCSTATUS NvEncOpenEncodeSession(void* device, uint32_t deviceType);
NVENCSTATUS NvEncGetEncodeGUIDCount(uint32_t* encodeGUIDCount);
NVENCSTATUS NvEncGetEncodeProfileGUIDCount(GUID encodeGUID, uint32_t* encodeProfileGUIDCount);
NVENCSTATUS NvEncGetEncodeProfileGUIDs(GUID encodeGUID, GUID* profileGUIDs, uint32_t guidArraySize, uint32_t* GUIDCount);
NVENCSTATUS NvEncGetEncodeGUIDs(GUID* GUIDs, uint32_t guidArraySize, uint32_t* GUIDCount);
NVENCSTATUS NvEncGetInputFormatCount(GUID encodeGUID, uint32_t* inputFmtCount);
NVENCSTATUS NvEncGetInputFormats(GUID encodeGUID, NV_ENC_BUFFER_FORMAT* inputFmts, uint32_t inputFmtArraySize, uint32_t* inputFmtCount);
NVENCSTATUS NvEncGetEncodeCaps(GUID encodeGUID, NV_ENC_CAPS_PARAM* capsParam, int* capsVal);
NVENCSTATUS NvEncGetEncodePresetCount(GUID encodeGUID, uint32_t* encodePresetGUIDCount);
NVENCSTATUS NvEncGetEncodePresetGUIDs(GUID encodeGUID, GUID* presetGUIDs, uint32_t guidArraySize, uint32_t* encodePresetGUIDCount);
NVENCSTATUS NvEncGetEncodePresetConfig(GUID encodeGUID, GUID presetGUID, NV_ENC_PRESET_CONFIG* presetConfig);
NVENCSTATUS NvEncCreateInputBuffer(uint32_t width, uint32_t height, void** inputBuffer, uint32_t isYuv444);
NVENCSTATUS NvEncDestroyInputBuffer(NV_ENC_INPUT_PTR inputBuffer);
NVENCSTATUS NvEncCreateBitstreamBuffer(uint32_t size, void** bitstreamBuffer);
NVENCSTATUS NvEncDestroyBitstreamBuffer(NV_ENC_OUTPUT_PTR bitstreamBuffer);
NVENCSTATUS NvEncLockBitstream(NV_ENC_LOCK_BITSTREAM* lockBitstreamBufferParams);
NVENCSTATUS NvEncUnlockBitstream(NV_ENC_OUTPUT_PTR bitstreamBuffer);
NVENCSTATUS NvEncLockInputBuffer(void* inputBuffer, void** bufferDataPtr, uint32_t* pitch);
NVENCSTATUS NvEncUnlockInputBuffer(NV_ENC_INPUT_PTR inputBuffer);
NVENCSTATUS NvEncGetEncodeStats(NV_ENC_STAT* encodeStats);
NVENCSTATUS NvEncGetSequenceParams(NV_ENC_SEQUENCE_PARAM_PAYLOAD* sequenceParamPayload);
NVENCSTATUS NvEncRegisterAsyncEvent(void** completionEvent);
NVENCSTATUS NvEncUnregisterAsyncEvent(void* completionEvent);
NVENCSTATUS NvEncMapInputResource(void* registeredResource, void** mappedResource);
NVENCSTATUS NvEncUnmapInputResource(NV_ENC_INPUT_PTR mappedInputBuffer);
NVENCSTATUS NvEncDestroyEncoder();
NVENCSTATUS NvEncInvalidateRefFrames(const NvEncPictureCommand *pEncPicCommand);
NVENCSTATUS NvEncOpenEncodeSessionEx(void* device, NV_ENC_DEVICE_TYPE deviceType);
NVENCSTATUS NvEncRegisterResource(NV_ENC_INPUT_RESOURCE_TYPE resourceType, void* resourceToRegister, uint32_t width, uint32_t height, uint32_t pitch, void** registeredResource);
NVENCSTATUS NvEncUnregisterResource(NV_ENC_REGISTERED_PTR registeredRes);
NVENCSTATUS NvEncReconfigureEncoder(const NvEncPictureCommand *pEncPicCommand);
NVENCSTATUS NvEncFlushEncoderQueue(void *hEOSEvent);
CNvHWEncoder();
virtual ~CNvHWEncoder();
NVENCSTATUS Initialize(void* device, NV_ENC_DEVICE_TYPE deviceType);
NVENCSTATUS Deinitialize();
NVENCSTATUS NvEncEncodeFrame(EncodeBuffer *pEncodeBuffer, NvEncPictureCommand *encPicCommand,
uint32_t width, uint32_t height,
NV_ENC_PIC_STRUCT ePicStruct = NV_ENC_PIC_STRUCT_FRAME,
int8_t *qpDeltaMapArray = NULL, uint32_t qpDeltaMapArraySize = 0);
NVENCSTATUS CreateEncoder(const EncodeConfig *pEncCfg);
GUID GetPresetGUID(char* encoderPreset, int codec);
NVENCSTATUS ProcessOutput(const EncodeBuffer *pEncodeBuffer, DataPacket* dataPacket);
NVENCSTATUS FlushEncoder();
NVENCSTATUS ValidateEncodeGUID(GUID inputCodecGuid);
NVENCSTATUS ValidatePresetGUID(GUID presetCodecGuid, GUID inputCodecGuid);
static NVENCSTATUS ParseArguments(EncodeConfig *encodeConfig, int argc, char *argv[]);
};
typedef NVENCSTATUS (NVENCAPI *MYPROC)(NV_ENCODE_API_FUNCTION_LIST*);

28
rdp-acceleraed/Server/NvEncoder/nvCPUOPSys.h
View File

@ -1,28 +0,0 @@
//
// Copyright 1993-2014 NVIDIA Corporation. All rights reserved.
//
// Please refer to the NVIDIA end user license agreement (EULA) associated
// with this source code for terms and conditions that govern your use of
// this software. Any use, reproduction, disclosure, or distribution of
// this software and related documentation outside the terms of the EULA
// is strictly prohibited.
//
////////////////////////////////////////////////////////////////////////////
#ifndef NVCPUOPSYS_H
#define NVCPUOPSYS_H
#if defined(_WIN32) || defined(_WIN16)
# define NV_WINDOWS
#endif
#if (defined(__unix__) || defined(__unix) ) && !defined(nvmacosx) && !defined(vxworks) && !defined(__DJGPP__) && !defined(NV_UNIX) && !defined(__QNX__) && !defined(__QNXNTO__)/* XXX until removed from Makefiles */
# define NV_UNIX
#endif /* defined(__unix__) */
#if defined(__linux__) && !defined(NV_LINUX) && !defined(NV_VMWARE)
# define NV_LINUX
#endif /* defined(__linux__) */
#endif

2965
rdp-acceleraed/Server/NvEncoder/nvEncodeAPI.h
View File

File diff suppressed because it is too large Load Diff

177
rdp-acceleraed/Server/NvEncoder/nvFileIO.h
View File

@ -1,177 +0,0 @@
///
// Copyright 1993-2014 NVIDIA Corporation. All rights reserved.
//
// Please refer to the NVIDIA end user license agreement (EULA) associated
// with this source code for terms and conditions that govern your use of
// this software. Any use, reproduction, disclosure, or distribution of
// this software and related documentation outside the terms of the EULA
// is strictly prohibited.
//
////////////////////////////////////////////////////////////////////////////
#ifndef NVFILE_IO_H
#define NVFILE_IO_H
#if defined __linux__
#include <stdio.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <errno.h>
#include <string.h>
#include <unistd.h>
#include <dlfcn.h>
#include <stdlib.h>
typedef void * HANDLE;
typedef void *HINSTANCE;
typedef unsigned long DWORD, *LPDWORD;
typedef DWORD FILE_SIZE;
#define FALSE 0
#define TRUE 1
#define INFINITE UINT_MAX
#define FILE_BEGIN SEEK_SET
#define INVALID_SET_FILE_POINTER (-1)
#define INVALID_HANDLE_VALUE ((void *)(-1))
#else
#include <stdio.h>
#include <windows.h>
#endif
#include "nvCPUOPSys.h"
typedef unsigned long long U64;
typedef unsigned int U32;
inline U32 nvSetFilePointer(HANDLE hInputFile, U32 fileOffset, U32 *moveFilePointer, U32 flag)
{
#if defined (NV_WINDOWS)
return SetFilePointer(hInputFile, fileOffset, NULL, flag);
#elif defined __linux || defined __APPLE_ || defined __MACOSX
return fseek((FILE *)hInputFile, fileOffset, flag);
#endif
}
inline U32 nvSetFilePointer64(HANDLE hInputFile, U64 fileOffset, U64 *moveFilePointer, U32 flag)
{
#if defined (NV_WINDOWS)
return SetFilePointer(hInputFile, ((U32 *)&fileOffset)[0], (PLONG)&((U32 *)&fileOffset)[1], flag);
#elif defined __linux || defined __APPLE__ || defined __MACOSX
return fseek((FILE *)hInputFile, (long int)fileOffset, flag);
#endif
}
inline bool nvReadFile(HANDLE hInputFile, void *buf, U32 bytes_to_read, U32 *bytes_read, void *operlapped)
{
#if defined (NV_WINDOWS)
ReadFile(hInputFile, buf, bytes_to_read, (LPDWORD)bytes_read, NULL);
return true;
#elif defined __linux || defined __APPLE__ || defined __MACOSX
U32 num_bytes_read;
num_bytes_read = fread(buf, bytes_to_read, 1, (FILE *)hInputFile);
if (bytes_read)
{
*bytes_read = num_bytes_read;
}
return true;
#endif
}
inline void nvGetFileSize(HANDLE hInputFile, DWORD *pFilesize)
{
#if defined (NV_WINDOWS)
LARGE_INTEGER file_size;
if (hInputFile != INVALID_HANDLE_VALUE)
{
file_size.LowPart = GetFileSize(hInputFile, (LPDWORD)&file_size.HighPart);
printf("[ Input Filesize] : %lld bytes\n", ((LONGLONG) file_size.HighPart << 32) + (LONGLONG)file_size.LowPart);
if (pFilesize != NULL) *pFilesize = file_size.LowPart;
}
#elif defined __linux || defined __APPLE__ || defined __MACOSX
FILE_SIZE file_size;
if (hInputFile != NULL)
{
nvSetFilePointer64(hInputFile, 0, NULL, SEEK_END);
file_size = ftell((FILE *)hInputFile);
nvSetFilePointer64(hInputFile, 0, NULL, SEEK_SET);
printf("Input Filesize: %ld bytes\n", file_size);
if (pFilesize != NULL) *pFilesize = file_size;
}
#endif
}
inline HANDLE nvOpenFile(const char *input_file)
{
HANDLE hInput = NULL;
#if defined (NV_WINDOWS)
hInput = CreateFileA(input_file, GENERIC_READ, FILE_SHARE_READ, NULL, OPEN_EXISTING , FILE_ATTRIBUTE_NORMAL, NULL);
if (hInput == INVALID_HANDLE_VALUE)
{
fprintf(stderr, "nvOpenFile Failed to open \"%s\"\n", input_file);
exit(EXIT_FAILURE);
}
#elif defined __linux || defined __APPLE_ || defined __MACOSX
hInput = fopen(input_file, "rb");
if (hInput == NULL)
{
fprintf(stderr, "nvOpenFile Failed to open \"%s\"\n", input_file);
exit(EXIT_FAILURE);
}
#endif
return hInput;
}
inline HANDLE nvOpenFileWrite(const char *output_file)
{
HANDLE hOutput = NULL;
#if defined (NV_WINDOWS)
hOutput = CreateFileA(output_file, GENERIC_WRITE, FILE_SHARE_WRITE, NULL, OPEN_EXISTING , FILE_ATTRIBUTE_NORMAL, NULL);
if (hOutput == INVALID_HANDLE_VALUE)
{
fprintf(stderr, "nvOpenFileWrite Failed to open \"%s\"\n", output_file);
exit(EXIT_FAILURE);
}
#elif defined __linux || defined __APPLE_ || defined __MACOSX
hOutput = fopen(output_file, "wb+");
if (hOutput == NULL)
{
fprintf(stderr, "nvOpenFileWrite Failed to open \"%s\"\n", output_file);
exit(EXIT_FAILURE);
}
#endif
return hOutput;
}
inline void nvCloseFile(HANDLE hFileHandle)
{
if (hFileHandle)
{
#if defined (NV_WINDOWS)
CloseHandle(hFileHandle);
#else
fclose((FILE *)hFileHandle);
#endif
}
}
#endif

127
rdp-acceleraed/Server/NvEncoder/nvUtils.h
View File

@ -1,127 +0,0 @@
//
// Copyright 1993-2014 NVIDIA Corporation. All rights reserved.
//
// Please refer to the NVIDIA end user license agreement (EULA) associated
// with this source code for terms and conditions that govern your use of
// this software. Any use, reproduction, disclosure, or distribution of
// this software and related documentation outside the terms of the EULA
// is strictly prohibited.
//
////////////////////////////////////////////////////////////////////////////
#ifndef NVUTILS_H
#define NVUTILS_H
#include "nvCPUOPSys.h"
#include "nvFileIO.h"
#if defined (NV_WINDOWS)
#include <windows.h>
#elif defined NV_UNIX
#include <sys/time.h>
#include <limits.h>
#define FALSE 0
#define TRUE 1
#define INFINITE UINT_MAX
#define stricmp strcasecmp
#define FILE_BEGIN SEEK_SET
#define INVALID_SET_FILE_POINTER (-1)
#define INVALID_HANDLE_VALUE ((void *)(-1))
#define max(a, b) ((a) > (b) ? (a) : (b))
#define min(a, b) ((a) < (b) ? (a) : (b))
typedef void* HANDLE;
typedef void* HINSTANCE;
typedef unsigned long DWORD, *LPWORD;
typedef DWORD FILE_SIZE;
#endif
inline bool NvSleep(unsigned int mSec)
{
#if defined (NV_WINDOWS)
Sleep(mSec);
#elif defined NV_UNIX
usleep(mSec * 1000);
#else
#error NvSleep function unknown for this platform.
#endif
return true;
}
inline bool NvQueryPerformanceFrequency(unsigned long long *freq)
{
*freq = 0;
#if defined (NV_WINDOWS)
LARGE_INTEGER lfreq;
if (!QueryPerformanceFrequency(&lfreq)) {
return false;
}
*freq = lfreq.QuadPart;
#elif defined NV_UNIX
// We use system's gettimeofday() to return timer ticks in uSec
*freq = 1000000000;
#else
#error NvQueryPerformanceFrequency function not defined for this platform.
#endif
return true;
}
#define SEC_TO_NANO_ULL(sec) ((unsigned long long)sec * 1000000000)
#define MICRO_TO_NANO_ULL(sec) ((unsigned long long)sec * 1000)
inline bool NvQueryPerformanceCounter(unsigned long long *counter)
{
*counter = 0;
#if defined (NV_WINDOWS)
LARGE_INTEGER lcounter;
if (!QueryPerformanceCounter(&lcounter)) {
return false;
}
*counter = lcounter.QuadPart;
#elif defined NV_UNIX
struct timeval tv;
int ret;
ret = gettimeofday(&tv, NULL);
if (ret != 0) {
return false;
}
*counter = SEC_TO_NANO_ULL(tv.tv_sec) + MICRO_TO_NANO_ULL(tv.tv_usec);
#else
#error NvQueryPerformanceCounter function not defined for this platform.
#endif
return true;
}
#if defined NV_UNIX
__inline bool operator==(const GUID &guid1, const GUID &guid2)
{
if (guid1.Data1 == guid2.Data1 &&
guid1.Data2 == guid2.Data2 &&
guid1.Data3 == guid2.Data3 &&
guid1.Data4[0] == guid2.Data4[0] &&
guid1.Data4[1] == guid2.Data4[1] &&
guid1.Data4[2] == guid2.Data4[2] &&
guid1.Data4[3] == guid2.Data4[3] &&
guid1.Data4[4] == guid2.Data4[4] &&
guid1.Data4[5] == guid2.Data4[5] &&
guid1.Data4[6] == guid2.Data4[6] &&
guid1.Data4[7] == guid2.Data4[7])
{
return true;
}
return false;
}
__inline bool operator!=(const GUID &guid1, const GUID &guid2)
{
return !(guid1 == guid2);
}
#endif
#endif
#define PRINTERR(message, ...) \
fprintf(stderr, "%s line %d: " message, __FILE__, __LINE__, ##__VA_ARGS__)

40
rdp-acceleraed/Server/WDDMCapture.h
View File

@ -1,40 +0,0 @@
#pragma once
#include "wddm.h"
#include "Capture.h"
class WDDMCapture : public Capture {
public:
void init(UINT monitorID, RECT screen)
{
this->screen = screen;
wddm.wf_dxgi_init(monitorID, screen);
}
int getNextFrame(RGBQUAD** pPixels)
{
int rc;
rc = wddm.wf_dxgi_nextFrame(3000);
if (rc != 0) {
return rc;
}
int pitch;
rc = wddm.wf_dxgi_getPixelData((byte**)pPixels, &pitch, &screen);
if (rc != 0) {
return rc;
}
return 0;
}
void doneNextFrame()
{
int rc = wddm.wf_dxgi_releasePixelData();
}
private:
RECT screen;
WDDM wddm;
};

53
rdp-acceleraed/Server/bounded_buffer.h
View File

@ -1,53 +0,0 @@
#include <boost/circular_buffer.hpp>
#include <boost/thread/mutex.hpp>
#include <boost/thread/condition.hpp>
#include <boost/thread/thread.hpp>
#include <boost/call_traits.hpp>
#include <boost/bind.hpp>
#include <boost/timer/timer.hpp> // for auto_cpu_timer
template <class T>
class bounded_buffer
{
public:
typedef boost::circular_buffer<T> container_type;
typedef typename container_type::size_type size_type;
typedef typename container_type::value_type value_type;
typedef typename boost::call_traits<value_type>::param_type param_type;
explicit bounded_buffer(size_type capacity) : m_unread(0), m_container(capacity) {}
void push_front(typename boost::call_traits<value_type>::param_type item)
{ // `param_type` represents the "best" way to pass a parameter of type `value_type` to a method.
boost::mutex::scoped_lock lock(m_mutex);
m_not_full.wait(lock, boost::bind(&bounded_buffer<value_type>::is_not_full, this));
m_container.push_front(item);
++m_unread;
lock.unlock();
m_not_empty.notify_one();
}
void pop_back(value_type* pItem) {
boost::mutex::scoped_lock lock(m_mutex);
m_not_empty.wait(lock, boost::bind(&bounded_buffer<value_type>::is_not_empty, this));
*pItem = m_container[--m_unread];
lock.unlock();
m_not_full.notify_one();
}
private:
bounded_buffer(const bounded_buffer&); // Disabled copy constructor.
bounded_buffer& operator = (const bounded_buffer&); // Disabled assign operator.
bool is_not_empty() const { return m_unread > 0; }
bool is_not_full() const { return m_unread < m_container.capacity(); }
size_type m_unread;
container_type m_container;
boost::mutex m_mutex;
boost::condition m_not_empty;
boost::condition m_not_full;
}; //

100
rdp-acceleraed/Server/color_conversion.cu
View File

@ -1,100 +0,0 @@
#include "cuda.h"
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "color_conversion.h"
#include "stdio.h"
__host__ __device__ __forceinline__ int divUp(int total, int grain)
{
return (total + grain - 1) / grain;
}
__global__ void RGB_to_jp(uchar4 *input, unsigned char *yuv_luma, unsigned char *yuv_cb, unsigned char *yuv_cr, int width, int height)
{
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x >= width || y>=height) return;
uchar4 px = input[y * width + x];
int Y = ( ( 66 * px.x + 129 * px.y + 25 * px.z + 128) >> 8) + 16;
int U = ( ( -38 * px.x - 74 * px.y + 112 * px.z + 128) >> 8) + 128;
int V = ( ( 112 * px.x - 94 * px.y - 18 * px.z + 128) >> 8) + 128;
yuv_luma[y * width + x] = Y;
int pos = (y >> 1) * (width >> 1) + (x >> 1);
yuv_cr[pos] = U;
yuv_cb[pos] = V;
}
bool RGB_to_YV12(int width, int height, void *pPixels, void* yuv_luma, void* yuv_cb, void* yuv_cr)
{
cudaError_t cudaStatus;
const dim3 block(32, 8);
const dim3 grid(divUp(width, block.x), divUp(height, block.y));
unsigned char *yuv_luma_device;
cudaMalloc(&yuv_luma_device, width *height * sizeof(unsigned char));
unsigned char *yuv_cb_device;
cudaMalloc(&yuv_cb_device, width *height * sizeof(unsigned char) / 4);
unsigned char *yuv_cr_device;
cudaMalloc(&yuv_cr_device, width *height * sizeof(unsigned char) / 4);
// Copy input vectors from host memory to GPU buffers.
uchar4 *dev_pPixels;
cudaStatus = cudaMalloc((void**)&dev_pPixels, width *height * sizeof(uchar4));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
return false;
}
cudaStatus = cudaMemcpy(dev_pPixels, pPixels, width *height * sizeof(uchar4), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy 1 failed!");
return false;
}
RGB_to_jp<<< grid, block >>>(dev_pPixels, yuv_luma_device, yuv_cb_device, yuv_cr_device, width, height);
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "RGB_to_jp failed!");
return false;
}
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize failed!");
return false;
}
cudaStatus = cudaMemcpy(yuv_luma, yuv_luma_device, width *height * sizeof(unsigned char), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy 2 failed!");
return false;
}
cudaStatus = cudaMemcpy(yuv_cb, yuv_cb_device, width *height * sizeof(unsigned char) / 4, cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy 2 failed!");
return false;
}
cudaStatus = cudaMemcpy(yuv_cr, yuv_cr_device, width *height * sizeof(unsigned char) / 4, cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy 2 failed!");
return false;
}
cudaFree(yuv_luma_device);
cudaFree(yuv_cb_device);
cudaFree(yuv_cr_device);
cudaFree(dev_pPixels);
return true;
}

1
rdp-acceleraed/Server/color_conversion.h
View File

@ -1 +0,0 @@
bool RGB_to_YV12(int width, int height, void *pPixels, void* yuv_luma, void* yuv_cb, void* yuv_cr);

4
rdp-acceleraed/Server/config.h.in
View File

@ -1,4 +0,0 @@
#cmakedefine HAS_CUDA
#cmakedefine HAS_WDDM
#cmakedefine HAS_NVENC
#cmakedefine HAS_FFMPEG

43
rdp-acceleraed/Server/fps.h
View File

@ -1,43 +0,0 @@
#pragma once
#include <time.h>
class FPS {
public:
FPS() {
fps = 0;
numFrame = 0;
lastSec = 0;
lastShouldRefresh = 0;
}
void newFrame() {
numFrame++;
double newTime = (double)clock() / CLOCKS_PER_SEC;
if (newTime >= lastSec + 1) {
fps = numFrame;
numFrame = 0;
lastSec = newTime;
printf("FPS: %d\n", getFps());
}
}
int getFps() {
return fps;
}
/* Returns true only 30 times per second */
bool shouldRefresh() {
double newTime = (double)clock() / CLOCKS_PER_SEC;
if (newTime >= lastShouldRefresh + 1.0/30) {
lastShouldRefresh = newTime;
return true;
} else {
return false;
}
}
private:
int fps;
int numFrame;
double lastSec;
double lastShouldRefresh;
};

19
rdp-acceleraed/Server/monitor.h
View File

@ -1,19 +0,0 @@
#pragma once
BOOL CALLBACK MonitorEnumProc(HMONITOR hMonitor, HDC hdcMonitor, LPRECT lprcMonitor, LPARAM dwData);
class Monitor {
public:
Monitor() {
if(!EnumDisplayMonitors(NULL, NULL, MonitorEnumProc, reinterpret_cast<LPARAM>(this))) {
throw std::runtime_error ("EnumDisplayMonitors failed");
}
}
std::vector<RECT> monitors;
};
BOOL CALLBACK MonitorEnumProc(HMONITOR hMonitor, HDC hdcMonitor, LPRECT lprcMonitor, LPARAM dwData)
{
Monitor* mon = (Monitor*)dwData;
mon->monitors.push_back(*lprcMonitor);
return true;
}

38
rdp-acceleraed/Server/params.h
View File

@ -1,38 +0,0 @@
#pragma once
#include <map>
#include <iostream>
#include <string>
using namespace std;
class Params {
public:
Params(int argc, const char* argv[]) {
// defaults
monitor = -1;
port = -1;
map<string, string> params;
for (int i = 1; i < argc; i++) {
string key = argv[i];
params[key] = argv[i + 1];
i++;
}
typedef map<string, string>::iterator it_type;
for (it_type iterator = params.begin(); iterator != params.end(); iterator++) {
cout << iterator->first << " : " << iterator->second << endl;
if (iterator->first.compare("monitor") == 0) {
monitor = atoi(iterator->second.c_str());
} else if (iterator->first.compare("port") == 0) {
port = atoi(iterator->second.c_str());
}
}
}
int monitor;
int port;
};

278
rdp-acceleraed/Server/server.cpp
View File

@ -1,278 +0,0 @@
//
// Copyright (c) 2003-2013 Christopher M. Kohlhoff (chris at kohlhoff dot com)
//
// Distributed under the Boost Software License, Version 1.0. (See accompanying
// file LICENSE_1_0.txt or copy at http://www.boost.org/LICENSE_1_0.txt)
//
#include <fstream>
#include <algorithm>
#include <boost/asio.hpp>
#include <boost/thread.hpp>
#include <bounded_buffer.h>
#include "fps.h"
#include "monitor.h"
#include "params.h"
#include "config.h"
#ifdef HAS_WDDM
#include "WDDMCapture.h"
#else
#include "GDICapture.h"
#endif
#ifdef HAS_FFMPEG
#include "FFMPEG_encoding.hpp"
#endif
#ifdef HAS_NVENC
#include "NV_encoding.hpp"
#endif
using namespace std;
using namespace boost::asio;
using ip::tcp;
const int max_length = 1024;
typedef boost::shared_ptr<tcp::socket> socket_ptr;
bounded_buffer<RGBQUAD*> screenToSendQueue(2);
void threadScreenCapture(UINT monitorID, RECT screen){
int height = screen.bottom - screen.top;
int width = screen.right - screen.left;
#ifdef HAS_WDDM
WDDMCapture capture;
#else
GDICapture capture;
#endif
capture.init(monitorID, screen);
RGBQUAD* pPixels;
FPS fps;
while(true){
int rc = capture.getNextFrame(&pPixels);
if (rc == 0) {
RGBQUAD* pixCopy = new RGBQUAD[width * height];
memcpy(pixCopy, pPixels, width * height * sizeof(RGBQUAD));
screenToSendQueue.push_front(pixCopy);
capture.doneNextFrame();
fps.newFrame();
}
}
}
void sessionVideo(socket_ptr sock, UINT monitorID, RECT screen)
{
// get the height and width of the screen
int height = screen.bottom - screen.top;
int width = screen.right - screen.left;
#ifdef HAS_NVENC
NV_encoding nv_encoding;
nv_encoding.load(width, height, sock, monitorID);
#elif defined(HAS_FFMPEG)
FFMPEG_encoding ffmpeg;
ffmpeg.load(width, height, sock);
#endif
boost::thread t(boost::bind(threadScreenCapture, monitorID, screen));
FPS fps;
RGBQUAD* pPixels;
while(true){
screenToSendQueue.pop_back(&pPixels);
#ifdef HAS_NVENC
nv_encoding.write(width, height, pPixels);
#elif defined(HAS_FFMPEG)
ffmpeg.write(width, height, pPixels);
#endif
//fps.newFrame();
free(pPixels);
}
#ifdef HAS_NVENC
nv_encoding.close();
#elif defined(HAS_FFMPEG)
ffmpeg.close();
#endif
}
struct SendStruct {
int type;
int x;
int y;
int button;
int keycode;
};
void sessionKeystroke(socket_ptr sock, RECT screen)
{
char data[sizeof(SendStruct)];
boost::system::error_code error;
SendStruct* s;
INPUT input = {0};
while(true) {
size_t length = sock->read_some(buffer(data), error);
if (error == error::eof)
return; // Connection closed cleanly by peer.
else if (error)
throw boost::system::system_error(error); // Some other error.
s = (SendStruct*)data;
::ZeroMemory(&input,sizeof(INPUT));
switch(s->type){
case 0: // MotionNotify
SetCursorPos(s->x + screen.left, s->y + screen.top);
break;
case 1:
switch (s->button) {
case 1: // left button
input.mi.dwFlags = MOUSEEVENTF_LEFTDOWN;
break;
case 2: // middle button
input.mi.dwFlags = MOUSEEVENTF_MIDDLEDOWN;
break;
case 3: // third button
input.mi.dwFlags = MOUSEEVENTF_RIGHTDOWN;
break;
case 4: // scroll up
input.mi.dwFlags = MOUSEEVENTF_WHEEL;
input.mi.mouseData = 100;
break;
case 5: // scroll down
input.mi.dwFlags = MOUSEEVENTF_WHEEL;
input.mi.mouseData = -100;
break;
}
input.type = INPUT_MOUSE;
::SendInput(1,&input,sizeof(INPUT));
break;
case 2:
switch (s->button) {
case 1: // left button
input.mi.dwFlags = MOUSEEVENTF_LEFTUP;
break;
case 2: // middle button
input.mi.dwFlags = MOUSEEVENTF_MIDDLEUP;
break;
case 3: // third button
input.mi.dwFlags = MOUSEEVENTF_RIGHTUP;
break;
}
if (input.mi.dwFlags) {
input.type = INPUT_MOUSE;
::SendInput(1,&input,sizeof(INPUT));
}
break;
case 3:
input.type = INPUT_KEYBOARD;
input.ki.wScan = s->keycode;
input.ki.wVk=0;
input.ki.dwFlags = KEYEVENTF_UNICODE;
::SendInput(1,&input,sizeof(INPUT));
break;
case 4:
input.type = INPUT_KEYBOARD;
input.ki.wScan = s->keycode;
input.ki.wVk=0;
input.ki.dwFlags = KEYEVENTF_UNICODE | KEYEVENTF_KEYUP;
::SendInput(1,&input,sizeof(INPUT));
break;
}
}
}
void session(socket_ptr sock, UINT monitorID, RECT screenCoordinates)
{
try
{
sock->set_option(tcp::no_delay(true));
char data[max_length];
boost::system::error_code error;
size_t length = sock->read_some(buffer(data), error);
if (error == error::eof)
return; // Connection closed cleanly by peer.
else if (error)
throw boost::system::system_error(error); // Some other error.
if (data[0] == 'a'){
sessionVideo(sock, monitorID, screenCoordinates);
} else if (data[0] == 'b'){
sessionKeystroke(sock, screenCoordinates);
} else {
cout << "Received a connection with a wrong identification buffer " << string(data, length) << endl;
}
}
catch (exception& e)
{
cerr << "Exception in thread: " << e.what() << "\n";
}
}
void server(io_service& io_service, short port, UINT monitorID, RECT screenCoordinates)
{
tcp::acceptor a(io_service, tcp::endpoint(tcp::v4(), port));
for (;;)
{
socket_ptr sock(new tcp::socket(io_service));
a.accept(*sock);
boost::thread t(boost::bind(session, sock, monitorID, screenCoordinates));
}
}
int main(int argc, const char* argv[])
{
cout << "Version 0.9" << endl;
Params params(argc, argv);
if (params.port == -1)
{
cerr << "Usage: ./server [options] port <#>" << endl;
cerr << "monitor <n>\n";
cerr << "Sample: ./server monitor 1 port 8080" << endl;
return 1;
}
Monitor monitor;
RECT screenCoordinates;
int monitorCount = GetSystemMetrics(SM_CMONITORS);
if (monitorCount > 1 && params.monitor == -1) {
cerr << "There are more than one monitor available, select which monitor to use with\n./server -monitor <n> <port>" << endl;
return 1;
} else {
if (params.monitor < 0 || params.monitor >= monitor.monitors.size()) {
cerr << "The chosen monitor " << params.monitor << " is invalid, select from the following:\n";
for (int i=0;i<monitor.monitors.size();i++) {
RECT r = monitor.monitors[i];
cerr << "Monitor " << i << ":" << "["<<r.left<<" "<<r.top<<","<<r.bottom<<" "<<r.right<<"]" << endl;
}
return 1;
}
screenCoordinates = monitor.monitors[params.monitor];
}
//socket_ptr sock;
//sessionVideo(sock, params.monitor, screenCoordinates); // TODO test
try
{
io_service io_service;
server(io_service, params.port, params.monitor, screenCoordinates);
}
catch (exception& e)
{
cerr << "Exception: " << e.what() << "\n";
}
return 0;
}

405
rdp-acceleraed/Server/wddm.h
View File

@ -1,405 +0,0 @@
#pragma once
//#pragma comment (lib, "d3dx11.lib")
//#pragma comment (lib, "d3dx10.lib")
#include <windows.h>
#include <windowsx.h>
//#define CINTERFACE
#include <DXGItype.h>
#include <D3D11.h>
#pragma comment (lib, "d3d11.lib")
#include <dxgi1_2.h>
#include <tchar.h>
/* Driver types supported */
D3D_DRIVER_TYPE DriverTypes[] =
{
D3D_DRIVER_TYPE_HARDWARE,
D3D_DRIVER_TYPE_WARP,
D3D_DRIVER_TYPE_REFERENCE,
};
UINT NumDriverTypes = ARRAYSIZE(DriverTypes);
D3D_FEATURE_LEVEL FeatureLevels[] =
{
D3D_FEATURE_LEVEL_11_0,
D3D_FEATURE_LEVEL_10_1,
D3D_FEATURE_LEVEL_10_0,
D3D_FEATURE_LEVEL_9_1
};
UINT NumFeatureLevels = ARRAYSIZE(FeatureLevels);
D3D_FEATURE_LEVEL FeatureLevel;
ID3D11Device* gDevice = NULL;
ID3D11DeviceContext* gContext = NULL;
IDXGIOutputDuplication* gOutputDuplication = NULL;
IDXGISurface* surf = NULL;
ID3D11Texture2D* sStage = NULL;
DXGI_OUTDUPL_FRAME_INFO FrameInfo;
class WDDM {
public:
int wf_dxgi_init(UINT screenID, RECT screen)
{
//not sure if needed
gAcquiredDesktopImage = NULL;
this->screen = screen;
if (wf_dxgi_createDevice() != 0)
{
return 1;
}
if (wf_dxgi_getDuplication(screenID) != 0)
{
return 1;
}
return 0;
}
int wf_dxgi_createDevice()
{
HRESULT status;
UINT DriverTypeIndex;
for (DriverTypeIndex = 0; DriverTypeIndex < NumDriverTypes; ++DriverTypeIndex)
{
/*status = D3D11CreateDevice(NULL, DriverTypes[DriverTypeIndex], NULL, D3D11_CREATE_DEVICE_DEBUG, FeatureLevels, NumFeatureLevels,
D3D11_SDK_VERSION, &gDevice, &FeatureLevel, &gContext);
*/
status = D3D11CreateDevice(NULL, DriverTypes[DriverTypeIndex], NULL, NULL, FeatureLevels, NumFeatureLevels,
D3D11_SDK_VERSION, &gDevice, &FeatureLevel, &gContext);
if (SUCCEEDED(status))
break;
_tprintf(_T("D3D11CreateDevice returned [%d] for Driver Type %d\n"), status, DriverTypes[DriverTypeIndex]);
}
if (FAILED(status))
{
_tprintf(_T("Failed to create device in InitializeDx\n"));
return 1;
//debug
/*
for (DriverTypeIndex = 0; DriverTypeIndex < NumDriverTypes; ++DriverTypeIndex)
{
status = D3D11CreateDevice(NULL, DriverTypes[DriverTypeIndex], NULL, NULL, FeatureLevels, NumFeatureLevels,
D3D11_SDK_VERSION, &gDevice, &FeatureLevel, &gContext);
if (SUCCEEDED(status))
break;
_tprintf(_T("D3D11CreateDevice returned [%d] for Driver Type %d\n"), status, DriverTypes[DriverTypeIndex]);
}
if (FAILED(status))
{
_tprintf(_T("Failed to create device in InitializeDx\n"));
return 1;
}
*/
}
return 0;
}
int wf_dxgi_getDuplication(UINT screenID)
{
HRESULT status;
UINT dTop, i = 0;
DXGI_OUTPUT_DESC desc;
IDXGIOutput * pOutput;
IDXGIDevice* DxgiDevice = NULL;
IDXGIAdapter* DxgiAdapter = NULL;
IDXGIOutput* DxgiOutput = NULL;
IDXGIOutput1* DxgiOutput1 = NULL;
status = gDevice->QueryInterface(__uuidof(IDXGIDevice), (void**)&DxgiDevice);
if (FAILED(status))
{
_tprintf(_T("Failed to get QI for DXGI Device\n"));
return 1;
}
status = DxgiDevice->GetParent(__uuidof(IDXGIAdapter), (void**)&DxgiAdapter);
DxgiDevice->Release();
DxgiDevice = NULL;
if (FAILED(status))
{
_tprintf(_T("Failed to get parent DXGI Adapter\n"));
return 1;
}
ZeroMemory(&desc, sizeof(desc));
pOutput = NULL;
while (DxgiAdapter->EnumOutputs(i, &pOutput) != DXGI_ERROR_NOT_FOUND)
{
DXGI_OUTPUT_DESC* pDesc = &desc;
status = pOutput->GetDesc(pDesc);
if (FAILED(status))
{
_tprintf(_T("Failed to get description\n"));
return 1;
}
wprintf(L"Output %d: [%s] [%s] (%d, %d, %d, %d)\n", i, pDesc->DeviceName, pDesc->AttachedToDesktop ? L"attached" : L"not attached",
pDesc->DesktopCoordinates.left, pDesc->DesktopCoordinates.top, pDesc->DesktopCoordinates.right, pDesc->DesktopCoordinates.bottom);
if (pDesc->AttachedToDesktop)
dTop = i;
pOutput->Release();
++i;
}
dTop = screenID;
status = DxgiAdapter->EnumOutputs(dTop, &DxgiOutput);
DxgiAdapter->Release();
DxgiAdapter = NULL;
if (FAILED(status))
{
_tprintf(_T("Failed to get output\n"));
return 1;
}
status = DxgiOutput->QueryInterface(__uuidof(DxgiOutput1), (void**)&DxgiOutput1);
DxgiOutput->Release();
DxgiOutput = NULL;
if (FAILED(status))
{
_tprintf(_T("Failed to get IDXGIOutput1\n"));
return 1;
}
status = DxgiOutput1->DuplicateOutput(gDevice, &gOutputDuplication);
DxgiOutput1->Release();
DxgiOutput1 = NULL;
if (FAILED(status))
{
if (status == DXGI_ERROR_NOT_CURRENTLY_AVAILABLE)
{
_tprintf(_T("There is already the maximum number of applications using the Desktop Duplication API running, please close one of those applications and then try again.\n"));
return 1;
}
_tprintf(_T("Failed to get duplicate output\n"));
return 1;
}
return 0;
}
int wf_dxgi_cleanup()
{
if (framesWaiting > 0)
{
wf_dxgi_releasePixelData();
}
if (gAcquiredDesktopImage)
{
gAcquiredDesktopImage->Release();
gAcquiredDesktopImage = NULL;
}
if (gOutputDuplication)
{
gOutputDuplication->Release();
gOutputDuplication = NULL;
}
if (gContext)
{
gContext->Release();
gContext = NULL;
}
if (gDevice)
{
gDevice->Release();
gDevice = NULL;
}
return 0;
}
int wf_dxgi_nextFrame(UINT timeout)
{
HRESULT status = 0;
UINT i = 0;
UINT DataBufferSize = 0;
BYTE* DataBuffer = NULL;
IDXGIResource* DesktopResource = NULL;
if (framesWaiting > 0)
{
wf_dxgi_releasePixelData();
}
if (gAcquiredDesktopImage)
{
gAcquiredDesktopImage->Release();
gAcquiredDesktopImage = NULL;
}
status = gOutputDuplication->AcquireNextFrame(timeout, &FrameInfo, &DesktopResource);
if (status == DXGI_ERROR_WAIT_TIMEOUT)
{
return 1;
}
if (FAILED(status))
{
if (status == DXGI_ERROR_ACCESS_LOST)
{
_tprintf(_T("Failed to acquire next frame with status=%#X\n"), status);
_tprintf(_T("Trying to reinitialize due to ACCESS LOST..."));
wf_dxgi_getDuplication(0);
}
else
{
_tprintf(_T("Failed to acquire next frame with status=%#X\n"), status);
_tprintf(_T("\tAccumulated Frames: %d\n\tRects: %d\n\tBuffSize: %d\n"),
FrameInfo.AccumulatedFrames,
FrameInfo.RectsCoalesced,
FrameInfo.TotalMetadataBufferSize);
status = gOutputDuplication->ReleaseFrame();
if (FAILED(status))
{
_tprintf(_T("Failed to release frame with status=%d\n"), status);
}
return 1;
}
}
status = DesktopResource->QueryInterface(__uuidof(ID3D11Texture2D), (void**)&gAcquiredDesktopImage);
DesktopResource->Release();
DesktopResource = NULL;
if (FAILED(status))
{
return 1;
}
framesWaiting = FrameInfo.AccumulatedFrames;
return 0;
}
int wf_dxgi_getPixelData(BYTE** data, int* pitch, RECT* invalid)
{
HRESULT status;
D3D11_BOX Box;
DXGI_MAPPED_RECT mappedRect;
D3D11_TEXTURE2D_DESC tDesc;
tDesc.Width = (invalid->right - invalid->left);
tDesc.Height = (invalid->bottom - invalid->top);
tDesc.MipLevels = 1;
tDesc.ArraySize = 1;
tDesc.Format = DXGI_FORMAT_B8G8R8A8_UNORM;
tDesc.SampleDesc.Count = 1;
tDesc.SampleDesc.Quality = 0;
tDesc.Usage = D3D11_USAGE_STAGING;
tDesc.BindFlags = 0;
tDesc.CPUAccessFlags = D3D11_CPU_ACCESS_READ;
tDesc.MiscFlags = 0;
INT OffsetX = screen.left;
INT OffsetY = screen.top;
Box.top = invalid->top - OffsetY;
Box.left = invalid->left - OffsetX;
Box.right = invalid->right - OffsetX;
Box.bottom = invalid->bottom - OffsetY;
Box.front = 0;
Box.back = 1;
status = gDevice->CreateTexture2D(&tDesc, NULL, &sStage);
if (FAILED(status))
{
_tprintf(_T("Failed to create staging surface\n"));
exit(1);
return 1;
}
gContext->CopySubresourceRegion(sStage, 0, 0, 0, 0, gAcquiredDesktopImage, 0, &Box);
status = sStage->QueryInterface(__uuidof(IDXGISurface), (void**)&surf);
if (FAILED(status))
{
_tprintf(_T("Failed to QI staging surface\n"));
exit(1);
return 1;
}
surf->Map(&mappedRect, DXGI_MAP_READ);
if (FAILED(status))
{
_tprintf(_T("Failed to map staging surface\n"));
exit(1);
return 1;
}
*data = mappedRect.pBits;
*pitch = mappedRect.Pitch;
return 0;
}
int wf_dxgi_releasePixelData()
{
HRESULT status;
if (surf) {
surf->Unmap();
surf->Release();
surf = NULL;
}
if (sStage) {
sStage->Release();
sStage = NULL;
}
status = gOutputDuplication->ReleaseFrame();
if (FAILED(status))
{
_tprintf(_T("Failed to release frame\n"));
return 1;
}
framesWaiting = 0;
return 0;
}
private:
ID3D11Texture2D* gAcquiredDesktopImage;
int framesWaiting;
RECT screen;
};

49
rdp-acceleraed/WindowsCompileGuide.md
View File

@ -1,49 +0,0 @@
###To compile the server in windows WITH NVIDIA card###
- Install BOOST
- http://www.boost.org/users/download/
- I downloaded boost_1_69_0-msvc-14.1-64.exe from https://sourceforge.net/projects/boost/files/boost-binaries/1.69.0/ for Visual Studio 2017
- Install CMAKE, I took cmake-3.13.3-win64-x64.msi
- http://www.cmake.org/install/
- Install Nvidia CUDA 10.0 from https://developer.nvidia.com/cuda-downloads
- Open CMAKE
- In the field: where is the source code, have the path to the subfolder Server from RPI-GPU-rdpClient git.
- In the field: Where to build the binaries, make a subfolder build under Server
- Press configure, I selected "Visual Studio 15 2017 Win64"
- Click on Add Entry and enter BOOST_ROOT to the root of the Boost folder "C:\local\boost_1_69_0"
- Do the same for BOOST_LIBRARYDIR and set it to "C:\local\boost_1_69_0\lib64-msvc-14.1"
- I had to set CUDA_TOOLKIT_ROOT_DIR to "C:/Program Files/NVIDIA GPU Computing Toolkit/CUDA/v10.0"
- Configure and Generate
- It should look like the following:
- ![ScreenShot](https://i.imgur.com/Htlr9NP.png)
- Open Server\build\server.sln in Visual Studio
- Select Release and Build the Solution
- Open a command prompt and cd to Server\build\Release
- Run "server monitor 0 port 8080"
###To compile the server in windows WITHOUT NVIDIA card###
Note, the FPS will be significantly lower without a NVIDIA card, around 10FPS depending on the CPU.
- Install BOOST
- http://www.boost.org/users/download/
- I downloaded boost_1_60_0-msvc-10.0-32.exe from https://sourceforge.net/projects/boost/files/boost-binaries/1.60.0/ for Visual Studio 2010
- Install CMAKE, I took cmake-3.5.0-rc3-win32-x86.msi
- http://www.cmake.org/install/
- Open CMAKE
- In the field: where is the source code, have the path to the subfolder Server from RPI-GPU-rdpClient git.
- In the field: Where to build the binaries, make a subfolder build under Server
- Press configure, I selected "Visual Studio 10 2010"
- Click on Add Entry and enter BOOST_ROOT to the root of the Boost folder "C:/local/boost_1_60_0"
- Do the same for BOOST_LIBRARYDIR and set it to "C:/local/boost_1_60_0/lib32-msvc-10.0"
- Download FFMPEG from http://ffmpeg.zeranoe.com/builds/, need the dev and shared
- Set FFMPEG_ROOT to the root of FFMPEG dev folder with the README.txt
- In my case "RPI-GPU-rdpClient\ffmpeg\ffmpeg-20160307-git-6f5048f-win32-dev"
- Add the bin folder of the shared zip to your path, or copy the DLLs
- Uncheck USE_CUDA and USE_NVENC
- Only keep USE_WDDM if you have Windows 8.0 or up
- Compile and Generate
- It should look like the following:
- ![ScreenShot](http://i.imgur.com/485jCoE.png)
- Open Server\build\server.sln in Visual Studio
- Select Release and Build the Solution
- Open a command prompt and cd to Server\build\Release
- Run "server monitor 0 port 8080"
- If missing [inttypes.h], check http://stackoverflow.com/questions/13266868/ffmpeg-inttypes-h-not-found-error

20
rdp-acceleraed/win8-wddm/win8-wddm.sln
View File

@ -1,20 +0,0 @@

Microsoft Visual Studio Solution File, Format Version 11.00
# Visual Studio 2010
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "win8-wddm", "win8-wddm\win8-wddm.vcxproj", "{293FE1A0-EFBC-49A3-840A-FD94FD31C89C}"
EndProject
Global
GlobalSection(SolutionConfigurationPlatforms) = preSolution
Debug|Win32 = Debug|Win32
Release|Win32 = Release|Win32
EndGlobalSection
GlobalSection(ProjectConfigurationPlatforms) = postSolution
{293FE1A0-EFBC-49A3-840A-FD94FD31C89C}.Debug|Win32.ActiveCfg = Debug|Win32
{293FE1A0-EFBC-49A3-840A-FD94FD31C89C}.Debug|Win32.Build.0 = Debug|Win32
{293FE1A0-EFBC-49A3-840A-FD94FD31C89C}.Release|Win32.ActiveCfg = Release|Win32
{293FE1A0-EFBC-49A3-840A-FD94FD31C89C}.Release|Win32.Build.0 = Release|Win32
EndGlobalSection
GlobalSection(SolutionProperties) = preSolution
HideSolutionNode = FALSE
EndGlobalSection
EndGlobal

30
rdp-acceleraed/win8-wddm/win8-wddm/main.cpp
View File

@ -1,30 +0,0 @@
#pragma comment (lib, "d3d11.lib")
#pragma comment (lib, "Dxgi.lib")
#include <fstream>
#include "wddm.h"
using namespace std;
int main(int argc, const char* argv[]) {
WDDM wddm;
wddm.wf_dxgi_init();
byte* data;
int pitch;
RECT rect;
rect.left=0;
rect.top=0;
rect.bottom=600;
rect.right=600;
while(true) {
wddm.wf_dxgi_getPixelData(&data, &pitch, &rect);
}
system("pause");
wddm.wf_dxgi_cleanup();
}

383
rdp-acceleraed/win8-wddm/win8-wddm/wddm.h
View File

@ -1,383 +0,0 @@
#pragma once
//#pragma comment (lib, "d3dx11.lib")
//#pragma comment (lib, "d3dx10.lib")
#include <windows.h>
#include <windowsx.h>
//#define CINTERFACE
#include <DXGItype.h>
#include <D3D11.h>
#include <dxgi1_2.h>
#include <tchar.h>
/* Driver types supported */
D3D_DRIVER_TYPE DriverTypes[] =
{
D3D_DRIVER_TYPE_HARDWARE,
D3D_DRIVER_TYPE_WARP,
D3D_DRIVER_TYPE_REFERENCE,
};
UINT NumDriverTypes = ARRAYSIZE(DriverTypes);
D3D_FEATURE_LEVEL FeatureLevels[] =
{
D3D_FEATURE_LEVEL_11_0,
D3D_FEATURE_LEVEL_10_1,
D3D_FEATURE_LEVEL_10_0,
D3D_FEATURE_LEVEL_9_1
};
UINT NumFeatureLevels = ARRAYSIZE(FeatureLevels);
D3D_FEATURE_LEVEL FeatureLevel;
ID3D11Device* gDevice = NULL;
ID3D11DeviceContext* gContext = NULL;
IDXGIOutputDuplication* gOutputDuplication = NULL;
IDXGISurface* surf;
ID3D11Texture2D* sStage;
DXGI_OUTDUPL_FRAME_INFO FrameInfo;
class WDDM {
public:
int wf_dxgi_init()
{
//not sure if needed
gAcquiredDesktopImage = NULL;
if (wf_dxgi_createDevice() != 0)
{
return 1;
}
if (wf_dxgi_getDuplication(0) != 0)
{
return 1;
}
return 0;
}
int wf_dxgi_createDevice()
{
HRESULT status;
UINT DriverTypeIndex;
for (DriverTypeIndex = 0; DriverTypeIndex < NumDriverTypes; ++DriverTypeIndex)
{
status = D3D11CreateDevice(NULL, DriverTypes[DriverTypeIndex], NULL, 0, FeatureLevels, NumFeatureLevels,
D3D11_SDK_VERSION, &gDevice, &FeatureLevel, &gContext);
if (SUCCEEDED(status))
break;
_tprintf(_T("D3D11CreateDevice returned [%d] for Driver Type %d\n"), status, DriverTypes[DriverTypeIndex]);
}
if (FAILED(status))
{
_tprintf(_T("Failed to create device in InitializeDx\n"));
return 1;
}
return 0;
}
int wf_dxgi_getDuplication(UINT screenID)
{
HRESULT status;
UINT i = 0;
DXGI_OUTPUT_DESC desc;
IDXGIOutput * pOutput;
IDXGIDevice* DxgiDevice = NULL;
IDXGIAdapter* DxgiAdapter = NULL;
IDXGIOutput* DxgiOutput = NULL;
IDXGIOutput1* DxgiOutput1 = NULL;
status = gDevice->QueryInterface(__uuidof(IDXGIDevice), (void**) &DxgiDevice);
if (FAILED(status))
{
_tprintf(_T("Failed to get QI for DXGI Device\n"));
return 1;
}
status = DxgiDevice->GetParent(__uuidof(IDXGIAdapter), (void**) &DxgiAdapter);
DxgiDevice->Release();
DxgiDevice = NULL;
if (FAILED(status))
{
_tprintf(_T("Failed to get parent DXGI Adapter\n"));
return 1;
}
ZeroMemory(&desc, sizeof(desc));
pOutput = NULL;
while (DxgiAdapter->EnumOutputs(i, &pOutput) != DXGI_ERROR_NOT_FOUND)
{
DXGI_OUTPUT_DESC* pDesc = &desc;
status = pOutput->GetDesc(pDesc);
if (FAILED(status))
{
_tprintf(_T("Failed to get description\n"));
return 1;
}
_tprintf(_T("Output %d: [%s] [%d]\n"), i, pDesc->DeviceName, pDesc->AttachedToDesktop);
/*if (pDesc->AttachedToDesktop)
dTop = i;*/
pOutput->Release();
++i;
}
status = DxgiAdapter->EnumOutputs(screenID, &DxgiOutput);
DxgiAdapter->Release();
DxgiAdapter = NULL;
if (FAILED(status))
{
_tprintf(_T("Failed to get output\n"));
return 1;
}
status = DxgiOutput->QueryInterface(__uuidof(IDXGIOutput1), (void**) &DxgiOutput1);
DxgiOutput->Release();
DxgiOutput = NULL;
if (FAILED(status))
{
_tprintf(_T("Failed to get IDXGIOutput1\n"));
return 1;
}
status = DxgiOutput1->DuplicateOutput((IUnknown*)gDevice, &gOutputDuplication);
DxgiOutput1->Release();
DxgiOutput1 = NULL;
if (FAILED(status))
{
if (status == DXGI_ERROR_NOT_CURRENTLY_AVAILABLE)
{
_tprintf(_T("There is already the maximum number of applications using the Desktop Duplication API running, please close one of those applications and then try again.\n"));
return 1;
}
_tprintf(_T("Failed to get duplicate output. Status = %#X\n"), status);
return 1;
}
return 0;
}
int wf_dxgi_cleanup()
{
/*if (framesWaiting > 0)
{
wf_dxgi_releasePixelData(wfi);
}*/
if (gAcquiredDesktopImage)
{
gAcquiredDesktopImage->Release();
gAcquiredDesktopImage = NULL;
}
if (gOutputDuplication)
{
gOutputDuplication->Release();
gOutputDuplication = NULL;
}
if(gContext)
{
gContext->Release();
gContext = NULL;
}
if(gDevice)
{
gDevice->Release();
gDevice = NULL;
}
return 0;
}
int wf_dxgi_nextFrame(UINT timeout)
{
HRESULT status = 0;
UINT i = 0;
UINT DataBufferSize = 0;
BYTE* DataBuffer = NULL;
IDXGIResource* DesktopResource = NULL;
if (gAcquiredDesktopImage)
{
gAcquiredDesktopImage->Release();
gAcquiredDesktopImage = NULL;
}
status = gOutputDuplication->AcquireNextFrame(timeout, &FrameInfo, &DesktopResource);
if (status == DXGI_ERROR_WAIT_TIMEOUT)
{
return 1;
}
if (FAILED(status))
{
if (status == DXGI_ERROR_ACCESS_LOST)
{
_tprintf(_T("Failed to acquire next frame with status=%#X\n"), status);
_tprintf(_T("Trying to reinitialize due to ACCESS LOST..."));
if (gAcquiredDesktopImage)
{
gAcquiredDesktopImage->Release();
gAcquiredDesktopImage = NULL;
}
if (gOutputDuplication)
{
gOutputDuplication->Release();
gOutputDuplication = NULL;
}
wf_dxgi_getDuplication(0); // TODO
return 1;
}
else
{
_tprintf(_T("Failed to acquire next frame with status=%#X\n"), status);
status = gOutputDuplication->ReleaseFrame();
if (FAILED(status))
{
_tprintf(_T("Failed to release frame with status=%d\n"), status);
}
return 1;
}
}
status = DesktopResource->QueryInterface(__uuidof(ID3D11Texture2D), (void**) &gAcquiredDesktopImage);
DesktopResource->Release();
DesktopResource = NULL;
if (FAILED(status))
{
return 1;
}
//wfi->framesWaiting = FrameInfo.AccumulatedFrames;
if (FrameInfo.AccumulatedFrames == 0)
{
status = gOutputDuplication->ReleaseFrame();
if (FAILED(status))
{
_tprintf(_T("Failed to release frame with status=%d\n"), status);
}
}
return 0;
}
int wf_dxgi_getPixelData(BYTE** data, int* pitch, RECT* invalid)
{
HRESULT status;
D3D11_BOX Box;
DXGI_MAPPED_RECT mappedRect;
D3D11_TEXTURE2D_DESC tDesc;
tDesc.Width = (invalid->right - invalid->left);
tDesc.Height = (invalid->bottom - invalid->top);
tDesc.MipLevels = 1;
tDesc.ArraySize = 1;
tDesc.Format = DXGI_FORMAT_B8G8R8A8_UNORM;
tDesc.SampleDesc.Count = 1;
tDesc.SampleDesc.Quality = 0;
tDesc.Usage = D3D11_USAGE_STAGING;
tDesc.BindFlags = 0;
tDesc.CPUAccessFlags = D3D11_CPU_ACCESS_READ;
tDesc.MiscFlags = 0;
Box.top = invalid->top;
Box.left = invalid->left;
Box.right = invalid->right;
Box.bottom = invalid->bottom;
Box.front = 0;
Box.back = 1;
status = gDevice->CreateTexture2D(&tDesc, NULL, &sStage);
if (FAILED(status))
{
_tprintf(_T("Failed to create staging surface\n"));
exit(1);
return 1;
}
gContext->CopySubresourceRegion((ID3D11Resource*) sStage, 0,0,0,0, (ID3D11Resource*) gAcquiredDesktopImage, 0, &Box);
status = sStage->QueryInterface(_uuidof(IDXGISurface), (void**) &surf);
if (FAILED(status))
{
_tprintf(_T("Failed to QI staging surface\n"));
exit(1);
return 1;
}
surf->Map(&mappedRect, DXGI_MAP_READ);
if (FAILED(status))
{
_tprintf(_T("Failed to map staging surface\n"));
exit(1);
return 1;
}
*data = mappedRect.pBits;
*pitch = mappedRect.Pitch;
return 0;
}
int wf_dxgi_releasePixelData()
{
HRESULT status;
surf->Unmap();
surf->Release();
surf = NULL;
sStage->Release();
sStage = NULL;
status = gOutputDuplication->ReleaseFrame();
if (FAILED(status))
{
_tprintf(_T("Failed to release frame\n"));
return 1;
}
//wfi->framesWaiting = 0;
return 0;
}
private:
ID3D11Texture2D* gAcquiredDesktopImage;
};

27
rdp-acceleraed/win8-wddm/win8-wddm/win8-wddm.vcxproj.filters
View File

@ -1,27 +0,0 @@
<?xml version="1.0" encoding="utf-8"?>
<Project ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
<ItemGroup>
<Filter Include="Source Files">
<UniqueIdentifier>{4FC737F1-C7A5-4376-A066-2A32D752A2FF}</UniqueIdentifier>
<Extensions>cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx</Extensions>
</Filter>
<Filter Include="Header Files">
<UniqueIdentifier>{93995380-89BD-4b04-88EB-625FBE52EBFB}</UniqueIdentifier>
<Extensions>h;hpp;hxx;hm;inl;inc;xsd</Extensions>
</Filter>
<Filter Include="Resource Files">
<UniqueIdentifier>{67DA6AB6-F800-4c08-8B7A-83BB121AAD01}</UniqueIdentifier>
<Extensions>rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms</Extensions>
</Filter>
</ItemGroup>
<ItemGroup>
<ClCompile Include="main.cpp">
<Filter>Source Files</Filter>
</ClCompile>
</ItemGroup>
<ItemGroup>
<ClInclude Include="wddm.h">
<Filter>Header Files</Filter>
</ClInclude>
</ItemGroup>
</Project>

37
temp-telegraf/README.md
View File

@ -1,37 +0,0 @@
# raspberrypi-temperature-telegraf
Collect RaspberryPi CPU and GPU temperature with telegraf
### How to use (No script required :fire:)
1. Add this to you telegraf.conf
```
[[inputs.file]]
files = ["/sys/class/thermal/thermal_zone0/temp"]
name_override = "cpu_temperature"
data_format = "value"
data_type = "integer"
[[inputs.exec]]
commands = [ "/opt/vc/bin/vcgencmd measure_temp" ]
name_override = "gpu_temperature"
data_format = "grok"
grok_patterns = ["%{NUMBER:value:float}"]
```
2. Add telegraf user to video group ```sudo usermod -a -G video telegraf```
3. ```sudo service telegraf stop;sudo service telegraf start```
4. Run test ```telegraf -config /etc/telegraf/telegraf.conf -test```
### How to use (Old way)
1. Copy ```telegraf_pi_temp.sh``` to ```/usr/local/bin/telegraf_pi_temp.sh```
2. Modify file permissions ```chmod +x /usr/local/bin/telegraf_pi_temp.sh```
3. Add ```telegraf``` user to video group ```sudo usermod -a -G video telegraf```
4. ```sudo service telegraf restart``` or ```sudo reboot```
5. Add to your telegraf.conf snippet from ```telegraf.conf```
6. Run test ```telegraf -config /etc/telegraf/telegraf.conf -test```
### Data format
To get a human readable *cpu* temperature divide it by 1000 (in grafana use the math(/ 1000) function
```json
{"cpu":54768, "gpu":54.8}
```
<img src="http://i.imgur.com/tnenohv.png" width="700">

5
temp-telegraf/telegraf.conf
View File

@ -1,5 +0,0 @@
[[inputs.exec]]
commands = ["/usr/local/bin/telegraf_pi_temp.sh"]
timeout = "5s"
data_format = "json"
name_suffix = "_pi_temp"

7
temp-telegraf/telegraf_pi_temp.sh
View File

@ -1,7 +0,0 @@
#!/bin/bash
prefix="temp="
suffix="'C"
gpu=$(/opt/vc/bin/vcgencmd measure_temp)
gpu_temp=${gpu#$prefix}
gpu_temp=${gpu_temp%$suffix}
echo -e "{\"cpu\":"$(</sys/class/thermal/thermal_zone0/temp)", \"gpu\":$gpu_temp}"