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VPU clock updates

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This commit is contained in:
Scare Crowe 2021-11-09 17:00:25 +05:00
parent 4005042dcf
commit 705e114f25
6 changed files with 43 additions and 18 deletions
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2
Overclock Essentials.txt
View File

@ -1,3 +1,5 @@
This is now deprecated as Sinclar uses auto adaptive over clocking.
Check what is your actual stable stock clock
vcgencmd measure_clock arm
Check temps on stock heatsink or with fan

15
drivers/clk/bcm/clk-bcm2835.c
View File

@ -2208,21 +2208,6 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
.frac_bits = 12,
.tcnt_mux = 28),
/* TV encoder clock. Only operating frequency is 108Mhz. */
[BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
SOC_ALL,
.name = "vec",
.ctl_reg = CM_VECCTL,
.div_reg = CM_VECDIV,
.int_bits = 4,
.frac_bits = 0,
/*
* Allow rate change propagation only on PLLH_AUX which is
* assigned index 7 in the parent array.
*/
.set_rate_parent = BIT(7),
.tcnt_mux = 29),
/* dsi clocks */
[BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
SOC_ALL,

3
drivers/clk/bcm/clk-raspberrypi.c
View File

@ -33,6 +33,7 @@ enum rpi_firmware_clk_id {
RPI_FIRMWARE_EMMC2_CLK_ID,
RPI_FIRMWARE_M2MC_CLK_ID,
RPI_FIRMWARE_PIXEL_BVB_CLK_ID,
RPI_FIRMWARE_VEC_CLK_ID,
RPI_FIRMWARE_NUM_CLK_ID,
};
@ -51,6 +52,7 @@ static char *rpi_firmware_clk_names[] = {
[RPI_FIRMWARE_EMMC2_CLK_ID] = "emmc2",
[RPI_FIRMWARE_M2MC_CLK_ID] = "m2mc",
[RPI_FIRMWARE_PIXEL_BVB_CLK_ID] = "pixel-bvb",
[RPI_FIRMWARE_VEC_CLK_ID] = "vec",
};
#define RPI_FIRMWARE_STATE_ENABLE_BIT BIT(0)
@ -273,6 +275,7 @@ static int raspberrypi_discover_clocks(struct raspberrypi_clk *rpi,
case RPI_FIRMWARE_V3D_CLK_ID:
case RPI_FIRMWARE_HEVC_CLK_ID:
case RPI_FIRMWARE_PIXEL_BVB_CLK_ID:
case RPI_FIRMWARE_VEC_CLK_ID:
hw = raspberrypi_clk_register(rpi, clks->parent,
clks->id);
if (IS_ERR(hw))

14
drivers/media/firewire/firedtv-avc.c
View File

@ -1165,7 +1165,11 @@ int avc_ca_pmt(struct firedtv *fdtv, char *msg, int length)
read_pos += program_info_length;
write_pos += program_info_length;
}
while (read_pos < length) {
while (read_pos + 4 < length) {
if (write_pos + 4 >= sizeof(c->operand) - 4) {
ret = -EINVAL;
goto out;
}
c->operand[write_pos++] = msg[read_pos++];
c->operand[write_pos++] = msg[read_pos++];
c->operand[write_pos++] = msg[read_pos++];
@ -1177,13 +1181,17 @@ int avc_ca_pmt(struct firedtv *fdtv, char *msg, int length)
c->operand[write_pos++] = es_info_length >> 8;
c->operand[write_pos++] = es_info_length & 0xff;
if (es_info_length > 0) {
if (read_pos >= length) {
ret = -EINVAL;
goto out;
}
pmt_cmd_id = msg[read_pos++];
if (pmt_cmd_id != 1 && pmt_cmd_id != 4)
dev_err(fdtv->device, "invalid pmt_cmd_id %d at stream level\n",
pmt_cmd_id);
if (es_info_length > sizeof(c->operand) - 4 -
write_pos) {
if (es_info_length > sizeof(c->operand) - 4 - write_pos ||
es_info_length > length - read_pos) {
ret = -EINVAL;
goto out;
}

2
drivers/media/firewire/firedtv-ci.c
View File

@ -134,6 +134,8 @@ static int fdtv_ca_pmt(struct firedtv *fdtv, void *arg)
} else {
data_length = msg->msg[3];
}
if (data_length > sizeof(msg->msg) - data_pos)
return -EINVAL;
return avc_ca_pmt(fdtv, &msg->msg[data_pos], data_length);
}

25
drivers/media/i2c/imx477.c
View File

@ -25,6 +25,10 @@ static int dpc_enable = 1;
module_param(dpc_enable, int, 0644);
MODULE_PARM_DESC(dpc_enable, "Enable on-sensor DPC");
static int trigger_mode;
module_param(trigger_mode, int, 0644);
MODULE_PARM_DESC(trigger_mode, "Set vsync trigger mode: 1=source, 2=sink");
#define IMX477_REG_VALUE_08BIT 1
#define IMX477_REG_VALUE_16BIT 2
@ -98,6 +102,12 @@ MODULE_PARM_DESC(dpc_enable, "Enable on-sensor DPC");
#define IMX477_TEST_PATTERN_B_DEFAULT 0
#define IMX477_TEST_PATTERN_GB_DEFAULT 0
/* Trigger mode */
#define IMX477_REG_MC_MODE 0x3f0b
#define IMX477_REG_MS_SEL 0x3041
#define IMX477_REG_XVS_IO_CTRL 0x3040
#define IMX477_REG_EXTOUT_EN 0x4b81
/* Embedded metadata stream structure */
#define IMX477_EMBEDDED_LINE_WIDTH 16384
#define IMX477_NUM_EMBEDDED_LINES 1
@ -1721,6 +1731,21 @@ static int imx477_start_streaming(struct imx477 *imx477)
imx477_write_reg(imx477, 0x0b05, IMX477_REG_VALUE_08BIT, !!dpc_enable);
imx477_write_reg(imx477, 0x0b06, IMX477_REG_VALUE_08BIT, !!dpc_enable);
/* Set vsync trigger mode */
if (trigger_mode != 0) {
/* trigger_mode == 1 for source, 2 for sink */
const u32 val = (trigger_mode == 1) ? 1 : 0;
imx477_write_reg(imx477, IMX477_REG_MC_MODE,
IMX477_REG_VALUE_08BIT, 1);
imx477_write_reg(imx477, IMX477_REG_MS_SEL,
IMX477_REG_VALUE_08BIT, val);
imx477_write_reg(imx477, IMX477_REG_XVS_IO_CTRL,
IMX477_REG_VALUE_08BIT, val);
imx477_write_reg(imx477, IMX477_REG_EXTOUT_EN,
IMX477_REG_VALUE_08BIT, val);
}
/* Apply customized values from user */
ret = __v4l2_ctrl_handler_setup(imx477->sd.ctrl_handler);
if (ret)