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T3Q gets dumped cuz he wanks the clowns he cries his lies to.

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This commit is contained in:
Scare Crowe 2021-10-26 22:35:21 +05:00
parent 3627ab3398
commit a68fed6dd5
1120 changed files with 60293 additions and 27052 deletions
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38
mesa 3D driver/.gitlab-ci.yml
View File

@ -12,6 +12,9 @@ variables:
JOB_ARTIFACTS_BASE: ${PIPELINE_ARTIFACTS_BASE}/${CI_JOB_ID}
# reference images stored for traces
PIGLIT_REPLAY_REFERENCE_IMAGES_BASE: "${MINIO_HOST}/mesa-tracie-results/$FDO_UPSTREAM_REPO"
# Individual CI farm status, set to "offline" to disable jobs
# running on a particular CI farm (ie. for outages, etc):
FD_FARM: "online"
include:
- project: 'freedesktop/ci-templates'
@ -27,22 +30,22 @@ include:
- local: '.gitlab-ci/test-source-dep.yml'
- local: 'src/amd/ci/gitlab-ci.yml'
- local: 'src/broadcom/ci/gitlab-ci.yml'
- local: 'src/etnaviv/ci/gitlab-ci.yml'
- local: 'src/freedreno/ci/gitlab-ci.yml'
- local: 'src/gallium/drivers/i915/ci/gitlab-ci.yml'
- local: 'src/gallium/drivers/iris/ci/gitlab-ci.yml'
- local: 'src/gallium/drivers/lima/ci/gitlab-ci.yml'
- local: 'src/gallium/drivers/llvmpipe/ci/gitlab-ci.yml'
- local: 'src/gallium/drivers/panfrost/ci/gitlab-ci.yml'
- local: 'src/gallium/drivers/radeonsi/ci/gitlab-ci.yml'
- local: 'src/gallium/drivers/softpipe/ci/gitlab-ci.yml'
- local: 'src/gallium/drivers/virgl/ci/gitlab-ci.yml'
- local: 'src/gallium/drivers/zink/ci/gitlab-ci.yml'
- local: 'src/gallium/frontends/lavapipe/ci/gitlab-ci.yml'
- local: 'src/panfrost/ci/gitlab-ci.yml'
stages:
- sanity
- container
- container-2
- git-archive
- build-x86_64
- build-misc
@ -51,6 +54,7 @@ stages:
- arm
- broadcom
- freedreno
- etnaviv
- software-renderer
- layered-backends
- deploy
@ -202,8 +206,10 @@ test-docs-mr:
FDO_DISTRIBUTION_TAG: "${MESA_IMAGE_TAG}--${MESA_BASE_TAG}--${MESA_TEMPLATES_COMMIT}"
.set-image:
extends:
- .incorporate-templates-commit
variables:
MESA_IMAGE: "$CI_REGISTRY_IMAGE/${MESA_IMAGE_PATH}:${MESA_IMAGE_TAG}--${MESA_TEMPLATES_COMMIT}"
MESA_IMAGE: "$CI_REGISTRY_IMAGE/${MESA_IMAGE_PATH}:${FDO_DISTRIBUTION_TAG}"
image: "$MESA_IMAGE"
.set-image-base-tag:
@ -211,7 +217,7 @@ test-docs-mr:
- .set-image
- .incorporate-base-tag+templates-commit
variables:
MESA_IMAGE: "$CI_REGISTRY_IMAGE/${MESA_IMAGE_PATH}:${MESA_IMAGE_TAG}--${MESA_BASE_TAG}--${MESA_TEMPLATES_COMMIT}"
MESA_IMAGE: "$CI_REGISTRY_IMAGE/${MESA_IMAGE_PATH}:${FDO_DISTRIBUTION_TAG}"
# Build the CI docker images.
@ -277,7 +283,6 @@ test-docs-mr:
- .incorporate-base-tag+templates-commit
# Don't want the .container rules
- .ci-run-policy
stage: container-2
# Debian 11 based x86 build image base
debian/x86_build-base:
@ -387,7 +392,7 @@ debian/android_build:
debian/x86_test-base:
extends: debian/x86_build-base
variables:
MESA_IMAGE_TAG: &debian-x86_test-base "2021-07-26-python"
MESA_IMAGE_TAG: &debian-x86_test-base "2021-09-28-deqp-runner"
.use-debian/x86_test-base:
extends:
@ -404,14 +409,14 @@ debian/x86_test-gl:
extends: .use-debian/x86_test-base
variables:
FDO_DISTRIBUTION_EXEC: 'env KERNEL_URL=${KERNEL_URL} FDO_CI_CONCURRENT=${FDO_CI_CONCURRENT} bash .gitlab-ci/container/${CI_JOB_NAME}.sh'
KERNEL_URL: &kernel-rootfs-url "https://gitlab.freedesktop.org/gfx-ci/linux/-/archive/v5.13-rc5-for-mesa-ci-27df41f1e0cf/linux-v5.13-rc5-for-mesa-ci-27df41f1e0cf.tar.bz2"
MESA_IMAGE_TAG: &debian-x86_test-gl "2021-08-04-latest-virglrenderer"
KERNEL_URL: &kernel-rootfs-url "https://gitlab.freedesktop.org/gfx-ci/linux/-/archive/v5.13-rc5-for-mesa-ci-2bb5d9ffd79c/linux-v5.13-rc5-for-mesa-ci-2bb5d9ffd79c.tar.bz2"
MESA_IMAGE_TAG: &debian-x86_test-gl "2021-2021-10-07-piglit"
# Debian 11 based x86 test image for VK
debian/x86_test-vk:
extends: .use-debian/x86_test-base
variables:
MESA_IMAGE_TAG: &debian-x86_test-vk "2021-07-30-piglit-2"
MESA_IMAGE_TAG: &debian-x86_test-vk "2021-2021-10-07-piglit"
# Debian 11 based ARM build image
debian/arm_build:
@ -456,11 +461,11 @@ fedora/x86_build:
.kernel+rootfs:
extends:
- .ci-run-policy
stage: container-2
stage: container
variables:
GIT_STRATEGY: fetch
KERNEL_URL: *kernel-rootfs-url
MESA_ROOTFS_TAG: &kernel-rootfs "2021-08-07-enable-lima"
MESA_ROOTFS_TAG: &kernel-rootfs "2021-10-07-piglit"
DISTRIBUTION_TAG: &distribution-tag-arm "${MESA_ROOTFS_TAG}--${MESA_ARTIFACTS_TAG}--${MESA_TEMPLATES_COMMIT}"
script:
- .gitlab-ci/container/lava_build.sh
@ -507,7 +512,6 @@ debian/arm_test:
- .container
# Don't want the .container rules
- .ci-run-policy
stage: build-misc
needs:
- kernel+rootfs_arm64
- kernel+rootfs_armhf
@ -515,7 +519,7 @@ debian/arm_test:
FDO_DISTRIBUTION_EXEC: 'env ARTIFACTS_PREFIX=https://${MINIO_HOST}/mesa-lava ARTIFACTS_SUFFIX=${MESA_ROOTFS_TAG}--${MESA_ARM_BUILD_TAG}--${MESA_TEMPLATES_COMMIT} CI_PROJECT_PATH=${CI_PROJECT_PATH} FDO_CI_CONCURRENT=${FDO_CI_CONCURRENT} FDO_UPSTREAM_REPO=${FDO_UPSTREAM_REPO} bash .gitlab-ci/container/${CI_JOB_NAME}.sh'
FDO_DISTRIBUTION_TAG: "${MESA_IMAGE_TAG}--${MESA_ROOTFS_TAG}--${MESA_ARM_BUILD_TAG}--${MESA_TEMPLATES_COMMIT}"
MESA_ARM_BUILD_TAG: *debian-arm_build
MESA_IMAGE_TAG: &debian-arm_test "2021-07-26-python"
MESA_IMAGE_TAG: &debian-arm_test "2021-09-17-deqp"
MESA_ROOTFS_TAG: *kernel-rootfs
.use-debian/arm_test:
@ -750,7 +754,6 @@ debian-gallium:
script:
- .gitlab-ci/meson/build.sh
- .gitlab-ci/run-shader-db.sh
- src/freedreno/.gitlab-ci/run-fdtools.sh
# Test a release build with -Werror so new warnings don't sneak in.
debian-release:
@ -774,6 +777,7 @@ debian-release:
-D gallium-opencl=disabled
-D llvm=false
GALLIUM_DRIVERS: "i915,iris,nouveau,kmsro,freedreno,r300,svga,swrast,v3d,vc4,virgl,etnaviv,panfrost,lima,zink,d3d12,crocus"
VULKAN_DRIVERS: "amd"
BUILDTYPE: "release"
EXTRA_OPTION: >
-D osmesa=true
@ -931,7 +935,7 @@ debian-arm64:
- .meson-arm
- .ci-deqp-artifacts
variables:
VULKAN_DRIVERS: "freedreno,broadcom"
VULKAN_DRIVERS: "freedreno,broadcom,panfrost"
EXTRA_OPTION: >
-D llvm=disabled
-D valgrind=false
@ -1333,7 +1337,7 @@ debian-mingw32-x86_64:
.baremetal-arm64-asan-test:
variables:
TEST_LD_PRELOAD: libasan.so.6
DEQP_RUNNER_OPTIONS: "--env LD_PRELOAD=libasan.so.6"
MINIO_ARTIFACT_NAME: mesa-arm64-asan
needs:
- debian/arm_test
@ -1343,4 +1347,4 @@ debian-mingw32-x86_64:
.baremetal-deqp-test:
variables:
HWCI_TEST_SCRIPT: "/install/deqp-runner.sh"
DEQP_PARALLEL: 0 # Default to number of CPUs
FDO_CI_CONCURRENT: 0 # Default to number of CPUs

138
mesa 3D driver/CODEOWNERS Normal file
View File

@ -0,0 +1,138 @@
# This file contains the GitLab handle of the maintainers/reviewers for
# a given file:
# https://docs.gitlab.com/ce/user/project/code_owners.html
#
# Consider these as the list of people who want to be involved in MRs
# touching these files/folders, and whom you can ask your questions and
# tag in issues.
#
# As of GitLab 14.3, all features surrounding this file are premium-only,
# which means this file is only read by humans for now.
#
# Paths starting with a `/` are relative to the git root, otherwise they
# can match any substring of the file's path.
# If multiple lines match, only the last one applies; there is no
# accumulation.
##################
# INFRASTRUCTURE #
##################
# Build system - Meson
meson.build @dbaker @eric
/meson_options.txt @dbaker @eric
/docs/meson.rst @dbaker @eric
# Build system - Android
/android/ @roman.stratiienko
# Compatibility headers
/include/c99* @evelikov
/include/c11* @eric
# Documentation
/docs/ @eric @evelikov
##########
# COMMON #
##########
# NIR
/src/compiler/nir/ @jekstrand
# Vulkan
/src/vulkan/ @eric @jekstrand
/include/vulkan/ @eric @jekstrand
#############
# PLATFORMS #
#############
# EGL
/src/egl/ @eric @evelikov
/include/EGL/ @eric @evelikov
# EGL - Android support
/src/egl/drivers/dri2/platform_android.c @robh @tfiga
# EGL - Device support
/src/egl/drivers/dri2/platform_device.c @evelikov
# EGL - Wayland support
/src/egl/wayland/ @daniels @eric
/src/egl/drivers/dri2/platform_wayland.c @daniels @eric
# Gallium targets
/src/gallium/targets/ @evelikov
# GLX
/src/glx/ @ajax
/include/GL/glx* @ajax
# GLVND
/src/egl/main/eglglvnd.c @kbrenneman
/src/egl/main/egldispatchstubs.* @kbrenneman
/src/egl/generate/ @kbrenneman
/src/glx/*glvnd* @kbrenneman
# Haiku
/include/HaikuGL/ @kallisti5
/src/egl/drivers/haiku/ @kallisti5
/src/gallium/frontends/hgl/ @kallisti5
/src/gallium/targets/haiku-softpipe/ @kallisti5
/src/gallium/winsys/sw/hgl/ @kallisti5
/src/hgl/ @kallisti5
# Loader - DRI/classic
/src/loader/ @evelikov
# Loader - Gallium
/src/gallium/auxiliary/pipe-loader/ @evelikov
/src/gallium/auxiliary/target-helpers/ @evelikov
# Vulkan WSI - Display
/src/vulkan/wsi/wsi_common_display.* @keithp
/src/*/vulkan/*_wsi_display.c @keithp
###########
# Drivers #
###########
# Asahi
/src/asahi/ @alyssa
/src/gallium/drivers/asahi/ @alyssa
# Freedreno
/src/gallium/drivers/freedreno/ @robclark
# Intel
/include/drm-uapi/i915_drm.h @kwg @llandwerlin @jekstrand @idr
/include/pci_ids/i*_pci_ids.h @kwg @llandwerlin @jekstrand @idr
/src/intel/ @kwg @llandwerlin @jekstrand @idr
/src/gallium/winsys/iris/ @kwg @llandwerlin @jekstrand @idr
/src/gallium/drivers/iris/ @kwg @llandwerlin @jekstrand @idr
/src/gallium/drivers/i915/ @anholt
/src/mesa/drivers/dri/i965/ @kwg @llandwerlin @jekstrand @idr
/doxygen/i965.doxy @kwg @llandwerlin @jekstrand @idr
# Microsoft
/src/microsoft/ @jenatali
/src/gallium/drivers/d3d12/ @jenatali
# Panfrost
/src/panfrost/ @alyssa
/src/panfrost/vulkan/ @bbrezillon
/src/gallium/drivers/panfrost/ @alyssa
# SWR
/src/gallium/drivers/swr/ @jzielins @krzysztof.raszkowski
/docs/gallium/drivers/openswr.rst @jzielins @krzysztof.raszkowski
/docs/gallium/drivers/openswr/ @jzielins @krzysztof.raszkowski
# VMware
/src/gallium/drivers/svga/ @brianp @charmainel
/src/gallium/winsys/svga/ @thomash @drawat

2
mesa 3D driver/VERSION
View File

@ -1 +1 @@
21.3.0-devel
22.0.0-devel

82
mesa 3D driver/bin/khronos-update.py
View File

@ -47,7 +47,7 @@ SOURCES = [
'api': 'khr',
'inc_folder': 'KHR',
'sources': [
Source('include/KHR/khrplatform.h', 'https://github.com/KhronosGroup/EGL-Registry/raw/master/api/KHR/khrplatform.h'),
Source('include/KHR/khrplatform.h', 'https://github.com/KhronosGroup/EGL-Registry/raw/main/api/KHR/khrplatform.h'),
],
},
@ -55,10 +55,10 @@ SOURCES = [
'api': 'egl',
'inc_folder': 'EGL',
'sources': [
Source('src/egl/generate/egl.xml', 'https://github.com/KhronosGroup/EGL-Registry/raw/master/api/egl.xml'),
Source('include/EGL/egl.h', 'https://github.com/KhronosGroup/EGL-Registry/raw/master/api/EGL/egl.h'),
Source('include/EGL/eglplatform.h', 'https://github.com/KhronosGroup/EGL-Registry/raw/master/api/EGL/eglplatform.h'),
Source('include/EGL/eglext.h', 'https://github.com/KhronosGroup/EGL-Registry/raw/master/api/EGL/eglext.h'),
Source('src/egl/generate/egl.xml', 'https://github.com/KhronosGroup/EGL-Registry/raw/main/api/egl.xml'),
Source('include/EGL/egl.h', 'https://github.com/KhronosGroup/EGL-Registry/raw/main/api/EGL/egl.h'),
Source('include/EGL/eglplatform.h', 'https://github.com/KhronosGroup/EGL-Registry/raw/main/api/EGL/eglplatform.h'),
Source('include/EGL/eglext.h', 'https://github.com/KhronosGroup/EGL-Registry/raw/main/api/EGL/eglext.h'),
Source('include/EGL/eglextchromium.h', 'https://chromium.googlesource.com/chromium/src/+/refs/heads/master/ui/gl/EGL/eglextchromium.h?format=TEXT'),
Source('include/EGL/eglext_angle.h', 'https://chromium.googlesource.com/angle/angle/+/refs/heads/master/include/EGL/eglext_angle.h?format=TEXT'),
Source('include/EGL/eglmesaext.h', None),
@ -69,11 +69,11 @@ SOURCES = [
'api': 'gl',
'inc_folder': 'GL',
'sources': [
Source('src/mapi/glapi/registry/gl.xml', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/master/xml/gl.xml'),
Source('include/GL/glcorearb.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/master/api/GL/glcorearb.h'),
Source('include/GL/glext.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/master/api/GL/glext.h'),
Source('include/GL/glxext.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/master/api/GL/glxext.h'),
Source('include/GL/wglext.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/master/api/GL/wglext.h'),
Source('src/mapi/glapi/registry/gl.xml', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/main/xml/gl.xml'),
Source('include/GL/glcorearb.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/main/api/GL/glcorearb.h'),
Source('include/GL/glext.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/main/api/GL/glext.h'),
Source('include/GL/glxext.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/main/api/GL/glxext.h'),
Source('include/GL/wglext.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/main/api/GL/wglext.h'),
Source('include/GL/gl.h', None), # FIXME: I don't know what the canonical source is
Source('include/GL/glx.h', None), # FIXME: I don't know what the canonical source is
Source('include/GL/internal/', None),
@ -86,10 +86,10 @@ SOURCES = [
'api': 'gles1',
'inc_folder': 'GLES',
'sources': [
Source('include/GLES/gl.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/master/api/GLES/gl.h'),
Source('include/GLES/glplatform.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/master/api/GLES/glplatform.h'),
Source('include/GLES/glext.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/master/api/GLES/glext.h'),
Source('include/GLES/egl.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/master/api/GLES/egl.h'),
Source('include/GLES/gl.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/main/api/GLES/gl.h'),
Source('include/GLES/glplatform.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/main/api/GLES/glplatform.h'),
Source('include/GLES/glext.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/main/api/GLES/glext.h'),
Source('include/GLES/egl.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/main/api/GLES/egl.h'),
],
},
@ -97,9 +97,9 @@ SOURCES = [
'api': 'gles2',
'inc_folder': 'GLES2',
'sources': [
Source('include/GLES2/gl2.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/master/api/GLES2/gl2.h'),
Source('include/GLES2/gl2platform.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/master/api/GLES2/gl2platform.h'),
Source('include/GLES2/gl2ext.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/master/api/GLES2/gl2ext.h'),
Source('include/GLES2/gl2.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/main/api/GLES2/gl2.h'),
Source('include/GLES2/gl2platform.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/main/api/GLES2/gl2platform.h'),
Source('include/GLES2/gl2ext.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/main/api/GLES2/gl2ext.h'),
],
},
@ -107,10 +107,10 @@ SOURCES = [
'api': 'gles3',
'inc_folder': 'GLES3',
'sources': [
Source('include/GLES3/gl3.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/master/api/GLES3/gl3.h'),
Source('include/GLES3/gl31.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/master/api/GLES3/gl31.h'),
Source('include/GLES3/gl32.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/master/api/GLES3/gl32.h'),
Source('include/GLES3/gl3platform.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/master/api/GLES3/gl3platform.h'),
Source('include/GLES3/gl3.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/main/api/GLES3/gl3.h'),
Source('include/GLES3/gl31.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/main/api/GLES3/gl31.h'),
Source('include/GLES3/gl32.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/main/api/GLES3/gl32.h'),
Source('include/GLES3/gl3platform.h', 'https://github.com/KhronosGroup/OpenGL-Registry/raw/main/api/GLES3/gl3platform.h'),
Source('include/GLES3/gl3ext.h', None), # FIXME: I don't know what the canonical source is
],
},
@ -155,25 +155,27 @@ SOURCES = [
'api': 'vulkan',
'inc_folder': 'vulkan',
'sources': [
Source('src/vulkan/registry/vk.xml', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/master/registry/vk.xml'),
Source('include/vulkan/vulkan.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/master/include/vulkan/vulkan.h'),
Source('include/vulkan/vulkan_core.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/master/include/vulkan/vulkan_core.h'),
Source('include/vulkan/vulkan_beta.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/master/include/vulkan/vulkan_beta.h'),
Source('include/vulkan/vk_icd.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/master/include/vulkan/vk_icd.h'),
Source('include/vulkan/vk_layer.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/master/include/vulkan/vk_layer.h'),
Source('include/vulkan/vk_platform.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/master/include/vulkan/vk_platform.h'),
Source('include/vulkan/vulkan_android.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/master/include/vulkan/vulkan_android.h'),
Source('include/vulkan/vulkan_fuchsia.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/master/include/vulkan/vulkan_fuchsia.h'),
Source('include/vulkan/vulkan_ggp.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/master/include/vulkan/vulkan_ggp.h'),
Source('include/vulkan/vulkan_ios.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/master/include/vulkan/vulkan_ios.h'),
Source('include/vulkan/vulkan_macos.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/master/include/vulkan/vulkan_macos.h'),
Source('include/vulkan/vulkan_metal.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/master/include/vulkan/vulkan_metal.h'),
Source('include/vulkan/vulkan_vi.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/master/include/vulkan/vulkan_vi.h'),
Source('include/vulkan/vulkan_wayland.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/master/include/vulkan/vulkan_wayland.h'),
Source('include/vulkan/vulkan_win32.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/master/include/vulkan/vulkan_win32.h'),
Source('include/vulkan/vulkan_xcb.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/master/include/vulkan/vulkan_xcb.h'),
Source('include/vulkan/vulkan_xlib.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/master/include/vulkan/vulkan_xlib.h'),
Source('include/vulkan/vulkan_xlib_xrandr.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/master/include/vulkan/vulkan_xlib_xrandr.h'),
Source('src/vulkan/registry/vk.xml', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/main/registry/vk.xml'),
Source('include/vulkan/vulkan.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/main/include/vulkan/vulkan.h'),
Source('include/vulkan/vulkan_core.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/main/include/vulkan/vulkan_core.h'),
Source('include/vulkan/vulkan_beta.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/main/include/vulkan/vulkan_beta.h'),
Source('include/vulkan/vk_icd.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/main/include/vulkan/vk_icd.h'),
Source('include/vulkan/vk_layer.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/main/include/vulkan/vk_layer.h'),
Source('include/vulkan/vk_platform.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/main/include/vulkan/vk_platform.h'),
Source('include/vulkan/vulkan_android.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/main/include/vulkan/vulkan_android.h'),
Source('include/vulkan/vulkan_directfb.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/main/include/vulkan/vulkan_directfb.h'),
Source('include/vulkan/vulkan_fuchsia.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/main/include/vulkan/vulkan_fuchsia.h'),
Source('include/vulkan/vulkan_ggp.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/main/include/vulkan/vulkan_ggp.h'),
Source('include/vulkan/vulkan_ios.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/main/include/vulkan/vulkan_ios.h'),
Source('include/vulkan/vulkan_macos.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/main/include/vulkan/vulkan_macos.h'),
Source('include/vulkan/vulkan_metal.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/main/include/vulkan/vulkan_metal.h'),
Source('include/vulkan/vulkan_screen.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/main/include/vulkan/vulkan_screen.h'),
Source('include/vulkan/vulkan_vi.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/main/include/vulkan/vulkan_vi.h'),
Source('include/vulkan/vulkan_wayland.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/main/include/vulkan/vulkan_wayland.h'),
Source('include/vulkan/vulkan_win32.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/main/include/vulkan/vulkan_win32.h'),
Source('include/vulkan/vulkan_xcb.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/main/include/vulkan/vulkan_xcb.h'),
Source('include/vulkan/vulkan_xlib.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/main/include/vulkan/vulkan_xlib.h'),
Source('include/vulkan/vulkan_xlib_xrandr.h', 'https://github.com/KhronosGroup/Vulkan-Headers/raw/main/include/vulkan/vulkan_xlib_xrandr.h'),
Source('include/vulkan/vk_android_native_buffer.h', 'https://android.googlesource.com/platform/frameworks/native/+/master/vulkan/include/vulkan/vk_android_native_buffer.h?format=TEXT'),
Source('include/vulkan/.editorconfig', None),
],

2
mesa 3D driver/bin/symbols-check.py
View File

@ -73,7 +73,7 @@ def get_symbols_dumpbin(dumpbin, lib):
continue
symbol_name = fields[3]
# De-mangle symbols
if symbol_name[0] == '_':
if symbol_name[0] == '_' and '@' in symbol_name:
symbol_name = symbol_name[1:].split('@')[0]
symbols.append(symbol_name)
return symbols

25
mesa 3D driver/bin/update-android-headers.sh
View File

@ -8,9 +8,11 @@ if [ ! -e .git ]; then
fi
if [ ! -d platform-hardware-libhardware ]; then
git clone --depth 1 https://android.googlesource.com/platform/frameworks/native platform-frameworks-native
git clone --depth 1 https://android.googlesource.com/platform/hardware/libhardware platform-hardware-libhardware
git clone --depth 1 https://android.googlesource.com/platform/system/core platform-system-core
git clone --depth 1 https://android.googlesource.com/platform/frameworks/native platform-frameworks-native
git clone --depth 1 https://android.googlesource.com/platform/system/logging platform-system-logging
git clone --depth 1 https://android.googlesource.com/platform/system/unwinding platform-system-unwinding
fi
dest=include/android_stub
@ -25,14 +27,14 @@ mkdir ${dest}
# These directories contains mostly only the files we need, so copy wholesale
cp -av platform-frameworks-native/libs/nativewindow/include/vndk \
platform-system-core/libsync/include/sync \
platform-system-core/libsync/include/ndk \
platform-system-core/libbacktrace/include/backtrace \
platform-system-core/libsystem/include/system \
platform-system-core/liblog/include/log \
platform-frameworks-native/libs/nativewindow/include/apex \
cp -av \
platform-frameworks-native/libs/nativewindow/include/vndk \
platform-frameworks-native/libs/nativebase/include/nativebase \
platform-system-core/libsync/include/ndk \
platform-system-core/libsync/include/sync \
platform-system-core/libsystem/include/system \
platform-system-logging/liblog/include/log \
platform-system-unwinding/libbacktrace/include/backtrace \
${dest}
@ -43,15 +45,16 @@ cp -av platform-hardware-libhardware/include/hardware/{hardware,gralloc,gralloc1
cp -av platform-frameworks-native/vulkan/include/hardware/hwvulkan.h ${dest}/hardware
mkdir ${dest}/cutils
cp -av platform-system-core/libcutils/include/cutils/{log,native_handle,properties}.h ${dest}/cutils
cp -av platform-system-core/libcutils/include/cutils/{compiler,log,native_handle,properties,trace}.h ${dest}/cutils
# include/android has files from a few different projects
mkdir ${dest}/android
cp -av platform-frameworks-native/libs/nativewindow/include/android/* \
cp -av \
platform-frameworks-native/libs/nativewindow/include/android/* \
platform-frameworks-native/libs/arect/include/android/* \
platform-system-core/liblog/include/android/* \
platform-system-core/libsync/include/android/* \
platform-system-logging/liblog/include/android/* \
${dest}/android

5
mesa 3D driver/docs/drivers/freedreno/isaspec.rst
View File

@ -22,7 +22,7 @@ cuts taken to get things up and running (which are mostly not inherent to
the xml schema, and should not be too difficult to remove from the py and
decode/disasm utility):
* Maximum "bitset" size is 64b
* Maximum "field" size is 64b
* Fixed instruction size
Often times, especially when new functionality is added in later gens
@ -184,6 +184,9 @@ decoding. The display template consists of references to fields (which may
be derived fields) specified as ``{FIELDNAME}`` and other characters
which are just echoed through to the resulting decoded bitset.
It is possible to define a line column alignment value per field to influence
the visual output. It needs to be pecified as ``{FIELDNAME:align=xx}``.
The ``<override>`` element will be described in the next section, but it
provides for both different decoded instruction syntax/mnemonics (when
simply providing a different display template string) as well as instruction

9
mesa 3D driver/docs/drivers/llvmpipe.rst
View File

@ -106,9 +106,10 @@ Windows
On Windows, building will create
``build/windows-x86-debug/gallium/targets/libgl-gdi/opengl32.dll`` which
is a drop-in alternative for system's ``opengl32.dll``. To use it put it
in the same directory as your application. It can also be used by
replacing the native ICD driver, but it's quite an advanced usage, so if
is a drop-in alternative for system's ``opengl32.dll``, which will use
the Mesa ICD, ``build/windows-x86-debug/gallium/targets/wgl/libgallium_wgl.dll``.
To use it put both dlls in the same directory as your application. It can also
be used by replacing the native ICD driver, but it's quite an advanced usage, so if
you need to ask, don't even try it.
There is however an easy way to replace the OpenGL software renderer
@ -116,7 +117,7 @@ that comes with Microsoft Windows 7 (or later) with llvmpipe (that is,
on systems without any OpenGL drivers):
- copy
``build/windows-x86-debug/gallium/targets/libgl-gdi/opengl32.dll`` to
``build/windows-x86-debug/gallium/targets/wgl/libgallium_wgl.dll`` to
``C:\Windows\SysWOW64\mesadrv.dll``
- load this registry settings:

16
mesa 3D driver/docs/drivers/panfrost.rst
View File

@ -1,9 +1,10 @@
Panfrost
========
The Panfrost driver stack includes a **non-conformant** OpenGL ES
implementation for Arm Mali GPUs based on the Midgard and Bifrost
microarchitectures. The following GPUs are currently supported:
The Panfrost driver stack includes an OpenGL ES implementation for Arm Mali
GPUs based on the Midgard and Bifrost microarchitectures. It is **conformant**
on Mali G52 but **non-conformant** on other GPUs. The following hardware is
currently supported:
========= ============ ============ =======
Product Architecture OpenGL ES OpenGL
@ -39,17 +40,16 @@ it's easy to add support, see the commit ``cff7de4bb597e9`` as an example.
LLVM is *not* required by Panfrost's compilers. LLVM support in Mesa can
safely be disabled for most OpenGL ES users with Panfrost.
Build with meson like ``meson . build/ -Ddri-drivers= -Dvulkan-drivers=
Build like ``meson . build/ -Ddri-drivers= -Dvulkan-drivers=
-Dgallium-drivers=panfrost -Dllvm=disabled`` for a build directory
``build``.
Building for Android via the legacy ``Android.mk`` system is not officially
supported but reportedly works. Your mileage may vary.
For general information on building Mesa, read :doc:`the install documentation
<../install>`.
Chat
----
Panfrost developers and users hang out on IRC at ``#panfrost`` on OFTC.
Panfrost developers and users hang out on IRC at ``#panfrost`` on OFTC. Note
that registering and authenticating with `NickServ` is required to prevent
spam. `Join the chat. <https://webchat.oftc.net/?channels=#panfrost>`_

17
mesa 3D driver/docs/drivers/zink.rst
View File

@ -227,6 +227,23 @@ are required to be supported
* `VK_KHR_draw_indirect_count`_
Performance
-----------
If you notice poor performance and high CPU usage while running an application,
changing the descriptor manager may improve performance:
.. envvar:: ZINK_DESCRIPTORS <mode> ("auto")
``auto``
Automatically detect best mode. This is the default.
``lazy``
Disable caching and attempt to use the least amount of CPU.
``nofallback``
Always use caching to try reducing GPU churn.
``notemplates``
The same as `auto`, but disables the use of `VK_KHR_descriptor_templates`.
Debugging
---------

102
mesa 3D driver/docs/envvars.rst
View File

@ -232,12 +232,13 @@ the :doc:`Xlib software driver page <xlibdriver>` for details.
:envvar:`MESA_GLX_ALPHA_BITS`
specifies default number of bits for alpha channel.
i945/i965 driver environment variables (non-Gallium)
Intel driver environment variables
----------------------------------------------------
:envvar:`INTEL_NO_HW`
if set to 1, prevents batches from being submitted to the hardware.
This is useful for debugging hangs, etc.
:envvar:`INTEL_BLACKHOLE_DEFAULT`
if set to 1, true or yes, then the OpenGL implementation will
default ``GL_BLACKHOLE_RENDER_INTEL`` to true, thus disabling any
rendering.
:envvar:`INTEL_DEBUG`
a comma-separated list of named flags, which do various things:
@ -334,8 +335,65 @@ i945/i965 driver environment variables (non-Gallium)
``vs``
dump shader assembly for vertex shaders
:envvar:`INTEL_SCALAR_VS` (or ``TCS``, ``TES``, ``GS``)
force scalar/vec4 mode for a shader stage (Gen8-9 only)
:envvar:`INTEL_MEASURE`
Collects GPU timestamps over common intervals, and generates a CSV report
to show how long rendering took. The overhead of collection is limited to
the flushing that is required at the interval boundaries for accurate
timestamps. By default, timing data is sent to ``stderr``. To direct output
to a file:
``INTEL_MEASURE=file=/tmp/measure.csv {workload}``
To begin capturing timestamps at a particular frame:
``INTEL_MEASURE=file=/tmp/measure.csv,start=15 {workload}``
To capture only 23 frames:
``INTEL_MEASURE=count=23 {workload}``
To capture frames 15-37, stopping before frame 38:
``INTEL_MEASURE=start=15,count=23 {workload}``
Designate an asynchronous control file with:
``INTEL_MEASURE=control=path/to/control.fifo {workload}``
As the workload runs, enable capture for 5 frames with:
``$ echo 5 > path/to/control.fifo``
Enable unbounded capture:
``$ echo -1 > path/to/control.fifo``
and disable with:
``$ echo 0 > path/to/control.fifo``
Select the boundaries of each snapshot with:
``INTEL_MEASURE=draw``
Collects timings for every render (DEFAULT)
``INTEL_MEASURE=rt``
Collects timings when the render target changes
``INTEL_MEASURE=batch``
Collects timings when batches are submitted
``INTEL_MEASURE=frame``
Collects timings at frame boundaries
With ``INTEL_MEASURE=interval=5``, the duration of 5 events will be
combined into a single record in the output. When possible, a single
start and end event will be submitted to the GPU to minimize
stalling. Combined events will not span batches, except in
the case of ``INTEL_MEASURE=frame``.
:envvar:`INTEL_NO_HW`
if set to 1, true or yes, prevents batches from being submitted to the
hardware. This is useful for debugging hangs, etc.
:envvar:`INTEL_PRECISE_TRIG`
if set to 1, true or yes, then the driver prefers accuracy over
performance in trig functions.
@ -353,10 +411,6 @@ i945/i965 driver environment variables (non-Gallium)
The success of assembly override would be signified by "Successfully
overrode shader with sha1 <sha1>" in stderr replacing the original
assembly.
:envvar:`INTEL_BLACKHOLE_DEFAULT`
if set to 1, true or yes, then the OpenGL implementation will
default ``GL_BLACKHOLE_RENDER_INTEL`` to true, thus disabling any
rendering.
Radeon driver environment variables (radeon, r200, and r300g)
@ -365,6 +419,13 @@ Radeon driver environment variables (radeon, r200, and r300g)
:envvar:`RADEON_NO_TCL`
if set, disable hardware-accelerated Transform/Clip/Lighting.
DRI environment variables
-------------------------
:envvar:`DRI_NO_MSAA`
disable MSAA for GLX/EGL MSAA visuals
EGL environment variables
-------------------------
@ -557,8 +618,6 @@ RADV driver environment variables
force all allocated buffers to be referenced in submissions
``checkir``
validate the LLVM IR before LLVM compiles the shader
``errors``
display more info about errors
``forcecompress``
Enables DCC,FMASK,CMASK,HTILE in situations where the driver supports it
but normally does not deem it beneficial.
@ -574,6 +633,8 @@ RADV driver environment variables
class of application bugs appearing as flickering.
``metashaders``
dump internal meta shaders
``noatocdithering``
disable dithering for alpha to coverage
``nobinning``
disable primitive binning
``nocache``
@ -596,6 +657,8 @@ RADV driver environment variables
disable memory shaders cache
``nongg``
disable NGG for GFX10+
``nonggc``
disable NGG culling on GPUs where it's enabled by default (GFX10.3+ only).
``nooutoforder``
disable out-of-order rasterization
``notccompatcmask``
@ -607,6 +670,8 @@ RADV driver environment variables
disable VRS for flat shading (only on GFX10.3+)
``preoptir``
dump LLVM IR before any optimizations
``prologs``
dump vertex shader prologs
``shaders``
dump shaders
``shaderstats``
@ -639,6 +704,9 @@ RADV driver environment variables
enable wave32 for compute shaders (GFX10+)
``dccmsaa``
enable DCC for MSAA images
``force_emulate_rt``
forces ray-tracing to be emulated in software,
even if there is hardware support.
``gewave32``
enable wave32 for vertex/tess/geometry shaders (GFX10+)
``localbos``
@ -648,7 +716,7 @@ RADV driver environment variables
``pswave32``
enable wave32 for pixel shaders (GFX10+)
``nggc``
enable NGG culling on GFX10+ GPUs.
enable NGG culling on GPUs where it's not enabled by default (GFX10.1 only).
``rt``
enable rt extensions whose implementation is still experimental.
``sam``
@ -690,8 +758,6 @@ radeonsi driver environment variables
Disable DCC.
``nodccclear``
Disable DCC fast clear.
``nodccfb``
Disable separate DCC on the main framebuffer
``nodccmsaa``
Disable DCC for MSAA
``nodpbb``
@ -768,12 +834,6 @@ radeonsi driver environment variables
Always use NGG culling even when it can hurt.
``nonggc``
Disable NGG culling.
``alwayspd``
Always enable the primitive discard compute shader.
``pd``
Enable the primitive discard compute shader for large draw calls.
``nopd``
Disable the primitive discard compute shader.
``switch_on_eop``
Program WD/IA to switch on end-of-packet.
``nooutoforder``

93
mesa 3D driver/docs/features.txt
View File

@ -41,7 +41,7 @@ GL 3.0, GLSL 1.30 --- all DONE: freedreno, i965, nv50, nvc0, r600, radeonsi, llv
glBindFragDataLocation, glGetFragDataLocation DONE
GL_NV_conditional_render (Conditional rendering) DONE ()
GL_ARB_map_buffer_range (Map buffer subranges) DONE (v3d, vc4, lima)
GL_ARB_color_buffer_float (Clamping controls) DONE (v3d)
GL_ARB_color_buffer_float (Clamping controls) DONE (v3d, lima)
GL_ARB_texture_float (Float textures, renderbuffers) DONE (v3d)
GL_EXT_packed_float DONE (v3d)
GL_EXT_texture_shared_exponent DONE (v3d)
@ -74,7 +74,7 @@ GL 3.1, GLSL 1.40 --- all DONE: freedreno, i965, nv50, nvc0, r600, radeonsi, llv
Forward compatible context support/deprecations DONE
GL_ARB_draw_instanced (Instanced drawing) DONE (v3d)
GL_ARB_copy_buffer (Buffer copying) DONE (v3d, vc4, lima)
GL_NV_primitive_restart (Primitive restart) DONE ()
GL_NV_primitive_restart (Primitive restart) DONE (v3d)
16 vertex texture image units DONE ()
GL_ARB_texture_buffer_object (Texture buffer objs) DONE ()
GL_ARB_texture_rectangle (Rectangular textures) DONE (v3d, vc4, lima)
@ -206,14 +206,14 @@ GL 4.4, GLSL 4.40 -- all DONE: i965/gen8+, nvc0, r600, radeonsi, llvmpipe, zink
- input/output block locations DONE
GL_ARB_multi_bind DONE (all drivers)
GL_ARB_query_buffer_object DONE (i965/hsw+, virgl)
GL_ARB_texture_mirror_clamp_to_edge DONE (i965, nv50, softpipe, swr, virgl, panfrost)
GL_ARB_texture_mirror_clamp_to_edge DONE (i965, nv50, softpipe, swr, virgl, v3d, panfrost)
GL_ARB_texture_stencil8 DONE (freedreno, i965/hsw+, nv50, softpipe, swr, virgl, v3d, panfrost, d3d12)
GL_ARB_vertex_type_10f_11f_11f_rev DONE (freedreno, i965, nv50, softpipe, swr, virgl, panfrost, d3d12)
GL 4.5, GLSL 4.50 -- all DONE: nvc0, r600, radeonsi, llvmpipe, zink
GL_ARB_ES3_1_compatibility DONE (i965/hsw+, softpipe, virgl)
GL_ARB_clip_control DONE (freedreno, i965, nv50, softpipe, swr, virgl)
GL_ARB_clip_control DONE (freedreno, i965, nv50, softpipe, swr, virgl, lima)
GL_ARB_conditional_render_inverted DONE (freedreno, i965, nv50, softpipe, swr, virgl, panfrost)
GL_ARB_cull_distance DONE (freedreno/a6xx, i965, nv50, softpipe, swr, virgl)
GL_ARB_derivative_control DONE (i965, nv50, softpipe, virgl)
@ -268,40 +268,40 @@ GLES3.1, GLSL ES 3.1 -- all DONE: i965/hsw+, nvc0, r600, radeonsi, virgl, v3d, s
glGetBooleani_v - restrict to GLES enums
gl_HelperInvocation support DONE (i965, r600, panfrost)
GLES3.2, GLSL ES 3.2 -- all DONE: i965/gen9+, radeonsi, virgl, llvmpipe
GLES3.2, GLSL ES 3.2 -- all DONE: i965/gen9+, radeonsi, virgl, llvmpipe, zink
GL_EXT_color_buffer_float DONE (all drivers)
GL_KHR_blend_equation_advanced DONE (freedreno/a6xx, i965, nvc0, panfrost)
GL_KHR_debug DONE (all drivers)
GL_KHR_robustness DONE (freedreno, i965, nvc0, r600, zink)
GL_KHR_texture_compression_astc_ldr DONE (freedreno, i965/gen9+, r600, v3d, vc4, panfrost, softpipe, swr, zink, lima)
GL_KHR_robustness DONE (freedreno, i965, nvc0, r600)
GL_KHR_texture_compression_astc_ldr DONE (freedreno, i965/gen9+, r600, v3d, vc4, panfrost, softpipe, swr, lima)
GL_OES_copy_image DONE (all drivers)
GL_OES_draw_buffers_indexed DONE (all drivers that support GL_ARB_draw_buffers_blend)
GL_OES_draw_elements_base_vertex DONE (all drivers)
GL_OES_geometry_shader DONE (freedreno/a6xx, i965/hsw+, nvc0, r600, softpipe, v3d, zink)
GL_OES_geometry_shader DONE (freedreno/a6xx, i965/hsw+, nvc0, r600, softpipe, v3d)
GL_OES_gpu_shader5 DONE (freedreno/a6xx, all drivers that support GL_ARB_gpu_shader5)
GL_OES_primitive_bounding_box DONE (freedreno/a5xx+, i965/gen7+, nvc0, r600, softpipe, v3d, zink)
GL_OES_sample_shading DONE (freedreno/a6xx, i965, nvc0, r600, zink, panfrost, zink)
GL_OES_sample_variables DONE (freedreno/a6xx, i965, nvc0, r600, zink, panfrost/bifrost, zink)
GL_OES_primitive_bounding_box DONE (freedreno/a5xx+, i965/gen7+, nvc0, r600, softpipe, v3d)
GL_OES_sample_shading DONE (freedreno/a6xx, i965, nvc0, r600, panfrost)
GL_OES_sample_variables DONE (freedreno/a6xx, i965, nvc0, r600, panfrost/bifrost)
GL_OES_shader_image_atomic DONE (all drivers that support GL_ARB_shader_image_load_store)
GL_OES_shader_io_blocks DONE (All drivers that support GLES 3.1)
GL_OES_shader_multisample_interpolation DONE (freedreno/a6xx, i965, nvc0, r600, zink)
GL_OES_shader_multisample_interpolation DONE (freedreno/a6xx, i965, nvc0, r600)
GL_OES_tessellation_shader DONE (freedreno/a6xx, all drivers that support GL_ARB_tessellation_shader)
GL_OES_texture_border_clamp DONE (all drivers)
GL_OES_texture_buffer DONE (freedreno, i965, nvc0, r600, softpipe, panfrost, zink)
GL_OES_texture_cube_map_array DONE (freedreno/a4xx+, i965/hsw+, nvc0, r600, softpipe, zink)
GL_OES_texture_buffer DONE (freedreno, i965, nvc0, r600, softpipe, panfrost)
GL_OES_texture_cube_map_array DONE (freedreno/a4xx+, i965/hsw+, nvc0, r600, softpipe)
GL_OES_texture_stencil8 DONE (all drivers that support GL_ARB_texture_stencil8)
GL_OES_texture_storage_multisample_2d_array DONE (all drivers that support GL_ARB_texture_multisample)
Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES version:
GL_ARB_bindless_texture DONE (nvc0, radeonsi)
GL_ARB_bindless_texture DONE (nvc0, radeonsi, zink)
GL_ARB_cl_event not started
GL_ARB_compute_variable_group_size DONE (i965/gen7+, nvc0, radeonsi, zink)
GL_ARB_ES3_2_compatibility DONE (i965/gen8+, radeonsi, virgl, zink)
GL_ARB_fragment_shader_interlock DONE (i965, zink)
GL_ARB_gpu_shader_int64 DONE (i965/gen8+, nvc0, radeonsi, softpipe, llvmpipe, zink)
GL_ARB_parallel_shader_compile DONE (all drivers)
GL_ARB_parallel_shader_compile DONE (freedreno, iris, radeonsi)
GL_ARB_post_depth_coverage DONE (i965, nvc0, radeonsi, llvmpipe, zink)
GL_ARB_robustness_isolation not started
GL_ARB_sample_locations DONE (nvc0, zink)
@ -316,12 +316,12 @@ Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES ve
GL_ARB_sparse_texture2 not started
GL_ARB_sparse_texture_clamp not started
GL_ARB_texture_filter_minmax DONE (nvc0/gm200+, zink)
GL_EXT_color_buffer_half_float DONE (gallium drivers supporting required formats)
GL_EXT_color_buffer_half_float DONE (freedreno, i965, iris, llvmpipe, nv50, nvc0, radeonsi, zink)
GL_EXT_depth_bounds_test DONE (i965/gen12+, nv50, nvc0, radeonsi, softpipe, swr, zink)
GL_EXT_memory_object DONE (radeonsi, i965/gen7+)
GL_EXT_memory_object_fd DONE (radeonsi, i965/gen7+)
GL_EXT_memory_object DONE (radeonsi, i965/gen7+, llvmpipe)
GL_EXT_memory_object_fd DONE (radeonsi, i965/gen7+, llvmpipe)
GL_EXT_memory_object_win32 not started
GL_EXT_multisampled_render_to_texture DONE (freedreno/a6xx, panfrost)
GL_EXT_multisampled_render_to_texture DONE (freedreno/a6xx, panfrost, zink)
GL_EXT_render_snorm DONE (i965, r600, radeonsi, softpipe, zink)
GL_EXT_semaphore DONE (radeonsi, i965/gen7+)
GL_EXT_semaphore_fd DONE (radeonsi, i965/gen7+)
@ -448,23 +448,23 @@ Vulkan 1.2 -- all DONE: anv, vn
VK_KHR_8bit_storage DONE (anv/gen8+, lvp, radv, vn)
VK_KHR_buffer_device_address DONE (anv/gen8+, lvp, radv, vn)
VK_KHR_create_renderpass2 DONE (anv, lvp, radv, tu, vn)
VK_KHR_depth_stencil_resolve DONE (anv, radv, tu, vn)
VK_KHR_depth_stencil_resolve DONE (anv, lvp, radv, tu, vn)
VK_KHR_draw_indirect_count DONE (anv, lvp, radv, tu, vn)
VK_KHR_driver_properties DONE (anv, lvp, radv, vn)
VK_KHR_image_format_list DONE (anv, lvp, radv, tu, v3dv, vn)
VK_KHR_imageless_framebuffer DONE (anv, lvp, radv, vn)
VK_KHR_imageless_framebuffer DONE (anv, lvp, radv, tu, vn)
VK_KHR_sampler_mirror_clamp_to_edge DONE (anv, lvp, radv, tu, v3dv, vn)
VK_KHR_separate_depth_stencil_layouts DONE (anv, lvp, radv, vn)
VK_KHR_shader_atomic_int64 DONE (anv/gen9+, lvp, radv, vn)
VK_KHR_shader_float16_int8 DONE (anv/gen8+, radv, tu, vn)
VK_KHR_shader_float_controls DONE (anv/gen8+, radv, tu, vn)
VK_KHR_shader_subgroup_extended_types DONE (anv/gen8+, radv, vn)
VK_KHR_spirv_1_4 DONE (anv, radv, tu, vn)
VK_KHR_shader_float16_int8 DONE (anv/gen8+, lvp, radv, tu, vn)
VK_KHR_shader_float_controls DONE (anv/gen8+, lvp, radv, tu, vn)
VK_KHR_shader_subgroup_extended_types DONE (anv/gen8+, lvp, radv, tu, vn)
VK_KHR_spirv_1_4 DONE (anv, lvp, radv, tu, vn)
VK_KHR_timeline_semaphore DONE (anv, lvp, radv, tu, vn)
VK_KHR_uniform_buffer_standard_layout DONE (anv, lvp, radv, v3dv, vn)
VK_KHR_uniform_buffer_standard_layout DONE (anv, lvp, radv, tu, v3dv, vn)
VK_KHR_vulkan_memory_model DONE (anv, radv, tu, vn)
VK_EXT_descriptor_indexing DONE (anv/gen9+, radv, tu, vn)
VK_EXT_host_query_reset DONE (anv, lvp, radv, tu, vn)
VK_EXT_host_query_reset DONE (anv, lvp, radv, tu, v3dv, vn)
VK_EXT_sampler_filter_minmax DONE (anv/gen9+, lvp, radv, tu, vn)
VK_EXT_scalar_block_layout DONE (anv, lvp, radv/gfx7+, tu, vn)
VK_EXT_separate_stencil_usage DONE (anv, lvp, tu, vn)
@ -477,28 +477,29 @@ Khronos extensions that are not part of any Vulkan version:
VK_KHR_deferred_host_operations DONE (anv, radv)
VK_KHR_display DONE (anv, lvp, radv, tu, v3dv)
VK_KHR_display_swapchain not started
VK_KHR_external_fence_fd DONE (anv, radv, tu, v3dv)
VK_KHR_external_fence_fd DONE (anv, radv, tu, v3dv, vn)
VK_KHR_external_fence_win32 not started
VK_KHR_external_memory_fd DONE (anv, radv, tu, v3dv)
VK_KHR_external_memory_fd DONE (anv, lvp, radv, tu, v3dv, vn)
VK_KHR_external_memory_win32 not started
VK_KHR_external_semaphore_fd DONE (anv, radv, tu, v3dv)
VK_KHR_external_semaphore_fd DONE (anv, radv, tu, v3dv, vn)
VK_KHR_external_semaphore_win32 not started
VK_KHR_fragment_shading_rate not started
VK_KHR_get_display_properties2 DONE (anv, lvp, radv, tu, v3dv)
VK_KHR_get_surface_capabilities2 DONE (anv, lvp, radv, tu, v3dv, vn)
VK_KHR_incremental_present DONE (anv, lvp, radv, tu, v3dv)
VK_KHR_incremental_present DONE (anv, lvp, radv, tu, v3dv, vn)
VK_KHR_performance_query DONE (anv/gen8+, tu)
VK_KHR_pipeline_executable_properties DONE (anv, radv, tu)
VK_KHR_push_descriptor DONE (anv, lvp, radv, tu)
VK_KHR_shader_clock DONE (anv, radv)
VK_KHR_shader_integer_dot_product DONE (radv)
VK_KHR_shader_non_semantic_info DONE (anv, radv)
VK_KHR_shader_subgroup_uniform_control_flow DONE (anv, radv)
VK_KHR_shader_terminate_invocation DONE (anv, radv, tu)
VK_KHR_shared_presentable_image not started
VK_KHR_surface DONE (anv, lvp, radv, tu, v3dv, vn)
VK_KHR_surface_protected_capabilities DONE (anv, lvp, radv, vn)
VK_KHR_swapchain DONE (anv, lvp, radv, tu, v3dv)
VK_KHR_swapchain_mutable_format DONE (anv, radv)
VK_KHR_surface_protected_capabilities DONE (anv, lvp, radv, v3dv, vn)
VK_KHR_swapchain DONE (anv, lvp, radv, tu, v3dv, vn)
VK_KHR_swapchain_mutable_format DONE (anv, radv, v3dv, vn)
VK_KHR_wayland_surface DONE (anv, lvp, radv, tu, v3dv, vn)
VK_KHR_workgroup_memory_explicit_layout DONE (anv, radv)
VK_KHR_win32_keyed_mutex not started
@ -506,40 +507,40 @@ Khronos extensions that are not part of any Vulkan version:
VK_KHR_xcb_surface DONE (anv, lvp, radv, tu, v3dv, vn)
VK_KHR_xlib_surface DONE (anv, lvp, radv, tu, v3dv, vn)
VK_KHR_zero_initialize_workgroup_memory DONE (anv, radv)
VK_EXT_4444_formats DONE (anv, radv, tu)
VK_EXT_4444_formats DONE (anv, lvp, radv, tu)
VK_EXT_calibrated_timestamps DONE (anv, lvp, radv)
VK_EXT_color_write_enable DONE (anv, lvp, v3dv)
VK_EXT_conditional_rendering DONE (anv, lvp, radv, tu)
VK_EXT_conservative_rasterization DONE (anv/gen9+, radv)
VK_EXT_custom_border_color DONE (anv, lvp, radv, tu, v3dv)
VK_EXT_debug_marker DONE (radv)
VK_EXT_depth_clip_enable DONE (anv, radv, tu)
VK_EXT_depth_clip_enable DONE (anv, lvp, radv, tu)
VK_EXT_depth_range_unrestricted DONE (radv)
VK_EXT_discard_rectangles DONE (radv)
VK_EXT_display_control DONE (anv, radv, tu)
VK_EXT_extended_dynamic_state DONE (anv, lvp, radv, tu)
VK_EXT_extended_dynamic_state2 DONE (anv, lvp, radv)
VK_EXT_external_memory_dma_buf DONE (anv, radv, tu, v3dv)
VK_EXT_external_memory_dma_buf DONE (anv, radv, tu, v3dv, vn)
VK_EXT_external_memory_host DONE (anv, lvp, radv)
VK_EXT_filter_cubic DONE (tu/a650)
VK_EXT_fragment_shader_interlock DONE (anv/gen9+)
VK_EXT_global_priority DONE (anv, radv)
VK_EXT_image_drm_format_modifier DONE (anv, radv/gfx9+, tu)
VK_EXT_image_drm_format_modifier DONE (anv, radv/gfx9+, tu, vn)
VK_EXT_image_robustness DONE (anv, radv)
VK_EXT_index_type_uint8 DONE (anv, lvp, radv/gfx8+, v3dv, tu)
VK_EXT_inline_uniform_block DONE (anv, radv)
VK_EXT_line_rasterization DONE (anv, lvp, radv)
VK_EXT_line_rasterization DONE (anv, lvp, radv, tu)
VK_EXT_memory_budget DONE (anv, radv, tu)
VK_EXT_memory_priority DONE (radv)
VK_EXT_multi_draw DONE (anv, lvp, radv)
VK_EXT_pci_bus_info DONE (anv, radv)
VK_EXT_physical_device_drm DONE (anv, radv, v3dv)
VK_EXT_pipeline_creation_cache_control DONE (anv, radv, v3dv)
VK_EXT_pipeline_creation_feedback DONE (anv, radv)
VK_EXT_pipeline_creation_feedback DONE (anv, radv, v3dv)
VK_EXT_post_depth_coverage DONE (anv/gfx10+, lvp, radv)
VK_EXT_private_data DONE (anv, lvp, radv, tu, v3dv)
VK_EXT_provoking_vertex DONE (anv, lvp, radv, tu, v3dv)
VK_EXT_queue_family_foreign DONE (anv, radv)
VK_EXT_queue_family_foreign DONE (anv, radv, vn)
VK_EXT_robustness2 DONE (anv, radv, tu)
VK_EXT_sample_locations DONE (anv, radv/gfx9-, tu/a650)
VK_EXT_shader_atomic_float DONE (anv, radv)
@ -552,11 +553,11 @@ Khronos extensions that are not part of any Vulkan version:
VK_EXT_subgroup_size_control DONE (anv, radv)
VK_EXT_texel_buffer_alignment DONE (anv, radv)
VK_EXT_transform_feedback DONE (anv, lvp, radv, tu, vn)
VK_EXT_vertex_attribute_divisor DONE (anv, radv, lvp, tu)
VK_EXT_vertex_input_dynamic_state DONE (lvp)
VK_EXT_vertex_attribute_divisor DONE (anv, radv, lvp, tu, v3dv)
VK_EXT_vertex_input_dynamic_state DONE (lvp, radv)
VK_EXT_ycbcr_image_arrays DONE (anv, radv)
VK_ANDROID_external_memory_android_hardware_buffer DONE (anv, radv)
VK_ANDROID_native_buffer DONE (anv, radv)
VK_ANDROID_external_memory_android_hardware_buffer DONE (anv, radv, vn)
VK_ANDROID_native_buffer DONE (anv, radv, vn)
VK_GOOGLE_decorate_string DONE (anv, lvp, radv)
VK_GOOGLE_hlsl_functionality1 DONE (anv, lvp, radv)
VK_GOOGLE_user_type DONE (anv, radv)

2
mesa 3D driver/docs/gallium/context.rst
View File

@ -118,6 +118,8 @@ objects. They all follow simple, one-method binding calls, e.g.
levels. This corresponds to GL's ``PATCH_DEFAULT_OUTER_LEVEL``.
* ``default_inner_level`` is the default value for the inner tessellation
levels. This corresponds to GL's ``PATCH_DEFAULT_INNER_LEVEL``.
* ``set_patch_vertices`` sets the number of vertices per input patch
for tessellation.
* ``set_debug_callback`` sets the callback to be used for reporting
various debug messages, eventually reported via KHR_debug and

13
mesa 3D driver/docs/gallium/cso/rasterizer.rst
View File

@ -326,10 +326,15 @@ clip_halfz
When true clip space in the z axis goes from [0..1] (D3D). When false
[-1, 1] (GL)
depth_clip
When false, the near and far depth clipping planes of the view volume are
disabled and the depth value will be clamped at the per-pixel level, after
polygon offset has been applied and before depth testing.
depth_clip_near
When false, the near depth clipping plane of the view volume is disabled.
depth_clip_far
When false, the far depth clipping plane of the view volume is disabled.
depth_clamp
Whether the depth value will be clamped to the interval defined by the
near and far depth range at the per-pixel level, after polygon offset has
been applied and before depth testing. Note that a clamp to [0,1] according
to GL rules should always happen even if this is disabled.
clip_plane_enable
For each k in [0, PIPE_MAX_CLIP_PLANES), if bit k of this field is set,

5
mesa 3D driver/docs/gallium/screen.rst
View File

@ -80,6 +80,9 @@ The integer capabilities:
disabling depth clipping (through pipe_rasterizer_state) separately for
the near and far plane. If not, depth_clip_near and depth_clip_far will be
equal.
``PIPE_CAP_DEPTH_CLAMP_ENABLE``: Whether the driver is capable of
enabling depth clamping (through pipe_rasterizer_state) separately from depth
clipping. If not, depth_clamp will be the inverse of depth_clip_far.
* ``PIPE_CAP_SHADER_STENCIL_EXPORT``: Whether a stencil reference value can be
written from a fragment shader.
* ``PIPE_CAP_TGSI_INSTANCEID``: Whether TGSI_SEMANTIC_INSTANCEID is supported
@ -618,6 +621,8 @@ The integer capabilities:
* ``PIPE_CAP_EMULATE_NONFIXED_PRIMITIVE_RESTART``: Driver requests all draws using a non-fixed restart index to be rewritten to use a fixed restart index.
* ``PIPE_CAP_SUPPORTED_PRIM_MODES``: A bitmask of the ``pipe_prim_type`` enum values that the driver can natively support.
* ``PIPE_CAP_SUPPORTED_PRIM_MODES_WITH_RESTART``: A bitmask of the ``pipe_prim_type`` enum values that the driver can natively support for primitive restart. Only useful if ``PIPE_CAP_PRIMITIVE_RESTART`` is also exported.
* ``PIPE_CAP_PREFER_BACK_BUFFER_REUSE``: Only applies to DRI_PRIME. If 1, the driver prefers that DRI3 tries to use the same back buffer each frame. If 0, this means DRI3 will at least use 2 back buffers and ping-pong between them to allow the tiled->linear copy to run in parallel.
* ``PIPE_CAP_DRAW_VERTEX_STATE``: Driver supports `pipe_screen::create_vertex_state/vertex_state_destroy` and `pipe_context::draw_vertex_state`. Only used by display lists and designed to serve vbo_save.
.. _pipe_capf:

5
mesa 3D driver/docs/gallium/tgsi.rst
View File

@ -3561,11 +3561,6 @@ interpolation should be done at, one of ``TGSI_INTERPOLATE_LOC_*``. Note that
when per-sample shading is enabled, the implementation may choose to
interpolate at the sample irrespective of the Location field.
The CylindricalWrap bitfield specifies which register components
should be subject to cylindrical wrapping when interpolating by the
rasteriser. If TGSI_CYLINDRICAL_WRAP_X is set to 1, the X component
should be interpolated according to cylindrical wrapping rules.
Declaration Sampler View
^^^^^^^^^^^^^^^^^^^^^^^^

31
mesa 3D driver/docs/isl/tiling.rst
View File

@ -246,6 +246,36 @@ ISL, we represent a W-tile as a tiling with a logical dimension of 64el x 64el
but a physical size of 128B x 32rows. This cleanly takes care of the pitch
issue above and seems to nicely model the hardware.
Tile4
-----
The tile4 format, introduced on Xe-HP, is somewhat similar to Y but with more
internal shuffling. Each tile4 tile is an 8x8 grid of cache lines arranged
as follows:
===== ===== ===== ===== ===== ===== ===== =====
===== ===== ===== ===== ===== ===== ===== =====
0x000 0x040 0x080 0x0a0 0x200 0x240 0x280 0x2a0
0x100 0x140 0x180 0x1a0 0x300 0x340 0x380 0x3a0
0x400 0x440 0x480 0x4a0 0x600 0x640 0x680 0x6a0
0x500 0x540 0x580 0x5a0 0x700 0x740 0x780 0x7a0
0x800 0x840 0x880 0x8a0 0xa00 0xa40 0xa80 0xaa0
0x900 0x940 0x980 0x9a0 0xb00 0xb40 0xb80 0xba0
0xc00 0xc40 0xc80 0xca0 0xe00 0xe40 0xe80 0xea0
0xd00 0xd40 0xd80 0xda0 0xf00 0xf40 0xf80 0xfa0
===== ===== ===== ===== ===== ===== ===== =====
Each 64B cache line within the tile is laid out the same way as for a Y-tile,
as 4 rows of 16B each:
==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ====
==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ====
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f
0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f
0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f
==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ==== ====
Tiling as a bit pattern
-----------------------
@ -281,6 +311,7 @@ the tile are given by the table below:
:cpp:enumerator:`isl_tiling::ISL_TILING_X` :math:`v_2` :math:`v_1` :math:`v_0` :math:`u_8` :math:`u_7` :math:`u_6` :math:`u_5` :math:`u_4` :math:`u_3` :math:`u_2` :math:`u_1` :math:`u_0`
:cpp:enumerator:`isl_tiling::ISL_TILING_Y0` :math:`u_6` :math:`u_5` :math:`u_4` :math:`v_4` :math:`v_3` :math:`v_2` :math:`v_1` :math:`v_0` :math:`u_3` :math:`u_2` :math:`u_1` :math:`u_0`
:cpp:enumerator:`isl_tiling::ISL_TILING_W` :math:`u_5` :math:`u_4` :math:`u_3` :math:`v_5` :math:`v_4` :math:`v_3` :math:`v_2` :math:`u_2` :math:`v_1` :math:`u_1` :math:`v_0` :math:`u_0`
:cpp:enumerator:`isl_tiling::ISL_TILING_4` :math:`v_4` :math:`v_3` :math:`u_6` :math:`v_2` :math:`u_5` :math:`u_4` :math:`v_1` :math:`v_0` :math:`u_3` :math:`u_2` :math:`u_1` :math:`u_0`
=========================================== =========== =========== =========== =========== =========== =========== =========== =========== =========== =========== =========== ===========
Constructing the mapping this way makes a lot of sense when you think about

16
mesa 3D driver/docs/release-calendar.csv
View File

@ -1,10 +1,6 @@
21.1,2021-08-25,21.1.8,Eric Engestrom,
21.2,2021-08-18,21.2.1,Dylan Baker
,2021-09-01,21.2.2,Dylan Baker
,2021-09-15,21.2.3,Dylan Baker,
,2021-09-29,21.2.4,Dylan Baker,
,2021-10-13,21.2.5,Dylan Baker,
,2021-10-27,21.2.6,Dylan Baker,
,2021-11-10,21.2.7,Dylan Baker,
,2021-11-24,21.2.8,Dylan Baker,
,2021-12-08,21.2.9,Dylan Baker,This is the last planned release of the 21.2.x series.
21.2,2021-10-27,21.2.5,Dylan Baker,
,2021-11-10,21.2.6,Dylan Baker,
,2021-11-24,21.2.7,Dylan Baker,
,2021-12-08,21.2.8,Dylan Baker,Last planned 21.2.x release.
21.3,2021-10-27,21.3.0-rc3,Eric Engestrom,
,2021-11-03,21.3.0-rc4,Eric Engestrom,

1 21.1,2021-08-25,21.1.8,Eric Engestrom, 21.2 2021-10-27 21.2.5 Dylan Baker
2 21.2,2021-08-18,21.2.1,Dylan Baker 2021-11-10 21.2.6 Dylan Baker
3 ,2021-09-01,21.2.2,Dylan Baker 2021-11-24 21.2.7 Dylan Baker
4 ,2021-09-15,21.2.3,Dylan Baker, 2021-12-08 21.2.8 Dylan Baker Last planned 21.2.x release.
5 ,2021-09-29,21.2.4,Dylan Baker, 21.3 2021-10-27 21.3.0-rc3 Eric Engestrom
6 ,2021-10-13,21.2.5,Dylan Baker, 2021-11-03 21.3.0-rc4 Eric Engestrom
,2021-10-27,21.2.6,Dylan Baker,
,2021-11-10,21.2.7,Dylan Baker,
,2021-11-24,21.2.8,Dylan Baker,
,2021-12-08,21.2.9,Dylan Baker,This is the last planned release of the 21.2.x series.

8
mesa 3D driver/docs/relnotes.rst
View File

@ -3,6 +3,10 @@ Release Notes
The release notes summarize what's new or changed in each Mesa release.
- :doc:`21.2.4 release notes <relnotes/21.2.4>`
- :doc:`21.2.3 release notes <relnotes/21.2.3>`
- :doc:`21.2.2 release notes <relnotes/21.2.2>`
- :doc:`21.1.8 release notes <relnotes/21.1.8>`
- :doc:`21.1.7 release notes <relnotes/21.1.7>`
- :doc:`21.2.0 release notes <relnotes/21.2.0>`
- :doc:`21.1.6 release notes <relnotes/21.1.6>`
@ -342,6 +346,10 @@ release notes, or in the `old docs`_.
:maxdepth: 1
:hidden:
relnotes/21.2.4
relnotes/21.2.3
relnotes/21.2.2
relnotes/21.1.8
relnotes/21.1.7
relnotes/21.2.0
relnotes/21.1.6

105
mesa 3D driver/docs/relnotes/21.1.8.rst Normal file
View File

@ -0,0 +1,105 @@
Mesa 21.1.8 Release Notes / 2021-09-08
======================================
Mesa 21.1.8 is a bug fix release which fixes bugs found since the 21.1.7 release.
Mesa 21.1.8 implements the OpenGL 4.6 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.6. OpenGL
4.6 is **only** available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
Mesa 21.1.8 implements the Vulkan 1.2 API, but the version reported by
the apiVersion property of the VkPhysicalDeviceProperties struct
depends on the particular driver being used.
SHA256 checksum
---------------
::
5cd32f5d089dca75300578a3d771a656eaed652090573a2655fe4e7022d56bfc mesa-21.1.8.tar.xz
New features
------------
- None
Bug fixes
---------
- llvmpipe doesn't compile a valid shader with an useless switch
- GetFragDataLocation(prog, "gl_FragColor") generates INVALID_OPERATION, but specs don't say it should
- Possible miscompilation of a comparison with unsigned zero
- dEQP-VK.wsi.android.swapchain.create#image_swapchain_create_info crash on Android R
Changes
-------
Alyssa Rosenzweig (1):
- drm-shim: Support kernels with >4k pages
Boris Brezillon (1):
- panfrost: Fix pan_blitter_emit_bifrost_blend()
Eric Engestrom (3):
- .pick_status.json: Update to 8bb9e9e76fa1f062c8da9536e9ee209b2dc268f7
- Revert "python: Explicitly add the 'L' suffix on Python 3"
- isl: drop left-over comment
Erik Faye-Lund (2):
- gallium/nir/tgsi: fixup indentation
- gallium/nir/tgsi: initialize file_max for inputs
Ilia Mirkin (1):
- mesa: don't return errors for gl_* GetFragData* queries
Jason Ekstrand (1):
- anv: Set CONTEXT_PARAM_RECOVERABLE to false
Lionel Landwerlin (1):
- anv/android: handle image bindings from gralloc buffers
Mao, Marc (1):
- iris: declare padding for iris_vue_prog_key
Marcin Ślusarz (2):
- nir/builder: invalidate metadata per function
- glsl/opt_algebraic: disable invalid optimization
Mike Blumenkrantz (1):
- nir/lower_vectorize_tess_levels: set num_components for vectorized loads
Roman Stratiienko (1):
- lima: Implement lima_resource_get_param() callback
Simon Ser (4):
- etnaviv: add stride, offset and modifier to resource_get_param
- panfrost: implement resource_get_param
- vc4: implement resource_get_param
- v3d: implement resource_get_param
Timothy Arceri (1):
- glsl: fix variable scope for instructions inside case statements
Vinson Lee (2):
- meson: Remove duplicate xvmc in build summary.
- nir: Initialize evaluate_cube_face_index_amd dst.x.

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Mesa 21.2.2 Release Notes / 2021-09-21
======================================
Mesa 21.2.2 is a bug fix release which fixes bugs found since the 21.2.1 release.
Mesa 21.2.2 implements the OpenGL 4.6 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.6. OpenGL
4.6 is **only** available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
Mesa 21.2.2 implements the Vulkan 1.2 API, but the version reported by
the apiVersion property of the VkPhysicalDeviceProperties struct
depends on the particular driver being used.
SHA256 checksum
---------------
::
c4aaf1bf974217ed825e1c536de6ab72a4e266d44bcf69fc4ec499039f99e5c4 mesa-21.2.2.tar.xz
New features
------------
- None
Bug fixes
---------
- RADV: consistent crash in Splitgate
- [RADV] The game "Aliens: Fireteam Elite" start crashing after commit 2e56e2342094e8ec90afa5265b1c43503f662939
- llvmpipe doesn't compile a shader with an inner scope in a for loop
- llvmpipe doesn't compile the increment of a for a loop
- Mesa 21.2.1 implementation error: unexpected state[0] in make_state_flags()
- freedreno: regression in org.skia.skqp.SkQPRunner#gles_localmatriximagefilter
- [Radeonsi] VA-API Encoding no longer works on AMD PITCAIRN
- turnip: Geometry flickering in Genshin Impact after 83e9a7fbcf53b90d0de66985dbbf91986fc7b05d
- OSMesa problem resizing
- Memory leak: si_get_shader_binary_size is missing a call to ac_rtld_close
- dEQP-GLES3.stress.draw.unaligned_data.random.4 segfault
- gl_DrawID is incorrect for glMultiDrawElementsBaseVertex/glMultiDrawElementsIndirect
- i915: GPU hang when doing FB fetch and gl_FragDepth write in one shader
- ../mesa-9999/src/amd/compiler/aco_instruction_selection.cpp:10009:30: error: 'exchange' is not a member of 'std'
- radv: disable DCC for displayable images with storage on navi12/14
- RADV: Menu static/artifacts in Doom Eternal
- Crash happens when testing GL_PIXEL_PACK_BUFFER
- panfrost G31 - Cathedral crash- opengl 2.1 game (I guess)
- panfrost / armv7 - crash with mesa newer than 21.0.3
- freedreno C++14 build error
- llvmpipe doesn't compile a valid shader with an useless switch
- GetFragDataLocation(prog, "gl_FragColor") generates INVALID_OPERATION, but specs don't say it should
Changes
-------
Adrian Bunk (1):
- util/format: NEON is not available with the soft-float ABI
Alyssa Rosenzweig (24):
- panfrost: Handle non-dithered clear colours
- panfrost: Disable shader-assisted indirect draws
- pan/bi: Don't set td in blend shaders
- pan/bi: Correct the sr_count on +ST_TILE
- pan/bi: Extract load_sample_id to a helper
- pan/bi: Set the sample ID for blend shader LD_TILE
- pan/bi: Use CLPER_V6 on Mali G31
- panfrost: Remove unneeded quirks from T760
- panfrost: Use blendable check for tib read check
- pan/mdg: Insert moves before writeout when needed
- panfrost: Zero initialize blend_shaders
- panfrost: Fix NULL dereference in allowlist code
- panfrost: Protect the variants array with a lock
- panfrost: Don't use ralloc for resources
- panfrost: Move bo->label assignment into the lock
- panfrost: Switch resources from an array to a set
- panfrost: Cache number of users of a resource
- panfrost: Maintain a bitmap of active batches
- panfrost: Add foreach_batch iterator
- panfrost: Prefer batch->resources to rsrc->users
- panfrost: Remove rsrc->track.users
- panfrost: Remove writer = NULL assignments
- panfrost: Replace writers pointer with hash table
- panfrost: Raise maximum texture size
Bas Nieuwenhuizen (2):
- util/fossilize_db: Don't corrupt keys during entry read.
- nir: Avoid visiting instructions multiple times in nir_instr_free_and_dce.
Boris Brezillon (2):
- panfrost: Add explicit padding to pan_blend_shader_key
- panfrost: v7 does not support RGB32_UNORM textures
Connor Abbott (4):
- ir3/ra: Fix available bitset for live-through collect srcs
- ir3/ra: Handle huge merge sets
- ir3/lower_pcopy: Use right flags for src const/immed
- ir3/lower_pcopy: Set entry->done in the swap loop
Corentin Noël (1):
- glx: Prevent crashes when an extension isn't found
Daniel Schürmann (1):
- aco: fix p_insert lowering with 16bit sources
Danylo Piliaiev (1):
- turnip: re-emit vertex params after they are invalidated
Dave Airlie (5):
- vulkan/wsi/sw: wait for image fence before submitting to queue
- crocus: copy views before adjusting
- crocus: add missing line smooth bits.
- crocus: add missing fs dirty on reduced prim change.
- crocus/gen7: add missing IVB/GT2 geom shader workaround.
Dylan Baker (11):
- docs: add SHA256 sum for mesa 21.2.1
- .pick_status.json: Update to 35c3f5f08b7b11f3896412fb5778f127be329615
- .pick_status.json: Update to 8e5e70bb3de7f75ab1b039e2cec2975ba59e4af7
- .pick_status.json: Update to 572ed2249465acd4c5f8a229d504a48cbddf95a5
- .pick_status.json: Update to 71e748ad2443c373bb090fa1da2626da367b1d20
- .pick_status.json: Update to 9bc61108d73db4e614dda2a27750ff80165eedbb
- .pick_status.json: Update to a6a89aaa2f2943532d99d9bc7b80106a1740f237
- .pick_status.json: Update to f4b61e90617f19ca1b8a3cfe046bac5801081057
- .pick_status.json: Update to 076c8f041a63c74c31d9f541684860628a8b9979
- .pick_status.json: Update to b58d6eaf1174aab296c4230e3895c65cba4bd9e3
- .pick_status.json: Update to 7244aa19806cec5265e1e219cac1a99b0d3c62c6
Ed Martin (1):
- winsys/radeonsi: Set vce_encode = true when VCE found
Emma Anholt (2):
- llvmpipe: Free CS shader images on context destroy.
- llvmpipe: Fix leak of CS local memory with 0 threads.
Erik Faye-Lund (4):
- gallivm: fix texture-mapping with 16-bit result
- gallium/nir/tgsi: fixup indentation
- gallium/nir/tgsi: initialize file_max for inputs
- lavapipe: fix reported subpixel precision for lines
Filip Gawin (2):
- nir: fix shadowed variable in nir_lower_bit_size.c
- nir: fix ifind_msb_rev by using appropriate type
Ian Romanick (3):
- util: Add and use functions to calculate min and max int for a size
- nir/lower_bit_size: Support add_sat and sub_sat
- nir/lower_gs_intrinsics: Return progress if append_set_vertex_and_primitive_count makes progress
Icecream95 (1):
- pan/bi: Extend bi_add_nop_for_atest for tilebuffer loads
Ilia Mirkin (3):
- mesa: don't return errors for gl_* GetFragData* queries
- glsl: fix explicit-location ifc matching in presence of array types
- freedreno: use OUT_WFI for emit_marker
Jason Ekstrand (1):
- anv: Set CONTEXT_PARAM_RECOVERABLE to false
Jordan Justen (1):
- intel/isl: Enable MOCS 61 for external surfaces on TGL
Juan A. Suarez Romero (1):
- broadcom/compiler: force a last thrsw for spilling
Lionel Landwerlin (2):
- nir: prevent peephole from generating invalid NIR
- intel/fs: fix framebuffer reads
Mao, Marc (1):
- iris: declare padding for iris_vue_prog_key
Marcin Ślusarz (2):
- glsl: propagate errors from \*=, /=, +=, -= operators
- glsl: break out early if compound assignment's operand errored out
Marek Olšák (6):
- mesa: remove unused indices parameter from validate functions
- mesa: fix gl_DrawID with indirect multi draws using user indirect buffer
- mesa: skip draw calls with unaligned indices
- radeonsi: fix a memory leak in si_get_shader_binary_size
- radeonsi: disable DCC stores on Navi12-14 for displayable DCC to fix corruption
- radeonsi: strengthen the VGT_FLUSH condition in begin_new_gfx_cs
Mike Blumenkrantz (8):
- nir/lower_vectorize_tess_levels: set num_components for vectorized loads
- zink: fix pipeline caching
- radv: use pool stride when copying single query results
- zink: free local shader nirs on program free
- zink: destroy shader modules on program free to avoid leaking
- tgsi_to_nir: force int type for LAYER output
- util/primconvert: force restart rewrites if original primtype wasn't supported
- zink: fix ZINK_MAX_DESCRIPTORS_PER_TYPE to stop exploding the stack
Nanley Chery (1):
- intel/blorp: Fix Gfx7 stencil surface state valign
Neha Bhende (1):
- svga/drm: use pb_usage_flags instead of pipe_map_flags in vmw_svga_winsys_buffer_map
Quantum (1):
- main: allow all external textures for BindImageTexture
Rhys Perry (4):
- aco: include utility in isel
- aco: don't constant propagate to DPP instructions
- aco/spill: add temporary operands of exec phis to next_use_distances_end
- nir: fix serialization of loop/if control
Samuel Pitoiset (5):
- radv: fix fast clearing depth images with mips on GFX10+
- radv: fix copying depth+stencil images on compute
- radv: disable DCC image stores on Navi12-14 for displayable DCC corruption
- radv: fix determining the maximum number of waves that can use scratch
- radv/llvm: fix using Wave32
Simon Ser (4):
- etnaviv: add stride, offset and modifier to resource_get_param
- panfrost: implement resource_get_param
- vc4: implement resource_get_param
- v3d: implement resource_get_param
Timothy Arceri (6):
- glsl: fix variable scope for instructions inside case statements
- nir: move nir_block_ends_in_break() to nir.h
- mesa: fix mesa_problem() call in _mesa_program_state_flags()
- glsl: fix variable scope for loop-expression
- glsl: handle scope correctly when inlining loop expression
- glsl: fix variable scope for do-while loops
Timur Kristóf (7):
- aco: Fix to_uniform_bool_instr when operands are not suitable.
- aco: Emit zero for the derivatives of uniforms.
- aco: Unset 16 and 24-bit flags from operands in apply_extract.
- nir: Fix local_invocation_index upper bound for non-compute-like stages.
- aco: Fix invalid usage of std::fill with std::array.
- aco: Use Builder reference in emit_copies_block.
- aco: Skip code paths to emit copies when there are no copies.
Vinson Lee (1):
- freedreno: Require C++17.
Yevhenii Kharchenko (1):
- iris: fix layer calculation for TEXTURE_3D ReadPixels() on mip-level>0
liuyujun (1):
- gallium: fix surface->destroy use-after-free
mattvchandler (1):
- gallium/osmesa: fix buffer resizing

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@ -0,0 +1,139 @@
Mesa 21.2.3 Release Notes / 2021-09-29
======================================
Mesa 21.2.3 is a bug fix release which fixes bugs found since the 21.2.2 release.
Mesa 21.2.3 implements the OpenGL 4.6 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.6. OpenGL
4.6 is **only** available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
Mesa 21.2.3 implements the Vulkan 1.2 API, but the version reported by
the apiVersion property of the VkPhysicalDeviceProperties struct
depends on the particular driver being used.
SHA256 checksum
---------------
::
7245284a159d2484770e1835a673e79e4322a9ddf43b17859668244946db7174 mesa-21.2.3.tar.xz
New features
------------
- None
Bug fixes
---------
- Significant performance drop on Radeon HD 8400
- [nir][radv] Out of range shift when compiling Resident Evil Village shaders
- [nir][radv] Out of range shift when compiling Resident Evil Village shaders
- GL_EXT_disjoint_timer_query glGetInteger64v GL_TIMESTAMP failing with GL_INVALID_ENUM
- Possible miscompilation of an integer division with vulkan
Changes
-------
Boris Brezillon (3):
- panfrost: RGB10_A2_SNORM is not a valid texture format on v6+
- panfrost: RGB332_UNORM is not a valid texture format on v6+
- pan/blit: Fix a NULL dereference in the preload path
Charmaine Lee (1):
- svga: fix render target views leak
Dylan Baker (15):
- docs/relnotes/21.2.2: Add SHA256 sum
- .pick_status.json: Update to d3511e8af21ac11b8e7f5305942624d1ae29a73a
- .pick_status.json: Mark a79ac1bee14d6600cde2788bf136aa59b69a786f as backported
- .pick_status.json: Mark e0533ebf16edcb8b9f0687d3155417e6c1c53d35 as backported
- .pick_status.json: Mark f241bd3749cec55ca5fac9cb24f17553ab31c0e1 as backported
- .pick_status.json: Mark 268158a758551a46feb120af3f3cff5fb9292310 as backported
- .pick_status.json: Mark 6373dd814a74d84becbbbfc42673df147adb6e9b as denominated
- .pick_status.json: Mark eb7d2ef070a8819c2859c10559496836275848e2 as denominated
- .pick_status.json: Mark a810e58051b4a065b0aade86c45bf7ed254fc726 as denominated
- .pick_status.json: Update to 400da4900e2d72ee807cc3eedac9ace1dfd5dfba
- .pick_status.json: Update to dc354b8fda928861b7dfff3f8f53159e0053f9f5
- .pick_status.json: Update to b653164973bbd3053d3b9ed37c4362af96346900
- .pick_status.json: Update to ecc6d78b0541d66765d434dd4158066d6c664f8e
- .pick_status.json: Update to fbbe00c0b7f7aa5aca42a82358332eb2de56b9af
- lavapipe/ci: Add additional failing test
Ella-0 (1):
- v3d: add R10G10B10X2_UNORM to format table
Emma Anholt (1):
- mesa: Fix missing CopyTexImage formats for OES_required_internalformat.
Italo Nicola (1):
- panfrost: fix null deref when no color buffer is attached
Jordan Justen (2):
- iris: Disable I915_FORMAT_MOD_Y_TILED_GEN12* on adl-p/display 13
- intel/dev: Add display_ver and set adl-p to 13
Lionel Landwerlin (1):
- nir: fix opt_memcpy src/dst mixup
Marcin Ślusarz (1):
- intel/compiler: INT DIV function does not support source modifiers
Marek Olšák (2):
- radeonsi: fix a depth texturing performance regression on gfx6-7
- radeonsi: fix clearing index_size for NGG fast launch
Marek Vasut (1):
- freedreno: Handle timeout == PIPE_TIMEOUT_INFINITE and rollover
Neha Bhende (1):
- auxiliary/indices: convert primitive type PIPE_PRIM_PATCHES
Qiang Yu (1):
- radeonsi: fix ps SI_PARAM_LINE_STIPPLE_TEX arg
Rhys Perry (3):
- aco: don't coalesce constant copies into non-power-of-two sizes
- aco/tests: add idep_amdgfxregs_h
- radv: don't require a GS copy shader to use the cache with NGG VS+GS
Rob Clark (2):
- freedreno: Use correct key for binning pass shader
- freedreno/drm: Don't return shared/control bo's to cache
Tapani Pälli (1):
- mesa: fix timestamp enum with EXT_disjoint_timer_query
Timur Kristóf (5):
- aco/optimize_postRA: Use iterators instead of operator[] of std::array.
- ac/nir: Fix match_mask to work correctly for VS outputs.
- nir: Exclude non-generic patch variables from get_variable_io_mask.
- ac/nir/nggc: Refactor save_reusable_variables.
- ac/nir/nggc: Don't reuse uniform values from divergent control flow.
Zachary Michaels (1):
- X11: Ensure that VK_SUBOPTIMAL_KHR propagates to user code

147
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@ -0,0 +1,147 @@
Mesa 21.2.4 Release Notes / 2021-10-14
======================================
Mesa 21.2.4 is a bug fix release which fixes bugs found since the 21.2.3 release.
Mesa 21.2.4 implements the OpenGL 4.6 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.6. OpenGL
4.6 is **only** available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
Mesa 21.2.4 implements the Vulkan 1.2 API, but the version reported by
the apiVersion property of the VkPhysicalDeviceProperties struct
depends on the particular driver being used.
SHA256 checksum
---------------
::
fe6ede82d1ac02339da3c2ec1820a379641902fd351a52cc01153f76eff85b44 mesa-21.2.4.tar.xz
New features
------------
- None
Bug fixes
---------
- RADV: Rendering issues in Resident Evil 2 with NGGC
- crocus: Incorrect stride when used through prime
- anv: descriptorBindingUniformBufferUpdateAfterBind feature is not supported
Changes
-------
Alyssa Rosenzweig (3):
- panfrost: Move special_varying to compiler definitions
- panfrost: Fix off-by-one in varying count assert
- panfrost: Don't set CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
Bas Nieuwenhuizen (2):
- amd/common: Add fallback for misreported clocks for RGP.
- radv: Handle copying zero queries.
Chia-I Wu (1):
- radv: plug leaks in radv_device_init_accel_struct_build_state
Connor Abbott (1):
- ir3: Use source in ir3_output_conv_src_type()
Dave Airlie (7):
- crocus/query: don't loop on ready status after gpu hang.
- device_select: close dri3 fd after using it.
- crocus: Honor scanout requirement from DRI
- crocus/gen5: reemit shaders on gen5 after new program cache bo.
- crocus/gen5: add dirty flags for urb fences.
- crocus/gen6: don't reemit the svbi when debugging
- gallivm/format: clamp SINT conversion rather than truncate.
Dylan Baker (7):
- docs" Add SHA256 sum for mesa 21.2.3
- .pick_status.json: Update to fb8f532ea1bbd9c959e0f59c652347e435a71f91
- .pick_status.json: Update to d2543658ef6fe0ad59af217a09a931d3b6174a43
- .pick_status.json: Update to 729991e09cd28550001ae63710ab929d95b115bc
- .pick_status.json: Update to 3a18963b0876af2aa0d60dd9917e69d409ce4d6e
- .pick_status.json: Update to ced950e42f4a95ef410e63c2d26a2119e0c3c40b
- .pick_status.json: Update to 783f8f728ce8e77885adbc7b2c12c39c3e3e5198
Emma Anholt (2):
- gallium/dri: Make YUV formats we're going to emulate external-only.
- i915g: Check for the scanout-layout conditions before setting level info.
Filip Gawin (1):
- r300: implement forgotten tgsi's cases of textures
Gert Wollny (1):
- mesa: signal driver when buffer is bound to different texture format
Icecream95 (1):
- pan/mdg: Use the correct swizzle for condition moves
Jason Ekstrand (1):
- vulkan/shader_module: Fix the lifetime of temporary shader modules
Kai Wasserbäch (2):
- gallivm: add new wrapper around Module::setOverrideStackAlignment()
- gallivm: fix FTBFS on i386 with LLVM >= 13, StackAlignmentOverride is gone
Lionel Landwerlin (3):
- anv: enable UBO indexing
- anv: add missing transition handling bits
- spirv: deal with null pointers
Marek Olšák (2):
- radeonsi: add back a workaround for DCC MSAA on gfx9 due to conformance issues
- ac/surface: don't overwrite DCC settings for imported buffers
Pavel Asyutchenko (1):
- llvmpipe: fix crash when doing FB fetch + gl_FragDepth write in one shader
Qiang Yu (1):
- loader/dri3: fix swap out of order when changing swap interval
Rob Clark (1):
- freedreno/drm: Move pipe unref after fence removal
Samuel Pitoiset (2):
- radv: fix adjusting the frag coord when RADV_FORCE_VRS is enabled
- aco: fix load_barycentric_at_{offset,sample}
Timur Kristóf (3):
- aco: Fix small primitive precision.
- aco: Fix determining whether any culling is enabled.
- ac/nir/cull: Accept NaN and +/- Inf in face culling.
Vasily Khoruzhick (1):
- lima: split_load_input: don't split unaligned vec2
Vinson Lee (1):
- pps: Avoid duplicate elements in with_datasources array.

8
mesa 3D driver/docs/relnotes/new_features.txt
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@ -1,8 +0,0 @@
VK_EXT_color_write_enable on lavapipe
GL_ARB_texture_filter_anisotropic in llvmpipe
Anisotropic texture filtering in lavapipe
VK_EXT_shader_atomic_float2 on Intel and RADV.
VK_KHR_timeline_semaphore on lavapipe
VK_EXT_external_memory_host on lavapipe
GL_AMD_pinned_memory on llvmpipe
GL 4.5 compatibility on llvmpipe

18
mesa 3D driver/include/EGL/eglext.h
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@ -14,12 +14,12 @@ extern "C" {
** used to make the header, and the header can be found at
** http://www.khronos.org/registry/egl
**
** Khronos $Git commit SHA1: e8baa0bf39 $ on $Git commit date: 2021-04-26 17:56:26 -0600 $
** Khronos $Git commit SHA1: dc0b58dca5 $ on $Git commit date: 2021-06-25 01:58:50 +0200 $
*/
#include <EGL/eglplatform.h>
#define EGL_EGLEXT_VERSION 20210604
#define EGL_EGLEXT_VERSION 20210629
/* Generated C header for:
* API: egl
@ -651,6 +651,11 @@ EGLAPI EGLBoolean EGLAPIENTRY eglCompositorSwapPolicyEXT (EGLint external_win_id
#endif
#endif /* EGL_EXT_compositor */
#ifndef EGL_EXT_config_select_group
#define EGL_EXT_config_select_group 1
#define EGL_CONFIG_SELECT_GROUP_EXT 0x34C0
#endif /* EGL_EXT_config_select_group */
#ifndef EGL_EXT_create_context_robustness
#define EGL_EXT_create_context_robustness 1
#define EGL_CONTEXT_OPENGL_ROBUST_ACCESS_EXT 0x30BF
@ -702,6 +707,10 @@ EGLAPI EGLBoolean EGLAPIENTRY eglQueryDisplayAttribEXT (EGLDisplay dpy, EGLint a
#define EGL_DEVICE_UUID_EXT 0x335C
#define EGL_DRIVER_UUID_EXT 0x335D
#define EGL_DRIVER_NAME_EXT 0x335E
typedef EGLBoolean (EGLAPIENTRYP PFNEGLQUERYDEVICEBINARYEXTPROC) (EGLDeviceEXT device, EGLint name, EGLint max_size, void *value, EGLint *size);
#ifdef EGL_EGLEXT_PROTOTYPES
EGLAPI EGLBoolean EGLAPIENTRY eglQueryDeviceBinaryEXT (EGLDeviceEXT device, EGLint name, EGLint max_size, void *value, EGLint *size);
#endif
#endif /* EGL_EXT_device_persistent_id */
#ifndef EGL_EXT_device_query
@ -895,6 +904,11 @@ EGLAPI EGLSurface EGLAPIENTRY eglCreatePlatformPixmapSurfaceEXT (EGLDisplay dpy,
#define EGL_PLATFORM_XCB_SCREEN_EXT 0x31DE
#endif /* EGL_EXT_platform_xcb */
#ifndef EGL_EXT_present_opaque
#define EGL_EXT_present_opaque 1
#define EGL_PRESENT_OPAQUE_EXT 0x31DF
#endif /* EGL_EXT_present_opaque */
#ifndef EGL_EXT_protected_content
#define EGL_EXT_protected_content 1
#define EGL_PROTECTED_CONTENT_EXT 0x32C0

4
mesa 3D driver/include/GL/gl.h
View File

@ -38,9 +38,7 @@
#if defined(__WIN32__) && !defined(__CYGWIN__)
# if (defined(_MSC_VER) || defined(__MINGW32__)) && defined(BUILD_GL32) /* tag specify we're building mesa as a DLL */
# define GLAPI __declspec(dllexport)
# elif (defined(_MSC_VER) || defined(__MINGW32__)) && defined(_DLL) /* tag specifying we're building for DLL runtime support */
# define GLAPI __declspec(dllimport)
# else /* for use with static link lib build of Win32 edition only */
# else
# define GLAPI extern
# endif
# if defined(__MINGW32__) && defined(GL_NO_STDCALL) || defined(UNDER_CE) /* The generated DLLs by MingW with STDCALL are not compatible with the ones done by Microsoft's compilers */

160
mesa 3D driver/include/GL/internal/dri_interface.h
View File

@ -48,8 +48,6 @@ typedef unsigned int drm_drawable_t;
typedef struct drm_clip_rect drm_clip_rect_t;
#endif
#include <GL/gl.h>
#include <stdint.h>
/**
@ -153,32 +151,6 @@ struct __DRIswapControlExtensionRec {
unsigned int (*getSwapInterval)(__DRIdrawable *drawable);
};
/**
* Used by drivers that implement the GLX_MESA_swap_frame_usage extension.
*/
#define __DRI_FRAME_TRACKING "DRI_FrameTracking"
#define __DRI_FRAME_TRACKING_VERSION 1
struct __DRIframeTrackingExtensionRec {
__DRIextension base;
/**
* Enable or disable frame usage tracking.
*
* \since Internal API version 20030317.
*/
int (*frameTracking)(__DRIdrawable *drawable, GLboolean enable);
/**
* Retrieve frame usage information.
*
* \since Internal API version 20030317.
*/
int (*queryFrameTracking)(__DRIdrawable *drawable,
int64_t * sbc, int64_t * missedFrames,
float * lastMissedUsage, float * usage);
};
/**
* Used by drivers that implement the GLX_SGI_video_sync extension.
*/
@ -205,24 +177,6 @@ struct __DRImediaStreamCounterExtensionRec {
int64_t *msc);
};
#define __DRI_TEX_OFFSET "DRI_TexOffset"
#define __DRI_TEX_OFFSET_VERSION 1
struct __DRItexOffsetExtensionRec {
__DRIextension base;
/**
* Method to override base texture image with a driver specific 'offset'.
* The depth passed in allows e.g. to ignore the alpha channel of texture
* images where the non-alpha components don't occupy a whole texel.
*
* For GLX_EXT_texture_from_pixmap with AIGLX.
*/
void (*setTexOffset)(__DRIcontext *pDRICtx, GLint texname,
unsigned long long offset, GLint depth, GLuint pitch);
};
/* Valid values for format in the setTexBuffer2 function below. These
* values match the GLX tokens for compatibility reasons, but we
* define them here since the DRI interface can't depend on GLX. */
@ -243,7 +197,7 @@ struct __DRItexBufferExtensionRec {
* setTexBuffer2 in version 2 of this interface
*/
void (*setTexBuffer)(__DRIcontext *pDRICtx,
GLint target,
int target,
__DRIdrawable *pDraw);
/**
@ -255,8 +209,8 @@ struct __DRItexBufferExtensionRec {
* \since 2
*/
void (*setTexBuffer2)(__DRIcontext *pDRICtx,
GLint target,
GLint format,
int target,
int format,
__DRIdrawable *pDraw);
/**
* Method to release texture buffer in case some special platform
@ -267,7 +221,7 @@ struct __DRItexBufferExtensionRec {
* \since 3
*/
void (*releaseTexBuffer)(__DRIcontext *pDRICtx,
GLint target,
int target,
__DRIdrawable *pDraw);
};
@ -410,8 +364,8 @@ struct __DRI2fenceExtensionRec {
* \param flags a combination of __DRI2_FENCE_FLAG_xxx flags
* \param timeout the timeout in ns or __DRI2_FENCE_TIMEOUT_INFINITE
*/
GLboolean (*client_wait_sync)(__DRIcontext *ctx, void *fence,
unsigned flags, uint64_t timeout);
unsigned char (*client_wait_sync)(__DRIcontext *ctx, void *fence,
unsigned flags, uint64_t timeout);
/**
* This function enqueues a wait command into the command stream of
@ -549,28 +503,6 @@ typedef struct __DRIdamageExtensionRec __DRIdamageExtension;
typedef struct __DRIloaderExtensionRec __DRIloaderExtension;
typedef struct __DRIswrastLoaderExtensionRec __DRIswrastLoaderExtension;
/**
* Callback to getDrawableInfo protocol
*/
#define __DRI_GET_DRAWABLE_INFO "DRI_GetDrawableInfo"
#define __DRI_GET_DRAWABLE_INFO_VERSION 1
struct __DRIgetDrawableInfoExtensionRec {
__DRIextension base;
/**
* This function is used to get information about the position, size, and
* clip rects of a drawable.
*/
GLboolean (* getDrawableInfo) ( __DRIdrawable *drawable,
unsigned int * index, unsigned int * stamp,
int * x, int * y, int * width, int * height,
int * numClipRects, drm_clip_rect_t ** pClipRects,
int * backX, int * backY,
int * numBackClipRects, drm_clip_rect_t ** pBackClipRects,
void *loaderPrivate);
};
/**
* Callback to get system time for media stream counter extensions.
*/
@ -591,7 +523,7 @@ struct __DRIsystemTimeExtensionRec {
* the rate of the "media stream counter". In practical terms, this is
* the frame refresh rate of the display.
*/
GLboolean (*getMSCRate)(__DRIdrawable *draw,
unsigned char (*getMSCRate)(__DRIdrawable *draw,
int32_t * numerator, int32_t * denominator,
void *loaderPrivate);
};
@ -622,7 +554,7 @@ struct __DRIdamageExtensionRec {
void (*reportDamage)(__DRIdrawable *draw,
int x, int y,
drm_clip_rect_t *rects, int num_rects,
GLboolean front_buffer,
unsigned char front_buffer,
void *loaderPrivate);
};
@ -721,9 +653,9 @@ struct __DRIswrastLoaderExtensionRec {
*
* \since 6
*/
GLboolean (*getImageShm2)(__DRIdrawable *readable,
int x, int y, int width, int height,
int shmid, void *loaderPrivate);
unsigned char (*getImageShm2)(__DRIdrawable *readable,
int x, int y, int width, int height,
int shmid, void *loaderPrivate);
};
/**
@ -1305,7 +1237,7 @@ struct __DRIdri2ExtensionRec {
* extensions.
*/
#define __DRI_IMAGE "DRI_IMAGE"
#define __DRI_IMAGE_VERSION 19
#define __DRI_IMAGE_VERSION 20
/**
* These formats correspond to the similarly named MESA_FORMAT_*
@ -1476,9 +1408,10 @@ enum __DRIChromaSiting {
#define __BLIT_FLAG_FINISH 0x0002
/**
* Flags for createImageFromDmaBufs3
* Flags for createImageFromDmaBufs3 and createImageFromFds2
*/
#define __DRI_IMAGE_PROTECTED_CONTENT_FLAG 0x00000001
#define __DRI_IMAGE_PRIME_LINEAR_BUFFER 0x00000002
/**
* queryDmaBufFormatModifierAttribs attributes
@ -1509,7 +1442,7 @@ struct __DRIimageExtensionRec {
unsigned int use,
void *loaderPrivate);
GLboolean (*queryImage)(__DRIimage *image, int attrib, int *value);
unsigned char (*queryImage)(__DRIimage *image, int attrib, int *value);
/**
* The new __DRIimage will share the content with the old one, see dup(2).
@ -1521,7 +1454,7 @@ struct __DRIimageExtensionRec {
*
* \since 2
*/
GLboolean (*validateUsage)(__DRIimage *image, unsigned int use);
unsigned char (*validateUsage)(__DRIimage *image, unsigned int use);
/**
* Unlike createImageFromName __DRI_IMAGE_FORMAT is not used but instead
@ -1702,8 +1635,8 @@ struct __DRIimageExtensionRec {
*
* \since 15
*/
GLboolean (*queryDmaBufFormats)(__DRIscreen *screen, int max,
int *formats, int *count);
unsigned char (*queryDmaBufFormats)(__DRIscreen *screen, int max,
int *formats, int *count);
/*
* dmabuf format modifier query for a given format to support
@ -1724,10 +1657,10 @@ struct __DRIimageExtensionRec {
*
* \since 15
*/
GLboolean (*queryDmaBufModifiers)(__DRIscreen *screen, int fourcc,
int max, uint64_t *modifiers,
unsigned int *external_only,
int *count);
unsigned char (*queryDmaBufModifiers)(__DRIscreen *screen, int fourcc,
int max, uint64_t *modifiers,
unsigned int *external_only,
int *count);
/**
* dmabuf format modifier attribute query for a given format and modifier.
@ -1743,9 +1676,11 @@ struct __DRIimageExtensionRec {
*
* \since 16
*/
GLboolean (*queryDmaBufFormatModifierAttribs)(__DRIscreen *screen,
uint32_t fourcc, uint64_t modifier,
int attrib, uint64_t *value);
unsigned char (*queryDmaBufFormatModifierAttribs)(__DRIscreen *screen,
uint32_t fourcc,
uint64_t modifier,
int attrib,
uint64_t *value);
/**
* Create a DRI image from the given renderbuffer.
@ -1804,6 +1739,20 @@ struct __DRIimageExtensionRec {
const unsigned int modifier_count,
unsigned int use,
void *loaderPrivate);
/**
* Like createImageFromFds, but with an added flag parameter.
*
* See __DRI_IMAGE_*_FLAG for valid definitions of flags.
*
* \since 20
*/
__DRIimage *(*createImageFromFds2)(__DRIscreen *screen,
int width, int height, int fourcc,
int *fds, int num_fds,
uint32_t flags,
int *strides, int *offsets,
void *loaderPrivate);
};
@ -1817,14 +1766,36 @@ struct __DRIimageExtensionRec {
* with new lookup functions.
*/
#define __DRI_IMAGE_LOOKUP "DRI_IMAGE_LOOKUP"
#define __DRI_IMAGE_LOOKUP_VERSION 1
#define __DRI_IMAGE_LOOKUP_VERSION 2
typedef struct __DRIimageLookupExtensionRec __DRIimageLookupExtension;
struct __DRIimageLookupExtensionRec {
__DRIextension base;
/**
* Lookup EGLImage without validated. Equivalent to call
* validateEGLImage() then lookupEGLImageValidated().
*
* \since 1
*/
__DRIimage *(*lookupEGLImage)(__DRIscreen *screen, void *image,
void *loaderPrivate);
/**
* Check if EGLImage is associated with the EGL display before lookup with
* lookupEGLImageValidated(). It will hold EGLDisplay.Mutex, so is separated
* out from lookupEGLImage() to avoid deadlock.
*
* \since 2
*/
unsigned char (*validateEGLImage)(void *image, void *loaderPrivate);
/**
* Lookup EGLImage after validateEGLImage(). No lock in this function.
*
* \since 2
*/
__DRIimage *(*lookupEGLImageValidated)(void *image, void *loaderPrivate);
};
/**
@ -1969,6 +1940,7 @@ typedef struct __DRIDriverVtableExtensionRec {
#define __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH (1 << 2)
#define __DRI2_RENDERER_HAS_PROTECTED_CONTENT 0x000e
#define __DRI2_RENDERER_PREFER_BACK_BUFFER_REUSE 0x000f
typedef struct __DRI2rendererQueryExtensionRec __DRI2rendererQueryExtension;
struct __DRI2rendererQueryExtensionRec {
@ -2178,7 +2150,7 @@ struct __DRIbackgroundCallableExtensionRec {
* the context was created. This can be used by the loader to identify
* which context any callbacks are associated with.
*/
GLboolean (*isThreadSafe)(void *loaderPrivate);
unsigned char (*isThreadSafe)(void *loaderPrivate);
};
/**

7
mesa 3D driver/include/android_stub/android/hardware_buffer.h
View File

@ -332,8 +332,6 @@ typedef struct AHardwareBuffer_Planes {
*/
typedef struct AHardwareBuffer AHardwareBuffer;
#if __ANDROID_API__ >= 26
/**
* Allocates a buffer that matches the passed AHardwareBuffer_Desc.
*
@ -501,10 +499,6 @@ int AHardwareBuffer_sendHandleToUnixSocket(const AHardwareBuffer* buffer, int so
*/
int AHardwareBuffer_recvHandleFromUnixSocket(int socketFd, AHardwareBuffer** outBuffer) __INTRODUCED_IN(26);
#endif // __ANDROID_API__ >= 26
#if __ANDROID_API__ >= 29
/**
* Test whether the given format and usage flag combination is
* allocatable.
@ -540,7 +534,6 @@ int AHardwareBuffer_isSupported(const AHardwareBuffer_Desc* desc) __INTRODUCED_I
int AHardwareBuffer_lockAndGetInfo(AHardwareBuffer* buffer, uint64_t usage,
int32_t fence, const ARect* rect, void** outVirtualAddress,
int32_t* outBytesPerPixel, int32_t* outBytesPerStride) __INTRODUCED_IN(29);
#endif // __ANDROID_API__ >= 29
__END_DECLS

2
mesa 3D driver/include/android_stub/android/log.h
View File

@ -217,7 +217,6 @@ typedef void (*__android_logger_function)(const struct __android_log_message* lo
*/
typedef void (*__android_aborter_function)(const char* abort_message);
#if !defined(__ANDROID__) || __ANDROID_API__ >= 30
/**
* Writes the log message specified by log_message. log_message includes additional file name and
* line number information that a logger may use. log_message is versioned for backwards
@ -371,7 +370,6 @@ int32_t __android_log_get_minimum_priority(void) __INTRODUCED_IN(30);
* Available since API level 30.
*/
void __android_log_set_default_tag(const char* tag) __INTRODUCED_IN(30);
#endif
#ifdef __cplusplus
}

12
mesa 3D driver/include/android_stub/android/native_window.h
View File

@ -185,8 +185,6 @@ int32_t ANativeWindow_lock(ANativeWindow* window, ANativeWindow_Buffer* outBuffe
*/
int32_t ANativeWindow_unlockAndPost(ANativeWindow* window);
#if __ANDROID_API__ >= 26
/**
* Set a transform that will be applied to future buffers posted to the window.
*
@ -197,10 +195,6 @@ int32_t ANativeWindow_unlockAndPost(ANativeWindow* window);
*/
int32_t ANativeWindow_setBuffersTransform(ANativeWindow* window, int32_t transform) __INTRODUCED_IN(26);
#endif // __ANDROID_API__ >= 26
#if __ANDROID_API__ >= 28
/**
* All buffers queued after this call will be associated with the dataSpace
* parameter specified.
@ -229,10 +223,6 @@ int32_t ANativeWindow_setBuffersDataSpace(ANativeWindow* window, int32_t dataSpa
*/
int32_t ANativeWindow_getBuffersDataSpace(ANativeWindow* window) __INTRODUCED_IN(28);
#endif // __ANDROID_API__ >= 28
#if __ANDROID_API__ >= 30
/** Compatibility value for ANativeWindow_setFrameRate. */
enum ANativeWindow_FrameRateCompatibility {
/**
@ -301,8 +291,6 @@ int32_t ANativeWindow_setFrameRate(ANativeWindow* window, float frameRate, int8_
*/
void ANativeWindow_tryAllocateBuffers(ANativeWindow* window);
#endif // __ANDROID_API__ >= 30
#ifdef __cplusplus
};
#endif

44
mesa 3D driver/include/android_stub/cutils/compiler.h Normal file
View File

@ -0,0 +1,44 @@
/*
* Copyright (C) 2009 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef ANDROID_CUTILS_COMPILER_H
#define ANDROID_CUTILS_COMPILER_H
/*
* helps the compiler's optimizer predicting branches
*/
#ifdef __cplusplus
# define CC_LIKELY( exp ) (__builtin_expect( !!(exp), true ))
# define CC_UNLIKELY( exp ) (__builtin_expect( !!(exp), false ))
#else
# define CC_LIKELY( exp ) (__builtin_expect( !!(exp), 1 ))
# define CC_UNLIKELY( exp ) (__builtin_expect( !!(exp), 0 ))
#endif
/**
* exports marked symbols
*
* if used on a C++ class declaration, this macro must be inserted
* after the "class" keyword. For instance:
*
* template <typename TYPE>
* class ANDROID_API Singleton { }
*/
#define ANDROID_API __attribute__((visibility("default")))
#endif // ANDROID_CUTILS_COMPILER_H

238
mesa 3D driver/include/android_stub/cutils/trace.h Normal file
View File

@ -0,0 +1,238 @@
/*
* Copyright (C) 2012 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _LIBS_CUTILS_TRACE_H
#define _LIBS_CUTILS_TRACE_H
#include <inttypes.h>
#include <stdatomic.h>
#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
#include <sys/cdefs.h>
#include <sys/types.h>
#include <unistd.h>
#include <cutils/compiler.h>
__BEGIN_DECLS
/**
* The ATRACE_TAG macro can be defined before including this header to trace
* using one of the tags defined below. It must be defined to one of the
* following ATRACE_TAG_* macros. The trace tag is used to filter tracing in
* userland to avoid some of the runtime cost of tracing when it is not desired.
*
* Defining ATRACE_TAG to be ATRACE_TAG_ALWAYS will result in the tracing always
* being enabled - this should ONLY be done for debug code, as userland tracing
* has a performance cost even when the trace is not being recorded. Defining
* ATRACE_TAG to be ATRACE_TAG_NEVER or leaving ATRACE_TAG undefined will result
* in the tracing always being disabled.
*
* ATRACE_TAG_HAL should be bitwise ORed with the relevant tags for tracing
* within a hardware module. For example a camera hardware module would set:
* #define ATRACE_TAG (ATRACE_TAG_CAMERA | ATRACE_TAG_HAL)
*
* Keep these in sync with frameworks/base/core/java/android/os/Trace.java.
*/
#define ATRACE_TAG_NEVER 0 // This tag is never enabled.
#define ATRACE_TAG_ALWAYS (1<<0) // This tag is always enabled.
#define ATRACE_TAG_GRAPHICS (1<<1)
#define ATRACE_TAG_INPUT (1<<2)
#define ATRACE_TAG_VIEW (1<<3)
#define ATRACE_TAG_WEBVIEW (1<<4)
#define ATRACE_TAG_WINDOW_MANAGER (1<<5)
#define ATRACE_TAG_ACTIVITY_MANAGER (1<<6)
#define ATRACE_TAG_SYNC_MANAGER (1<<7)
#define ATRACE_TAG_AUDIO (1<<8)
#define ATRACE_TAG_VIDEO (1<<9)
#define ATRACE_TAG_CAMERA (1<<10)
#define ATRACE_TAG_HAL (1<<11)
#define ATRACE_TAG_APP (1<<12)
#define ATRACE_TAG_RESOURCES (1<<13)
#define ATRACE_TAG_DALVIK (1<<14)
#define ATRACE_TAG_RS (1<<15)
#define ATRACE_TAG_BIONIC (1<<16)
#define ATRACE_TAG_POWER (1<<17)
#define ATRACE_TAG_PACKAGE_MANAGER (1<<18)
#define ATRACE_TAG_SYSTEM_SERVER (1<<19)
#define ATRACE_TAG_DATABASE (1<<20)
#define ATRACE_TAG_NETWORK (1<<21)
#define ATRACE_TAG_ADB (1<<22)
#define ATRACE_TAG_VIBRATOR (1<<23)
#define ATRACE_TAG_AIDL (1<<24)
#define ATRACE_TAG_NNAPI (1<<25)
#define ATRACE_TAG_RRO (1<<26)
#define ATRACE_TAG_LAST ATRACE_TAG_RRO
// Reserved for initialization.
#define ATRACE_TAG_NOT_READY (1ULL<<63)
#define ATRACE_TAG_VALID_MASK ((ATRACE_TAG_LAST - 1) | ATRACE_TAG_LAST)
#ifndef ATRACE_TAG
#define ATRACE_TAG ATRACE_TAG_NEVER
#elif ATRACE_TAG > ATRACE_TAG_VALID_MASK
#error ATRACE_TAG must be defined to be one of the tags defined in cutils/trace.h
#endif
/**
* Opens the trace file for writing and reads the property for initial tags.
* The atrace.tags.enableflags property sets the tags to trace.
* This function should not be explicitly called, the first call to any normal
* trace function will cause it to be run safely.
*/
void atrace_setup();
/**
* If tracing is ready, set atrace_enabled_tags to the system property
* debug.atrace.tags.enableflags. Can be used as a sysprop change callback.
*/
void atrace_update_tags();
/**
* Set whether tracing is enabled for the current process. This is used to
* prevent tracing within the Zygote process.
*/
void atrace_set_tracing_enabled(bool enabled);
/**
* This is always set to false. This forces code that uses an old version
* of this header to always call into atrace_setup, in which we call
* atrace_init unconditionally.
*/
extern atomic_bool atrace_is_ready;
/**
* Set of ATRACE_TAG flags to trace for, initialized to ATRACE_TAG_NOT_READY.
* A value of zero indicates setup has failed.
* Any other nonzero value indicates setup has succeeded, and tracing is on.
*/
extern uint64_t atrace_enabled_tags;
/**
* Handle to the kernel's trace buffer, initialized to -1.
* Any other value indicates setup has succeeded, and is a valid fd for tracing.
*/
extern int atrace_marker_fd;
/**
* atrace_init readies the process for tracing by opening the trace_marker file.
* Calling any trace function causes this to be run, so calling it is optional.
* This can be explicitly run to avoid setup delay on first trace function.
*/
#define ATRACE_INIT() atrace_init()
#define ATRACE_GET_ENABLED_TAGS() atrace_get_enabled_tags()
void atrace_init();
uint64_t atrace_get_enabled_tags();
/**
* Test if a given tag is currently enabled.
* Returns nonzero if the tag is enabled, otherwise zero.
* It can be used as a guard condition around more expensive trace calculations.
*/
#define ATRACE_ENABLED() atrace_is_tag_enabled(ATRACE_TAG)
static inline uint64_t atrace_is_tag_enabled(uint64_t tag)
{
return atrace_get_enabled_tags() & tag;
}
/**
* Trace the beginning of a context. name is used to identify the context.
* This is often used to time function execution.
*/
#define ATRACE_BEGIN(name) atrace_begin(ATRACE_TAG, name)
static inline void atrace_begin(uint64_t tag, const char* name)
{
if (CC_UNLIKELY(atrace_is_tag_enabled(tag))) {
void atrace_begin_body(const char*);
atrace_begin_body(name);
}
}
/**
* Trace the end of a context.
* This should match up (and occur after) a corresponding ATRACE_BEGIN.
*/
#define ATRACE_END() atrace_end(ATRACE_TAG)
static inline void atrace_end(uint64_t tag)
{
if (CC_UNLIKELY(atrace_is_tag_enabled(tag))) {
void atrace_end_body();
atrace_end_body();
}
}
/**
* Trace the beginning of an asynchronous event. Unlike ATRACE_BEGIN/ATRACE_END
* contexts, asynchronous events do not need to be nested. The name describes
* the event, and the cookie provides a unique identifier for distinguishing
* simultaneous events. The name and cookie used to begin an event must be
* used to end it.
*/
#define ATRACE_ASYNC_BEGIN(name, cookie) \
atrace_async_begin(ATRACE_TAG, name, cookie)
static inline void atrace_async_begin(uint64_t tag, const char* name,
int32_t cookie)
{
if (CC_UNLIKELY(atrace_is_tag_enabled(tag))) {
void atrace_async_begin_body(const char*, int32_t);
atrace_async_begin_body(name, cookie);
}
}
/**
* Trace the end of an asynchronous event.
* This should have a corresponding ATRACE_ASYNC_BEGIN.
*/
#define ATRACE_ASYNC_END(name, cookie) atrace_async_end(ATRACE_TAG, name, cookie)
static inline void atrace_async_end(uint64_t tag, const char* name, int32_t cookie)
{
if (CC_UNLIKELY(atrace_is_tag_enabled(tag))) {
void atrace_async_end_body(const char*, int32_t);
atrace_async_end_body(name, cookie);
}
}
/**
* Traces an integer counter value. name is used to identify the counter.
* This can be used to track how a value changes over time.
*/
#define ATRACE_INT(name, value) atrace_int(ATRACE_TAG, name, value)
static inline void atrace_int(uint64_t tag, const char* name, int32_t value)
{
if (CC_UNLIKELY(atrace_is_tag_enabled(tag))) {
void atrace_int_body(const char*, int32_t);
atrace_int_body(name, value);
}
}
/**
* Traces a 64-bit integer counter value. name is used to identify the
* counter. This can be used to track how a value changes over time.
*/
#define ATRACE_INT64(name, value) atrace_int64(ATRACE_TAG, name, value)
static inline void atrace_int64(uint64_t tag, const char* name, int64_t value)
{
if (CC_UNLIKELY(atrace_is_tag_enabled(tag))) {
void atrace_int64_body(const char*, int64_t);
atrace_int64_body(name, value);
}
}
__END_DECLS
#endif // _LIBS_CUTILS_TRACE_H

10
mesa 3D driver/include/android_stub/log/log_main.h
View File

@ -364,13 +364,11 @@ int __android_log_is_loggable(int prio, const char* tag, int default_prio);
int __android_log_is_loggable_len(int prio, const char* tag, size_t len, int default_prio);
#if LOG_NDEBUG /* Production */
#define android_testLog(prio, tag) \
(__android_log_is_loggable_len(prio, tag, ((tag) && *(tag)) ? strlen(tag) : 0, \
ANDROID_LOG_DEBUG) != 0)
#define android_testLog(prio, tag) \
(__android_log_is_loggable_len(prio, tag, (tag) ? strlen(tag) : 0, ANDROID_LOG_DEBUG) != 0)
#else
#define android_testLog(prio, tag) \
(__android_log_is_loggable_len(prio, tag, ((tag) && *(tag)) ? strlen(tag) : 0, \
ANDROID_LOG_VERBOSE) != 0)
#define android_testLog(prio, tag) \
(__android_log_is_loggable_len(prio, tag, (tag) ? strlen(tag) : 0, ANDROID_LOG_VERBOSE) != 0)
#endif
#if defined(__clang__)

4
mesa 3D driver/include/android_stub/ndk/sync.h
View File

@ -33,8 +33,6 @@
__BEGIN_DECLS
#if __ANDROID_API__ >= 26
/* Fences indicate the status of an asynchronous task. They are initially
* in unsignaled state (0), and make a one-time transition to either signaled
* (1) or error (< 0) state. A sync file is a collection of one or more fences;
@ -101,8 +99,6 @@ static inline struct sync_fence_info* sync_get_fence_info(const struct sync_file
*/
void sync_file_info_free(struct sync_file_info* info) __INTRODUCED_IN(26);
#endif /* __ANDROID_API__ >= 26 */
__END_DECLS
#endif /* ANDROID_SYNC_H */

14
mesa 3D driver/include/android_stub/vndk/hardware_buffer.h
View File

@ -81,6 +81,20 @@ enum {
AHARDWAREBUFFER_FORMAT_YCbCr_422_I = 0x14,
};
/**
* Buffer usage flags.
*/
enum {
/* for future proofing, keep these in sync with hardware/gralloc.h */
/* The buffer will be written by the HW camera pipeline. */
AHARDWAREBUFFER_USAGE_CAMERA_WRITE = 2UL << 16,
/* The buffer will be read by the HW camera pipeline. */
AHARDWAREBUFFER_USAGE_CAMERA_READ = 4UL << 16,
/* Mask for the camera access values. */
AHARDWAREBUFFER_USAGE_CAMERA_MASK = 6UL << 16,
};
__END_DECLS
#endif /* ANDROID_VNDK_NATIVEWINDOW_AHARDWAREBUFFER_H */

27
mesa 3D driver/include/drm-uapi/virtgpu_drm.h
View File

@ -47,12 +47,15 @@ extern "C" {
#define DRM_VIRTGPU_WAIT 0x08
#define DRM_VIRTGPU_GET_CAPS 0x09
#define DRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x0a
#define DRM_VIRTGPU_CONTEXT_INIT 0x0b
#define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01
#define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02
#define VIRTGPU_EXECBUF_RING_IDX 0x04
#define VIRTGPU_EXECBUF_FLAGS (\
VIRTGPU_EXECBUF_FENCE_FD_IN |\
VIRTGPU_EXECBUF_FENCE_FD_OUT |\
VIRTGPU_EXECBUF_RING_IDX |\
0)
struct drm_virtgpu_map {
@ -68,6 +71,8 @@ struct drm_virtgpu_execbuffer {
__u64 bo_handles;
__u32 num_bo_handles;
__s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */
__u32 ring_idx; /* command ring index (see VIRTGPU_EXECBUF_RING_IDX) */
__u32 pad;
};
#define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
@ -75,6 +80,8 @@ struct drm_virtgpu_execbuffer {
#define VIRTGPU_PARAM_RESOURCE_BLOB 3 /* DRM_VIRTGPU_RESOURCE_CREATE_BLOB */
#define VIRTGPU_PARAM_HOST_VISIBLE 4 /* Host blob resources are mappable */
#define VIRTGPU_PARAM_CROSS_DEVICE 5 /* Cross virtio-device resource sharing */
#define VIRTGPU_PARAM_CONTEXT_INIT 6 /* DRM_VIRTGPU_CONTEXT_INIT */
#define VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs 7 /* Bitmask of supported capability set ids */
struct drm_virtgpu_getparam {
__u64 param;
@ -173,6 +180,22 @@ struct drm_virtgpu_resource_create_blob {
__u64 blob_id;
};
#define VIRTGPU_CONTEXT_PARAM_CAPSET_ID 0x0001
#define VIRTGPU_CONTEXT_PARAM_NUM_RINGS 0x0002
#define VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK 0x0003
struct drm_virtgpu_context_set_param {
__u64 param;
__u64 value;
};
struct drm_virtgpu_context_init {
__u32 num_params;
__u32 pad;
/* pointer to drm_virtgpu_context_set_param array */
__u64 ctx_set_params;
};
#define DRM_IOCTL_VIRTGPU_MAP \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
@ -212,6 +235,10 @@ struct drm_virtgpu_resource_create_blob {
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB, \
struct drm_virtgpu_resource_create_blob)
#define DRM_IOCTL_VIRTGPU_CONTEXT_INIT \
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_CONTEXT_INIT, \
struct drm_virtgpu_context_init)
#if defined(__cplusplus)
}
#endif

15
mesa 3D driver/include/vulkan/vulkan_android.h
View File

@ -44,7 +44,7 @@ VKAPI_ATTR VkResult VKAPI_CALL vkCreateAndroidSurfaceKHR(
#define VK_ANDROID_external_memory_android_hardware_buffer 1
struct AHardwareBuffer;
#define VK_ANDROID_EXTERNAL_MEMORY_ANDROID_HARDWARE_BUFFER_SPEC_VERSION 3
#define VK_ANDROID_EXTERNAL_MEMORY_ANDROID_HARDWARE_BUFFER_SPEC_VERSION 4
#define VK_ANDROID_EXTERNAL_MEMORY_ANDROID_HARDWARE_BUFFER_EXTENSION_NAME "VK_ANDROID_external_memory_android_hardware_buffer"
typedef struct VkAndroidHardwareBufferUsageANDROID {
VkStructureType sType;
@ -90,6 +90,19 @@ typedef struct VkExternalFormatANDROID {
uint64_t externalFormat;
} VkExternalFormatANDROID;
typedef struct VkAndroidHardwareBufferFormatProperties2ANDROID {
VkStructureType sType;
void* pNext;
VkFormat format;
uint64_t externalFormat;
VkFormatFeatureFlags2KHR formatFeatures;
VkComponentMapping samplerYcbcrConversionComponents;
VkSamplerYcbcrModelConversion suggestedYcbcrModel;
VkSamplerYcbcrRange suggestedYcbcrRange;
VkChromaLocation suggestedXChromaOffset;
VkChromaLocation suggestedYChromaOffset;
} VkAndroidHardwareBufferFormatProperties2ANDROID;
typedef VkResult (VKAPI_PTR *PFN_vkGetAndroidHardwareBufferPropertiesANDROID)(VkDevice device, const struct AHardwareBuffer* buffer, VkAndroidHardwareBufferPropertiesANDROID* pProperties);
typedef VkResult (VKAPI_PTR *PFN_vkGetMemoryAndroidHardwareBufferANDROID)(VkDevice device, const VkMemoryGetAndroidHardwareBufferInfoANDROID* pInfo, struct AHardwareBuffer** pBuffer);

99
mesa 3D driver/include/vulkan/vulkan_beta.h
View File

@ -22,7 +22,7 @@ extern "C" {
#define VK_KHR_video_queue 1
VK_DEFINE_NON_DISPATCHABLE_HANDLE(VkVideoSessionKHR)
VK_DEFINE_NON_DISPATCHABLE_HANDLE(VkVideoSessionParametersKHR)
#define VK_KHR_VIDEO_QUEUE_SPEC_VERSION 1
#define VK_KHR_VIDEO_QUEUE_SPEC_VERSION 2
#define VK_KHR_VIDEO_QUEUE_EXTENSION_NAME "VK_KHR_video_queue"
typedef enum VkQueryResultStatusKHR {
@ -66,12 +66,12 @@ typedef enum VkVideoComponentBitDepthFlagBitsKHR {
} VkVideoComponentBitDepthFlagBitsKHR;
typedef VkFlags VkVideoComponentBitDepthFlagsKHR;
typedef enum VkVideoCapabilitiesFlagBitsKHR {
VK_VIDEO_CAPABILITIES_PROTECTED_CONTENT_BIT_KHR = 0x00000001,
VK_VIDEO_CAPABILITIES_SEPARATE_REFERENCE_IMAGES_BIT_KHR = 0x00000002,
VK_VIDEO_CAPABILITIES_FLAG_BITS_MAX_ENUM_KHR = 0x7FFFFFFF
} VkVideoCapabilitiesFlagBitsKHR;
typedef VkFlags VkVideoCapabilitiesFlagsKHR;
typedef enum VkVideoCapabilityFlagBitsKHR {
VK_VIDEO_CAPABILITY_PROTECTED_CONTENT_BIT_KHR = 0x00000001,
VK_VIDEO_CAPABILITY_SEPARATE_REFERENCE_IMAGES_BIT_KHR = 0x00000002,
VK_VIDEO_CAPABILITY_FLAG_BITS_MAX_ENUM_KHR = 0x7FFFFFFF
} VkVideoCapabilityFlagBitsKHR;
typedef VkFlags VkVideoCapabilityFlagsKHR;
typedef enum VkVideoSessionCreateFlagBitsKHR {
VK_VIDEO_SESSION_CREATE_DEFAULT_KHR = 0,
@ -90,7 +90,6 @@ typedef enum VkVideoCodingControlFlagBitsKHR {
typedef VkFlags VkVideoCodingControlFlagsKHR;
typedef enum VkVideoCodingQualityPresetFlagBitsKHR {
VK_VIDEO_CODING_QUALITY_PRESET_DEFAULT_BIT_KHR = 0,
VK_VIDEO_CODING_QUALITY_PRESET_NORMAL_BIT_KHR = 0x00000001,
VK_VIDEO_CODING_QUALITY_PRESET_POWER_BIT_KHR = 0x00000002,
VK_VIDEO_CODING_QUALITY_PRESET_QUALITY_BIT_KHR = 0x00000004,
@ -120,16 +119,16 @@ typedef struct VkVideoProfilesKHR {
} VkVideoProfilesKHR;
typedef struct VkVideoCapabilitiesKHR {
VkStructureType sType;
void* pNext;
VkVideoCapabilitiesFlagsKHR capabilityFlags;
VkDeviceSize minBitstreamBufferOffsetAlignment;
VkDeviceSize minBitstreamBufferSizeAlignment;
VkExtent2D videoPictureExtentGranularity;
VkExtent2D minExtent;
VkExtent2D maxExtent;
uint32_t maxReferencePicturesSlotsCount;
uint32_t maxReferencePicturesActiveCount;
VkStructureType sType;
void* pNext;
VkVideoCapabilityFlagsKHR capabilityFlags;
VkDeviceSize minBitstreamBufferOffsetAlignment;
VkDeviceSize minBitstreamBufferSizeAlignment;
VkExtent2D videoPictureExtentGranularity;
VkExtent2D minExtent;
VkExtent2D maxExtent;
uint32_t maxReferencePicturesSlotsCount;
uint32_t maxReferencePicturesActiveCount;
} VkVideoCapabilitiesKHR;
typedef struct VkPhysicalDeviceVideoFormatInfoKHR {
@ -305,7 +304,7 @@ VKAPI_ATTR void VKAPI_CALL vkCmdControlVideoCodingKHR(
#define VK_KHR_video_decode_queue 1
#define VK_KHR_VIDEO_DECODE_QUEUE_SPEC_VERSION 1
#define VK_KHR_VIDEO_DECODE_QUEUE_SPEC_VERSION 2
#define VK_KHR_VIDEO_DECODE_QUEUE_EXTENSION_NAME "VK_KHR_video_decode_queue"
typedef enum VkVideoDecodeFlagBitsKHR {
@ -370,7 +369,7 @@ typedef struct VkPhysicalDevicePortabilitySubsetPropertiesKHR {
#define VK_KHR_video_encode_queue 1
#define VK_KHR_VIDEO_ENCODE_QUEUE_SPEC_VERSION 2
#define VK_KHR_VIDEO_ENCODE_QUEUE_SPEC_VERSION 3
#define VK_KHR_VIDEO_ENCODE_QUEUE_EXTENSION_NAME "VK_KHR_video_encode_queue"
typedef enum VkVideoEncodeFlagBitsKHR {
@ -433,10 +432,10 @@ VKAPI_ATTR void VKAPI_CALL vkCmdEncodeVideoKHR(
#define VK_EXT_video_encode_h264 1
#include "vk_video/vulkan_video_codec_h264std.h"
#include "vk_video/vulkan_video_codec_h264std_encode.h"
#define VK_EXT_VIDEO_ENCODE_H264_SPEC_VERSION 1
#define VK_EXT_VIDEO_ENCODE_H264_SPEC_VERSION 2
#define VK_EXT_VIDEO_ENCODE_H264_EXTENSION_NAME "VK_EXT_video_encode_h264"
typedef enum VkVideoEncodeH264CapabilitiesFlagBitsEXT {
typedef enum VkVideoEncodeH264CapabilityFlagBitsEXT {
VK_VIDEO_ENCODE_H264_CAPABILITY_CABAC_BIT_EXT = 0x00000001,
VK_VIDEO_ENCODE_H264_CAPABILITY_CAVLC_BIT_EXT = 0x00000002,
VK_VIDEO_ENCODE_H264_CAPABILITY_WEIGHTED_BI_PRED_IMPLICIT_BIT_EXT = 0x00000004,
@ -448,9 +447,9 @@ typedef enum VkVideoEncodeH264CapabilitiesFlagBitsEXT {
VK_VIDEO_ENCODE_H264_CAPABILITY_DEBLOCKING_FILTER_PARTIAL_BIT_EXT = 0x00000100,
VK_VIDEO_ENCODE_H264_CAPABILITY_MULTIPLE_SLICE_PER_FRAME_BIT_EXT = 0x00000200,
VK_VIDEO_ENCODE_H264_CAPABILITY_EVENLY_DISTRIBUTED_SLICE_SIZE_BIT_EXT = 0x00000400,
VK_VIDEO_ENCODE_H264_CAPABILITIES_FLAG_BITS_MAX_ENUM_EXT = 0x7FFFFFFF
} VkVideoEncodeH264CapabilitiesFlagBitsEXT;
typedef VkFlags VkVideoEncodeH264CapabilitiesFlagsEXT;
VK_VIDEO_ENCODE_H264_CAPABILITY_FLAG_BITS_MAX_ENUM_EXT = 0x7FFFFFFF
} VkVideoEncodeH264CapabilityFlagBitsEXT;
typedef VkFlags VkVideoEncodeH264CapabilityFlagsEXT;
typedef enum VkVideoEncodeH264InputModeFlagBitsEXT {
VK_VIDEO_ENCODE_H264_INPUT_MODE_FRAME_BIT_EXT = 0x00000001,
@ -475,19 +474,19 @@ typedef enum VkVideoEncodeH264CreateFlagBitsEXT {
} VkVideoEncodeH264CreateFlagBitsEXT;
typedef VkFlags VkVideoEncodeH264CreateFlagsEXT;
typedef struct VkVideoEncodeH264CapabilitiesEXT {
VkStructureType sType;
const void* pNext;
VkVideoEncodeH264CapabilitiesFlagsEXT flags;
VkVideoEncodeH264InputModeFlagsEXT inputModeFlags;
VkVideoEncodeH264OutputModeFlagsEXT outputModeFlags;
VkExtent2D minPictureSizeInMbs;
VkExtent2D maxPictureSizeInMbs;
VkExtent2D inputImageDataAlignment;
uint8_t maxNumL0ReferenceForP;
uint8_t maxNumL0ReferenceForB;
uint8_t maxNumL1Reference;
uint8_t qualityLevelCount;
VkExtensionProperties stdExtensionVersion;
VkStructureType sType;
const void* pNext;
VkVideoEncodeH264CapabilityFlagsEXT flags;
VkVideoEncodeH264InputModeFlagsEXT inputModeFlags;
VkVideoEncodeH264OutputModeFlagsEXT outputModeFlags;
VkExtent2D minPictureSizeInMbs;
VkExtent2D maxPictureSizeInMbs;
VkExtent2D inputImageDataAlignment;
uint8_t maxNumL0ReferenceForP;
uint8_t maxNumL0ReferenceForB;
uint8_t maxNumL1Reference;
uint8_t qualityLevelCount;
VkExtensionProperties stdExtensionVersion;
} VkVideoEncodeH264CapabilitiesEXT;
typedef struct VkVideoEncodeH264SessionCreateInfoEXT {
@ -567,22 +566,22 @@ typedef struct VkVideoEncodeH264ProfileEXT {
#define VK_EXT_video_decode_h264 1
#include "vk_video/vulkan_video_codec_h264std_decode.h"
#define VK_EXT_VIDEO_DECODE_H264_SPEC_VERSION 1
#define VK_EXT_VIDEO_DECODE_H264_SPEC_VERSION 3
#define VK_EXT_VIDEO_DECODE_H264_EXTENSION_NAME "VK_EXT_video_decode_h264"
typedef enum VkVideoDecodeH264FieldLayoutFlagBitsEXT {
VK_VIDEO_DECODE_H264_PROGRESSIVE_PICTURES_ONLY_EXT = 0,
VK_VIDEO_DECODE_H264_FIELD_LAYOUT_LINE_INTERLACED_PLANE_BIT_EXT = 0x00000001,
VK_VIDEO_DECODE_H264_FIELD_LAYOUT_SEPARATE_INTERLACED_PLANE_BIT_EXT = 0x00000002,
VK_VIDEO_DECODE_H264_FIELD_LAYOUT_FLAG_BITS_MAX_ENUM_EXT = 0x7FFFFFFF
} VkVideoDecodeH264FieldLayoutFlagBitsEXT;
typedef VkFlags VkVideoDecodeH264FieldLayoutFlagsEXT;
typedef enum VkVideoDecodeH264PictureLayoutFlagBitsEXT {
VK_VIDEO_DECODE_H264_PICTURE_LAYOUT_PROGRESSIVE_EXT = 0,
VK_VIDEO_DECODE_H264_PICTURE_LAYOUT_INTERLACED_INTERLEAVED_LINES_BIT_EXT = 0x00000001,
VK_VIDEO_DECODE_H264_PICTURE_LAYOUT_INTERLACED_SEPARATE_PLANES_BIT_EXT = 0x00000002,
VK_VIDEO_DECODE_H264_PICTURE_LAYOUT_FLAG_BITS_MAX_ENUM_EXT = 0x7FFFFFFF
} VkVideoDecodeH264PictureLayoutFlagBitsEXT;
typedef VkFlags VkVideoDecodeH264PictureLayoutFlagsEXT;
typedef VkFlags VkVideoDecodeH264CreateFlagsEXT;
typedef struct VkVideoDecodeH264ProfileEXT {
VkStructureType sType;
const void* pNext;
StdVideoH264ProfileIdc stdProfileIdc;
VkVideoDecodeH264FieldLayoutFlagsEXT fieldLayout;
VkStructureType sType;
const void* pNext;
StdVideoH264ProfileIdc stdProfileIdc;
VkVideoDecodeH264PictureLayoutFlagsEXT pictureLayout;
} VkVideoDecodeH264ProfileEXT;
typedef struct VkVideoDecodeH264CapabilitiesEXT {

298
mesa 3D driver/include/vulkan/vulkan_core.h
View File

@ -20,7 +20,7 @@ extern "C" {
#define VK_VERSION_1_0 1
#include "vulkan/vk_platform.h"
#include "vk_platform.h"
#define VK_DEFINE_HANDLE(object) typedef struct object##_T* object;
@ -72,7 +72,7 @@ extern "C" {
#define VK_API_VERSION_1_0 VK_MAKE_API_VERSION(0, 1, 0, 0)// Patch version should always be set to 0
// Version of this file
#define VK_HEADER_VERSION 185
#define VK_HEADER_VERSION 195
// Complete version of this file
#define VK_HEADER_VERSION_COMPLETE VK_MAKE_API_VERSION(0, 1, 2, VK_HEADER_VERSION)
@ -565,6 +565,7 @@ typedef enum VkStructureType {
VK_STRUCTURE_TYPE_IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID = 1000129003,
VK_STRUCTURE_TYPE_MEMORY_GET_ANDROID_HARDWARE_BUFFER_INFO_ANDROID = 1000129004,
VK_STRUCTURE_TYPE_EXTERNAL_FORMAT_ANDROID = 1000129005,
VK_STRUCTURE_TYPE_ANDROID_HARDWARE_BUFFER_FORMAT_PROPERTIES_2_ANDROID = 1000129006,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT = 1000138000,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT = 1000138001,
VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET_INLINE_UNIFORM_BLOCK_EXT = 1000138002,
@ -607,6 +608,7 @@ typedef enum VkStructureType {
VK_STRUCTURE_TYPE_IMAGE_DRM_FORMAT_MODIFIER_LIST_CREATE_INFO_EXT = 1000158003,
VK_STRUCTURE_TYPE_IMAGE_DRM_FORMAT_MODIFIER_EXPLICIT_CREATE_INFO_EXT = 1000158004,
VK_STRUCTURE_TYPE_IMAGE_DRM_FORMAT_MODIFIER_PROPERTIES_EXT = 1000158005,
VK_STRUCTURE_TYPE_DRM_FORMAT_MODIFIER_PROPERTIES_LIST_2_EXT = 1000158006,
VK_STRUCTURE_TYPE_VALIDATION_CACHE_CREATE_INFO_EXT = 1000160000,
VK_STRUCTURE_TYPE_SHADER_MODULE_VALIDATION_CACHE_CREATE_INFO_EXT = 1000160001,
#ifdef VK_ENABLE_BETA_EXTENSIONS
@ -754,6 +756,8 @@ typedef enum VkStructureType {
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEVICE_GENERATED_COMMANDS_FEATURES_NV = 1000277007,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INHERITED_VIEWPORT_SCISSOR_FEATURES_NV = 1000278000,
VK_STRUCTURE_TYPE_COMMAND_BUFFER_INHERITANCE_VIEWPORT_SCISSOR_INFO_NV = 1000278001,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_INTEGER_DOT_PRODUCT_FEATURES_KHR = 1000280000,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_INTEGER_DOT_PRODUCT_PROPERTIES_KHR = 1000280001,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT = 1000281000,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT = 1000281001,
VK_STRUCTURE_TYPE_COMMAND_BUFFER_INHERITANCE_RENDER_PASS_TRANSFORM_INFO_QCOM = 1000282000,
@ -817,6 +821,7 @@ typedef enum VkStructureType {
VK_STRUCTURE_TYPE_BUFFER_IMAGE_COPY_2_KHR = 1000337009,
VK_STRUCTURE_TYPE_IMAGE_RESOLVE_2_KHR = 1000337010,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_4444_FORMATS_FEATURES_EXT = 1000340000,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_RGBA10X6_FORMATS_FEATURES_EXT = 1000344000,
VK_STRUCTURE_TYPE_DIRECTFB_SURFACE_CREATE_INFO_EXT = 1000346000,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MUTABLE_DESCRIPTOR_TYPE_FEATURES_VALVE = 1000351000,
VK_STRUCTURE_TYPE_MUTABLE_DESCRIPTOR_TYPE_CREATE_INFO_VALVE = 1000351002,
@ -824,11 +829,23 @@ typedef enum VkStructureType {
VK_STRUCTURE_TYPE_VERTEX_INPUT_BINDING_DESCRIPTION_2_EXT = 1000352001,
VK_STRUCTURE_TYPE_VERTEX_INPUT_ATTRIBUTE_DESCRIPTION_2_EXT = 1000352002,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRM_PROPERTIES_EXT = 1000353000,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PRIMITIVE_TOPOLOGY_LIST_RESTART_FEATURES_EXT = 1000356000,
VK_STRUCTURE_TYPE_FORMAT_PROPERTIES_3_KHR = 1000360000,
VK_STRUCTURE_TYPE_IMPORT_MEMORY_ZIRCON_HANDLE_INFO_FUCHSIA = 1000364000,
VK_STRUCTURE_TYPE_MEMORY_ZIRCON_HANDLE_PROPERTIES_FUCHSIA = 1000364001,
VK_STRUCTURE_TYPE_MEMORY_GET_ZIRCON_HANDLE_INFO_FUCHSIA = 1000364002,
VK_STRUCTURE_TYPE_IMPORT_SEMAPHORE_ZIRCON_HANDLE_INFO_FUCHSIA = 1000365000,
VK_STRUCTURE_TYPE_SEMAPHORE_GET_ZIRCON_HANDLE_INFO_FUCHSIA = 1000365001,
VK_STRUCTURE_TYPE_BUFFER_COLLECTION_CREATE_INFO_FUCHSIA = 1000366000,
VK_STRUCTURE_TYPE_IMPORT_MEMORY_BUFFER_COLLECTION_FUCHSIA = 1000366001,
VK_STRUCTURE_TYPE_BUFFER_COLLECTION_IMAGE_CREATE_INFO_FUCHSIA = 1000366002,
VK_STRUCTURE_TYPE_BUFFER_COLLECTION_PROPERTIES_FUCHSIA = 1000366003,
VK_STRUCTURE_TYPE_BUFFER_CONSTRAINTS_INFO_FUCHSIA = 1000366004,
VK_STRUCTURE_TYPE_BUFFER_COLLECTION_BUFFER_CREATE_INFO_FUCHSIA = 1000366005,
VK_STRUCTURE_TYPE_IMAGE_CONSTRAINTS_INFO_FUCHSIA = 1000366006,
VK_STRUCTURE_TYPE_IMAGE_FORMAT_CONSTRAINTS_INFO_FUCHSIA = 1000366007,
VK_STRUCTURE_TYPE_SYSMEM_COLOR_SPACE_FUCHSIA = 1000366008,
VK_STRUCTURE_TYPE_BUFFER_COLLECTION_CONSTRAINTS_INFO_FUCHSIA = 1000366009,
VK_STRUCTURE_TYPE_SUBPASS_SHADING_PIPELINE_CREATE_INFO_HUAWEI = 1000369000,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBPASS_SHADING_FEATURES_HUAWEI = 1000369001,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBPASS_SHADING_PROPERTIES_HUAWEI = 1000369002,
@ -843,6 +860,11 @@ typedef enum VkStructureType {
VK_STRUCTURE_TYPE_QUEUE_FAMILY_GLOBAL_PRIORITY_PROPERTIES_EXT = 1000388001,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTI_DRAW_FEATURES_EXT = 1000392000,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTI_DRAW_PROPERTIES_EXT = 1000392001,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PAGEABLE_DEVICE_LOCAL_MEMORY_FEATURES_EXT = 1000412000,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_4_FEATURES_KHR = 1000413000,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_4_PROPERTIES_KHR = 1000413001,
VK_STRUCTURE_TYPE_DEVICE_BUFFER_MEMORY_REQUIREMENTS_KHR = 1000413002,
VK_STRUCTURE_TYPE_DEVICE_IMAGE_MEMORY_REQUIREMENTS_KHR = 1000413003,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES,
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES,
VK_STRUCTURE_TYPE_DEBUG_REPORT_CREATE_INFO_EXT = VK_STRUCTURE_TYPE_DEBUG_REPORT_CALLBACK_CREATE_INFO_EXT,
@ -1060,6 +1082,7 @@ typedef enum VkObjectType {
VK_OBJECT_TYPE_DEFERRED_OPERATION_KHR = 1000268000,
VK_OBJECT_TYPE_INDIRECT_COMMANDS_LAYOUT_NV = 1000277000,
VK_OBJECT_TYPE_PRIVATE_DATA_SLOT_EXT = 1000295000,
VK_OBJECT_TYPE_BUFFER_COLLECTION_FUCHSIA = 1000366000,
VK_OBJECT_TYPE_DESCRIPTOR_UPDATE_TEMPLATE_KHR = VK_OBJECT_TYPE_DESCRIPTOR_UPDATE_TEMPLATE,
VK_OBJECT_TYPE_SAMPLER_YCBCR_CONVERSION_KHR = VK_OBJECT_TYPE_SAMPLER_YCBCR_CONVERSION,
VK_OBJECT_TYPE_MAX_ENUM = 0x7FFFFFFF
@ -1706,13 +1729,15 @@ typedef enum VkAttachmentLoadOp {
VK_ATTACHMENT_LOAD_OP_LOAD = 0,
VK_ATTACHMENT_LOAD_OP_CLEAR = 1,
VK_ATTACHMENT_LOAD_OP_DONT_CARE = 2,
VK_ATTACHMENT_LOAD_OP_NONE_EXT = 1000400000,
VK_ATTACHMENT_LOAD_OP_MAX_ENUM = 0x7FFFFFFF
} VkAttachmentLoadOp;
typedef enum VkAttachmentStoreOp {
VK_ATTACHMENT_STORE_OP_STORE = 0,
VK_ATTACHMENT_STORE_OP_DONT_CARE = 1,
VK_ATTACHMENT_STORE_OP_NONE_QCOM = 1000301000,
VK_ATTACHMENT_STORE_OP_NONE_EXT = 1000301000,
VK_ATTACHMENT_STORE_OP_NONE_QCOM = VK_ATTACHMENT_STORE_OP_NONE_EXT,
VK_ATTACHMENT_STORE_OP_MAX_ENUM = 0x7FFFFFFF
} VkAttachmentStoreOp;
@ -2123,10 +2148,6 @@ typedef enum VkImageViewCreateFlagBits {
VK_IMAGE_VIEW_CREATE_FLAG_BITS_MAX_ENUM = 0x7FFFFFFF
} VkImageViewCreateFlagBits;
typedef VkFlags VkImageViewCreateFlags;
typedef enum VkShaderModuleCreateFlagBits {
VK_SHADER_MODULE_CREATE_FLAG_BITS_MAX_ENUM = 0x7FFFFFFF
} VkShaderModuleCreateFlagBits;
typedef VkFlags VkShaderModuleCreateFlags;
typedef enum VkPipelineCacheCreateFlagBits {
@ -5282,6 +5303,10 @@ typedef enum VkDriverId {
VK_DRIVER_ID_MOLTENVK = 14,
VK_DRIVER_ID_COREAVI_PROPRIETARY = 15,
VK_DRIVER_ID_JUICE_PROPRIETARY = 16,
VK_DRIVER_ID_VERISILICON_PROPRIETARY = 17,
VK_DRIVER_ID_MESA_TURNIP = 18,
VK_DRIVER_ID_MESA_V3DV = 19,
VK_DRIVER_ID_MESA_PANVK = 20,
VK_DRIVER_ID_AMD_PROPRIETARY_KHR = VK_DRIVER_ID_AMD_PROPRIETARY,
VK_DRIVER_ID_AMD_OPEN_SOURCE_KHR = VK_DRIVER_ID_AMD_OPEN_SOURCE,
VK_DRIVER_ID_MESA_RADV_KHR = VK_DRIVER_ID_MESA_RADV,
@ -6563,8 +6588,10 @@ VKAPI_ATTR void VKAPI_CALL vkCmdDispatchBaseKHR(
#define VK_KHR_maintenance1 1
#define VK_KHR_MAINTENANCE1_SPEC_VERSION 2
#define VK_KHR_MAINTENANCE1_EXTENSION_NAME "VK_KHR_maintenance1"
#define VK_KHR_MAINTENANCE_1_SPEC_VERSION 2
#define VK_KHR_MAINTENANCE_1_EXTENSION_NAME "VK_KHR_maintenance1"
#define VK_KHR_MAINTENANCE1_SPEC_VERSION VK_KHR_MAINTENANCE_1_SPEC_VERSION
#define VK_KHR_MAINTENANCE1_EXTENSION_NAME VK_KHR_MAINTENANCE_1_EXTENSION_NAME
typedef VkCommandPoolTrimFlags VkCommandPoolTrimFlagsKHR;
typedef void (VKAPI_PTR *PFN_vkTrimCommandPoolKHR)(VkDevice device, VkCommandPool commandPool, VkCommandPoolTrimFlags flags);
@ -7144,8 +7171,10 @@ VKAPI_ATTR void VKAPI_CALL vkReleaseProfilingLockKHR(
#define VK_KHR_maintenance2 1
#define VK_KHR_MAINTENANCE2_SPEC_VERSION 1
#define VK_KHR_MAINTENANCE2_EXTENSION_NAME "VK_KHR_maintenance2"
#define VK_KHR_MAINTENANCE_2_SPEC_VERSION 1
#define VK_KHR_MAINTENANCE_2_EXTENSION_NAME "VK_KHR_maintenance2"
#define VK_KHR_MAINTENANCE2_SPEC_VERSION VK_KHR_MAINTENANCE_2_SPEC_VERSION
#define VK_KHR_MAINTENANCE2_EXTENSION_NAME VK_KHR_MAINTENANCE_2_EXTENSION_NAME
typedef VkPointClippingBehavior VkPointClippingBehaviorKHR;
typedef VkTessellationDomainOrigin VkTessellationDomainOriginKHR;
@ -7398,8 +7427,10 @@ VKAPI_ATTR VkResult VKAPI_CALL vkBindImageMemory2KHR(
#define VK_KHR_maintenance3 1
#define VK_KHR_MAINTENANCE3_SPEC_VERSION 1
#define VK_KHR_MAINTENANCE3_EXTENSION_NAME "VK_KHR_maintenance3"
#define VK_KHR_MAINTENANCE_3_SPEC_VERSION 1
#define VK_KHR_MAINTENANCE_3_EXTENSION_NAME "VK_KHR_maintenance3"
#define VK_KHR_MAINTENANCE3_SPEC_VERSION VK_KHR_MAINTENANCE_3_SPEC_VERSION
#define VK_KHR_MAINTENANCE3_EXTENSION_NAME VK_KHR_MAINTENANCE_3_EXTENSION_NAME
typedef VkPhysicalDeviceMaintenance3Properties VkPhysicalDeviceMaintenance3PropertiesKHR;
typedef VkDescriptorSetLayoutSupport VkDescriptorSetLayoutSupportKHR;
@ -7575,7 +7606,7 @@ typedef struct VkPhysicalDeviceShaderTerminateInvocationFeaturesKHR {
#define VK_KHR_fragment_shading_rate 1
#define VK_KHR_FRAGMENT_SHADING_RATE_SPEC_VERSION 1
#define VK_KHR_FRAGMENT_SHADING_RATE_SPEC_VERSION 2
#define VK_KHR_FRAGMENT_SHADING_RATE_EXTENSION_NAME "VK_KHR_fragment_shading_rate"
typedef enum VkFragmentShadingRateCombinerOpKHR {
@ -7864,6 +7895,52 @@ VKAPI_ATTR VkResult VKAPI_CALL vkGetPipelineExecutableInternalRepresentationsKHR
#endif
#define VK_KHR_shader_integer_dot_product 1
#define VK_KHR_SHADER_INTEGER_DOT_PRODUCT_SPEC_VERSION 1
#define VK_KHR_SHADER_INTEGER_DOT_PRODUCT_EXTENSION_NAME "VK_KHR_shader_integer_dot_product"
typedef struct VkPhysicalDeviceShaderIntegerDotProductFeaturesKHR {
VkStructureType sType;
void* pNext;
VkBool32 shaderIntegerDotProduct;
} VkPhysicalDeviceShaderIntegerDotProductFeaturesKHR;
typedef struct VkPhysicalDeviceShaderIntegerDotProductPropertiesKHR {
VkStructureType sType;
void* pNext;
VkBool32 integerDotProduct8BitUnsignedAccelerated;
VkBool32 integerDotProduct8BitSignedAccelerated;
VkBool32 integerDotProduct8BitMixedSignednessAccelerated;
VkBool32 integerDotProduct4x8BitPackedUnsignedAccelerated;
VkBool32 integerDotProduct4x8BitPackedSignedAccelerated;
VkBool32 integerDotProduct4x8BitPackedMixedSignednessAccelerated;
VkBool32 integerDotProduct16BitUnsignedAccelerated;
VkBool32 integerDotProduct16BitSignedAccelerated;
VkBool32 integerDotProduct16BitMixedSignednessAccelerated;
VkBool32 integerDotProduct32BitUnsignedAccelerated;
VkBool32 integerDotProduct32BitSignedAccelerated;
VkBool32 integerDotProduct32BitMixedSignednessAccelerated;
VkBool32 integerDotProduct64BitUnsignedAccelerated;
VkBool32 integerDotProduct64BitSignedAccelerated;
VkBool32 integerDotProduct64BitMixedSignednessAccelerated;
VkBool32 integerDotProductAccumulatingSaturating8BitUnsignedAccelerated;
VkBool32 integerDotProductAccumulatingSaturating8BitSignedAccelerated;
VkBool32 integerDotProductAccumulatingSaturating8BitMixedSignednessAccelerated;
VkBool32 integerDotProductAccumulatingSaturating4x8BitPackedUnsignedAccelerated;
VkBool32 integerDotProductAccumulatingSaturating4x8BitPackedSignedAccelerated;
VkBool32 integerDotProductAccumulatingSaturating4x8BitPackedMixedSignednessAccelerated;
VkBool32 integerDotProductAccumulatingSaturating16BitUnsignedAccelerated;
VkBool32 integerDotProductAccumulatingSaturating16BitSignedAccelerated;
VkBool32 integerDotProductAccumulatingSaturating16BitMixedSignednessAccelerated;
VkBool32 integerDotProductAccumulatingSaturating32BitUnsignedAccelerated;
VkBool32 integerDotProductAccumulatingSaturating32BitSignedAccelerated;
VkBool32 integerDotProductAccumulatingSaturating32BitMixedSignednessAccelerated;
VkBool32 integerDotProductAccumulatingSaturating64BitUnsignedAccelerated;
VkBool32 integerDotProductAccumulatingSaturating64BitSignedAccelerated;
VkBool32 integerDotProductAccumulatingSaturating64BitMixedSignednessAccelerated;
} VkPhysicalDeviceShaderIntegerDotProductPropertiesKHR;
#define VK_KHR_pipeline_library 1
#define VK_KHR_PIPELINE_LIBRARY_SPEC_VERSION 1
#define VK_KHR_PIPELINE_LIBRARY_EXTENSION_NAME "VK_KHR_pipeline_library"
@ -8350,6 +8427,117 @@ VKAPI_ATTR void VKAPI_CALL vkCmdResolveImage2KHR(
#endif
#define VK_KHR_format_feature_flags2 1
#define VK_KHR_FORMAT_FEATURE_FLAGS_2_SPEC_VERSION 1
#define VK_KHR_FORMAT_FEATURE_FLAGS_2_EXTENSION_NAME "VK_KHR_format_feature_flags2"
typedef VkFlags64 VkFormatFeatureFlags2KHR;
// Flag bits for VkFormatFeatureFlagBits2KHR
typedef VkFlags64 VkFormatFeatureFlagBits2KHR;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_BIT_KHR = 0x00000001ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_STORAGE_IMAGE_BIT_KHR = 0x00000002ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_STORAGE_IMAGE_ATOMIC_BIT_KHR = 0x00000004ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_UNIFORM_TEXEL_BUFFER_BIT_KHR = 0x00000008ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_STORAGE_TEXEL_BUFFER_BIT_KHR = 0x00000010ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_STORAGE_TEXEL_BUFFER_ATOMIC_BIT_KHR = 0x00000020ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_VERTEX_BUFFER_BIT_KHR = 0x00000040ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_COLOR_ATTACHMENT_BIT_KHR = 0x00000080ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_COLOR_ATTACHMENT_BLEND_BIT_KHR = 0x00000100ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_DEPTH_STENCIL_ATTACHMENT_BIT_KHR = 0x00000200ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_BLIT_SRC_BIT_KHR = 0x00000400ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_BLIT_DST_BIT_KHR = 0x00000800ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_LINEAR_BIT_KHR = 0x00001000ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_CUBIC_BIT_EXT = 0x00002000ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_TRANSFER_SRC_BIT_KHR = 0x00004000ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_TRANSFER_DST_BIT_KHR = 0x00008000ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_MINMAX_BIT_KHR = 0x00010000ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_MIDPOINT_CHROMA_SAMPLES_BIT_KHR = 0x00020000ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_YCBCR_CONVERSION_LINEAR_FILTER_BIT_KHR = 0x00040000ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_YCBCR_CONVERSION_SEPARATE_RECONSTRUCTION_FILTER_BIT_KHR = 0x00080000ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_YCBCR_CONVERSION_CHROMA_RECONSTRUCTION_EXPLICIT_BIT_KHR = 0x00100000ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_YCBCR_CONVERSION_CHROMA_RECONSTRUCTION_EXPLICIT_FORCEABLE_BIT_KHR = 0x00200000ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_DISJOINT_BIT_KHR = 0x00400000ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_COSITED_CHROMA_SAMPLES_BIT_KHR = 0x00800000ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_STORAGE_READ_WITHOUT_FORMAT_BIT_KHR = 0x80000000ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_STORAGE_WRITE_WITHOUT_FORMAT_BIT_KHR = 0x100000000ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_DEPTH_COMPARISON_BIT_KHR = 0x200000000ULL;
#ifdef VK_ENABLE_BETA_EXTENSIONS
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_VIDEO_DECODE_OUTPUT_BIT_KHR = 0x02000000ULL;
#endif
#ifdef VK_ENABLE_BETA_EXTENSIONS
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_VIDEO_DECODE_DPB_BIT_KHR = 0x04000000ULL;
#endif
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_ACCELERATION_STRUCTURE_VERTEX_BUFFER_BIT_KHR = 0x20000000ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_FRAGMENT_DENSITY_MAP_BIT_EXT = 0x01000000ULL;
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR = 0x40000000ULL;
#ifdef VK_ENABLE_BETA_EXTENSIONS
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_VIDEO_ENCODE_INPUT_BIT_KHR = 0x08000000ULL;
#endif
#ifdef VK_ENABLE_BETA_EXTENSIONS
static const VkFormatFeatureFlagBits2KHR VK_FORMAT_FEATURE_2_VIDEO_ENCODE_DPB_BIT_KHR = 0x10000000ULL;
#endif
typedef struct VkFormatProperties3KHR {
VkStructureType sType;
void* pNext;
VkFormatFeatureFlags2KHR linearTilingFeatures;
VkFormatFeatureFlags2KHR optimalTilingFeatures;
VkFormatFeatureFlags2KHR bufferFeatures;
} VkFormatProperties3KHR;
#define VK_KHR_maintenance4 1
#define VK_KHR_MAINTENANCE_4_SPEC_VERSION 1
#define VK_KHR_MAINTENANCE_4_EXTENSION_NAME "VK_KHR_maintenance4"
typedef struct VkPhysicalDeviceMaintenance4FeaturesKHR {
VkStructureType sType;
void* pNext;
VkBool32 maintenance4;
} VkPhysicalDeviceMaintenance4FeaturesKHR;
typedef struct VkPhysicalDeviceMaintenance4PropertiesKHR {
VkStructureType sType;
void* pNext;
VkDeviceSize maxBufferSize;
} VkPhysicalDeviceMaintenance4PropertiesKHR;
typedef struct VkDeviceBufferMemoryRequirementsKHR {
VkStructureType sType;
const void* pNext;
const VkBufferCreateInfo* pCreateInfo;
} VkDeviceBufferMemoryRequirementsKHR;
typedef struct VkDeviceImageMemoryRequirementsKHR {
VkStructureType sType;
const void* pNext;
const VkImageCreateInfo* pCreateInfo;
VkImageAspectFlagBits planeAspect;
} VkDeviceImageMemoryRequirementsKHR;
typedef void (VKAPI_PTR *PFN_vkGetDeviceBufferMemoryRequirementsKHR)(VkDevice device, const VkDeviceBufferMemoryRequirementsKHR* pInfo, VkMemoryRequirements2* pMemoryRequirements);
typedef void (VKAPI_PTR *PFN_vkGetDeviceImageMemoryRequirementsKHR)(VkDevice device, const VkDeviceImageMemoryRequirementsKHR* pInfo, VkMemoryRequirements2* pMemoryRequirements);
typedef void (VKAPI_PTR *PFN_vkGetDeviceImageSparseMemoryRequirementsKHR)(VkDevice device, const VkDeviceImageMemoryRequirementsKHR* pInfo, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements2* pSparseMemoryRequirements);
#ifndef VK_NO_PROTOTYPES
VKAPI_ATTR void VKAPI_CALL vkGetDeviceBufferMemoryRequirementsKHR(
VkDevice device,
const VkDeviceBufferMemoryRequirementsKHR* pInfo,
VkMemoryRequirements2* pMemoryRequirements);
VKAPI_ATTR void VKAPI_CALL vkGetDeviceImageMemoryRequirementsKHR(
VkDevice device,
const VkDeviceImageMemoryRequirementsKHR* pInfo,
VkMemoryRequirements2* pMemoryRequirements);
VKAPI_ATTR void VKAPI_CALL vkGetDeviceImageSparseMemoryRequirementsKHR(
VkDevice device,
const VkDeviceImageMemoryRequirementsKHR* pInfo,
uint32_t* pSparseMemoryRequirementCount,
VkSparseImageMemoryRequirements2* pSparseMemoryRequirements);
#endif
#define VK_EXT_debug_report 1
VK_DEFINE_NON_DISPATCHABLE_HANDLE(VkDebugReportCallbackEXT)
#define VK_EXT_DEBUG_REPORT_SPEC_VERSION 10
@ -8394,6 +8582,7 @@ typedef enum VkDebugReportObjectTypeEXT {
VK_DEBUG_REPORT_OBJECT_TYPE_CU_FUNCTION_NVX_EXT = 1000029001,
VK_DEBUG_REPORT_OBJECT_TYPE_ACCELERATION_STRUCTURE_KHR_EXT = 1000150000,
VK_DEBUG_REPORT_OBJECT_TYPE_ACCELERATION_STRUCTURE_NV_EXT = 1000165000,
VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_COLLECTION_FUCHSIA_EXT = 1000366000,
VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_EXT = VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT_EXT,
VK_DEBUG_REPORT_OBJECT_TYPE_VALIDATION_CACHE_EXT = VK_DEBUG_REPORT_OBJECT_TYPE_VALIDATION_CACHE_EXT_EXT,
VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_UPDATE_TEMPLATE_KHR_EXT = VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_UPDATE_TEMPLATE_EXT,
@ -9253,8 +9442,10 @@ VKAPI_ATTR VkResult VKAPI_CALL vkGetPastPresentationTimingGOOGLE(
#define VK_NV_viewport_array2 1
#define VK_NV_VIEWPORT_ARRAY2_SPEC_VERSION 1
#define VK_NV_VIEWPORT_ARRAY2_EXTENSION_NAME "VK_NV_viewport_array2"
#define VK_NV_VIEWPORT_ARRAY_2_SPEC_VERSION 1
#define VK_NV_VIEWPORT_ARRAY_2_EXTENSION_NAME "VK_NV_viewport_array2"
#define VK_NV_VIEWPORT_ARRAY2_SPEC_VERSION VK_NV_VIEWPORT_ARRAY_2_SPEC_VERSION
#define VK_NV_VIEWPORT_ARRAY2_EXTENSION_NAME VK_NV_VIEWPORT_ARRAY_2_EXTENSION_NAME
#define VK_NVX_multiview_per_view_attributes 1
@ -9824,7 +10015,7 @@ typedef struct VkPhysicalDeviceShaderSMBuiltinsFeaturesNV {
#define VK_EXT_image_drm_format_modifier 1
#define VK_EXT_IMAGE_DRM_FORMAT_MODIFIER_SPEC_VERSION 1
#define VK_EXT_IMAGE_DRM_FORMAT_MODIFIER_SPEC_VERSION 2
#define VK_EXT_IMAGE_DRM_FORMAT_MODIFIER_EXTENSION_NAME "VK_EXT_image_drm_format_modifier"
typedef struct VkDrmFormatModifierPropertiesEXT {
uint64_t drmFormatModifier;
@ -9869,6 +10060,19 @@ typedef struct VkImageDrmFormatModifierPropertiesEXT {
uint64_t drmFormatModifier;
} VkImageDrmFormatModifierPropertiesEXT;
typedef struct VkDrmFormatModifierProperties2EXT {
uint64_t drmFormatModifier;
uint32_t drmFormatModifierPlaneCount;
VkFormatFeatureFlags2KHR drmFormatModifierTilingFeatures;
} VkDrmFormatModifierProperties2EXT;
typedef struct VkDrmFormatModifierPropertiesList2EXT {
VkStructureType sType;
void* pNext;
uint32_t drmFormatModifierCount;
VkDrmFormatModifierProperties2EXT* pDrmFormatModifierProperties;
} VkDrmFormatModifierPropertiesList2EXT;
typedef VkResult (VKAPI_PTR *PFN_vkGetImageDrmFormatModifierPropertiesEXT)(VkDevice device, VkImage image, VkImageDrmFormatModifierPropertiesEXT* pProperties);
#ifndef VK_NO_PROTOTYPES
@ -10133,9 +10337,10 @@ typedef VkGeometryFlagBitsKHR VkGeometryFlagBitsNV;
typedef enum VkGeometryInstanceFlagBitsKHR {
VK_GEOMETRY_INSTANCE_TRIANGLE_FACING_CULL_DISABLE_BIT_KHR = 0x00000001,
VK_GEOMETRY_INSTANCE_TRIANGLE_FRONT_COUNTERCLOCKWISE_BIT_KHR = 0x00000002,
VK_GEOMETRY_INSTANCE_TRIANGLE_FLIP_FACING_BIT_KHR = 0x00000002,
VK_GEOMETRY_INSTANCE_FORCE_OPAQUE_BIT_KHR = 0x00000004,
VK_GEOMETRY_INSTANCE_FORCE_NO_OPAQUE_BIT_KHR = 0x00000008,
VK_GEOMETRY_INSTANCE_TRIANGLE_FRONT_COUNTERCLOCKWISE_BIT_KHR = VK_GEOMETRY_INSTANCE_TRIANGLE_FLIP_FACING_BIT_KHR,
VK_GEOMETRY_INSTANCE_TRIANGLE_CULL_DISABLE_BIT_NV = VK_GEOMETRY_INSTANCE_TRIANGLE_FACING_CULL_DISABLE_BIT_KHR,
VK_GEOMETRY_INSTANCE_TRIANGLE_FRONT_COUNTERCLOCKWISE_BIT_NV = VK_GEOMETRY_INSTANCE_TRIANGLE_FRONT_COUNTERCLOCKWISE_BIT_KHR,
VK_GEOMETRY_INSTANCE_FORCE_OPAQUE_BIT_NV = VK_GEOMETRY_INSTANCE_FORCE_OPAQUE_BIT_KHR,
@ -11029,7 +11234,7 @@ VKAPI_ATTR void VKAPI_CALL vkSetLocalDimmingAMD(
#define VK_EXT_fragment_density_map 1
#define VK_EXT_FRAGMENT_DENSITY_MAP_SPEC_VERSION 1
#define VK_EXT_FRAGMENT_DENSITY_MAP_SPEC_VERSION 2
#define VK_EXT_FRAGMENT_DENSITY_MAP_EXTENSION_NAME "VK_EXT_fragment_density_map"
typedef struct VkPhysicalDeviceFragmentDensityMapFeaturesEXT {
VkStructureType sType;
@ -11063,8 +11268,10 @@ typedef VkPhysicalDeviceScalarBlockLayoutFeatures VkPhysicalDeviceScalarBlockLay
#define VK_GOOGLE_hlsl_functionality1 1
#define VK_GOOGLE_HLSL_FUNCTIONALITY1_SPEC_VERSION 1
#define VK_GOOGLE_HLSL_FUNCTIONALITY1_EXTENSION_NAME "VK_GOOGLE_hlsl_functionality1"
#define VK_GOOGLE_HLSL_FUNCTIONALITY_1_SPEC_VERSION 1
#define VK_GOOGLE_HLSL_FUNCTIONALITY_1_EXTENSION_NAME "VK_GOOGLE_hlsl_functionality1"
#define VK_GOOGLE_HLSL_FUNCTIONALITY1_SPEC_VERSION VK_GOOGLE_HLSL_FUNCTIONALITY_1_SPEC_VERSION
#define VK_GOOGLE_HLSL_FUNCTIONALITY1_EXTENSION_NAME VK_GOOGLE_HLSL_FUNCTIONALITY_1_EXTENSION_NAME
#define VK_GOOGLE_decorate_string 1
@ -12354,6 +12561,17 @@ typedef struct VkPhysicalDevice4444FormatsFeaturesEXT {
#define VK_EXT_rgba10x6_formats 1
#define VK_EXT_RGBA10X6_FORMATS_SPEC_VERSION 1
#define VK_EXT_RGBA10X6_FORMATS_EXTENSION_NAME "VK_EXT_rgba10x6_formats"
typedef struct VkPhysicalDeviceRGBA10X6FormatsFeaturesEXT {
VkStructureType sType;
void* pNext;
VkBool32 formatRgba10x6WithoutYCbCrSampler;
} VkPhysicalDeviceRGBA10X6FormatsFeaturesEXT;
#define VK_NV_acquire_winrt_display 1
#define VK_NV_ACQUIRE_WINRT_DISPLAY_SPEC_VERSION 1
#define VK_NV_ACQUIRE_WINRT_DISPLAY_EXTENSION_NAME "VK_NV_acquire_winrt_display"
@ -12450,6 +12668,18 @@ typedef struct VkPhysicalDeviceDrmPropertiesEXT {
#define VK_EXT_primitive_topology_list_restart 1
#define VK_EXT_PRIMITIVE_TOPOLOGY_LIST_RESTART_SPEC_VERSION 1
#define VK_EXT_PRIMITIVE_TOPOLOGY_LIST_RESTART_EXTENSION_NAME "VK_EXT_primitive_topology_list_restart"
typedef struct VkPhysicalDevicePrimitiveTopologyListRestartFeaturesEXT {
VkStructureType sType;
void* pNext;
VkBool32 primitiveTopologyListRestart;
VkBool32 primitiveTopologyPatchListRestart;
} VkPhysicalDevicePrimitiveTopologyListRestartFeaturesEXT;
#define VK_HUAWEI_subpass_shading 1
#define VK_HUAWEI_SUBPASS_SHADING_SPEC_VERSION 2
#define VK_HUAWEI_SUBPASS_SHADING_EXTENSION_NAME "VK_HUAWEI_subpass_shading"
@ -12666,9 +12896,33 @@ VKAPI_ATTR void VKAPI_CALL vkCmdDrawMultiIndexedEXT(
#endif
#define VK_EXT_load_store_op_none 1
#define VK_EXT_LOAD_STORE_OP_NONE_SPEC_VERSION 1
#define VK_EXT_LOAD_STORE_OP_NONE_EXTENSION_NAME "VK_EXT_load_store_op_none"
#define VK_EXT_pageable_device_local_memory 1
#define VK_EXT_PAGEABLE_DEVICE_LOCAL_MEMORY_SPEC_VERSION 1
#define VK_EXT_PAGEABLE_DEVICE_LOCAL_MEMORY_EXTENSION_NAME "VK_EXT_pageable_device_local_memory"
typedef struct VkPhysicalDevicePageableDeviceLocalMemoryFeaturesEXT {
VkStructureType sType;
void* pNext;
VkBool32 pageableDeviceLocalMemory;
} VkPhysicalDevicePageableDeviceLocalMemoryFeaturesEXT;
typedef void (VKAPI_PTR *PFN_vkSetDeviceMemoryPriorityEXT)(VkDevice device, VkDeviceMemory memory, float priority);
#ifndef VK_NO_PROTOTYPES
VKAPI_ATTR void VKAPI_CALL vkSetDeviceMemoryPriorityEXT(
VkDevice device,
VkDeviceMemory memory,
float priority);
#endif
#define VK_KHR_acceleration_structure 1
VK_DEFINE_NON_DISPATCHABLE_HANDLE(VkAccelerationStructureKHR)
#define VK_KHR_ACCELERATION_STRUCTURE_SPEC_VERSION 11
#define VK_KHR_ACCELERATION_STRUCTURE_SPEC_VERSION 13
#define VK_KHR_ACCELERATION_STRUCTURE_EXTENSION_NAME "VK_KHR_acceleration_structure"
typedef enum VkBuildAccelerationStructureModeKHR {

141
mesa 3D driver/include/vulkan/vulkan_fuchsia.h
View File

@ -114,6 +114,147 @@ VKAPI_ATTR VkResult VKAPI_CALL vkGetSemaphoreZirconHandleFUCHSIA(
zx_handle_t* pZirconHandle);
#endif
#define VK_FUCHSIA_buffer_collection 1
VK_DEFINE_NON_DISPATCHABLE_HANDLE(VkBufferCollectionFUCHSIA)
#define VK_FUCHSIA_BUFFER_COLLECTION_SPEC_VERSION 2
#define VK_FUCHSIA_BUFFER_COLLECTION_EXTENSION_NAME "VK_FUCHSIA_buffer_collection"
typedef enum VkImageFormatConstraintsFlagBitsFUCHSIA {
VK_IMAGE_FORMAT_CONSTRAINTS_FLAG_BITS_MAX_ENUM_FUCHSIA = 0x7FFFFFFF
} VkImageFormatConstraintsFlagBitsFUCHSIA;
typedef VkFlags VkImageFormatConstraintsFlagsFUCHSIA;
typedef enum VkImageConstraintsInfoFlagBitsFUCHSIA {
VK_IMAGE_CONSTRAINTS_INFO_CPU_READ_RARELY_FUCHSIA = 0x00000001,
VK_IMAGE_CONSTRAINTS_INFO_CPU_READ_OFTEN_FUCHSIA = 0x00000002,
VK_IMAGE_CONSTRAINTS_INFO_CPU_WRITE_RARELY_FUCHSIA = 0x00000004,
VK_IMAGE_CONSTRAINTS_INFO_CPU_WRITE_OFTEN_FUCHSIA = 0x00000008,
VK_IMAGE_CONSTRAINTS_INFO_PROTECTED_OPTIONAL_FUCHSIA = 0x00000010,
VK_IMAGE_CONSTRAINTS_INFO_FLAG_BITS_MAX_ENUM_FUCHSIA = 0x7FFFFFFF
} VkImageConstraintsInfoFlagBitsFUCHSIA;
typedef VkFlags VkImageConstraintsInfoFlagsFUCHSIA;
typedef struct VkBufferCollectionCreateInfoFUCHSIA {
VkStructureType sType;
const void* pNext;
zx_handle_t collectionToken;
} VkBufferCollectionCreateInfoFUCHSIA;
typedef struct VkImportMemoryBufferCollectionFUCHSIA {
VkStructureType sType;
const void* pNext;
VkBufferCollectionFUCHSIA collection;
uint32_t index;
} VkImportMemoryBufferCollectionFUCHSIA;
typedef struct VkBufferCollectionImageCreateInfoFUCHSIA {
VkStructureType sType;
const void* pNext;
VkBufferCollectionFUCHSIA collection;
uint32_t index;
} VkBufferCollectionImageCreateInfoFUCHSIA;
typedef struct VkBufferCollectionConstraintsInfoFUCHSIA {
VkStructureType sType;
const void* pNext;
uint32_t minBufferCount;
uint32_t maxBufferCount;
uint32_t minBufferCountForCamping;
uint32_t minBufferCountForDedicatedSlack;
uint32_t minBufferCountForSharedSlack;
} VkBufferCollectionConstraintsInfoFUCHSIA;
typedef struct VkBufferConstraintsInfoFUCHSIA {
VkStructureType sType;
const void* pNext;
VkBufferCreateInfo createInfo;
VkFormatFeatureFlags requiredFormatFeatures;
VkBufferCollectionConstraintsInfoFUCHSIA bufferCollectionConstraints;
} VkBufferConstraintsInfoFUCHSIA;
typedef struct VkBufferCollectionBufferCreateInfoFUCHSIA {
VkStructureType sType;
const void* pNext;
VkBufferCollectionFUCHSIA collection;
uint32_t index;
} VkBufferCollectionBufferCreateInfoFUCHSIA;
typedef struct VkSysmemColorSpaceFUCHSIA {
VkStructureType sType;
const void* pNext;
uint32_t colorSpace;
} VkSysmemColorSpaceFUCHSIA;
typedef struct VkBufferCollectionPropertiesFUCHSIA {
VkStructureType sType;
void* pNext;
uint32_t memoryTypeBits;
uint32_t bufferCount;
uint32_t createInfoIndex;
uint64_t sysmemPixelFormat;
VkFormatFeatureFlags formatFeatures;
VkSysmemColorSpaceFUCHSIA sysmemColorSpaceIndex;
VkComponentMapping samplerYcbcrConversionComponents;
VkSamplerYcbcrModelConversion suggestedYcbcrModel;
VkSamplerYcbcrRange suggestedYcbcrRange;
VkChromaLocation suggestedXChromaOffset;
VkChromaLocation suggestedYChromaOffset;
} VkBufferCollectionPropertiesFUCHSIA;
typedef struct VkImageFormatConstraintsInfoFUCHSIA {
VkStructureType sType;
const void* pNext;
VkImageCreateInfo imageCreateInfo;
VkFormatFeatureFlags requiredFormatFeatures;
VkImageFormatConstraintsFlagsFUCHSIA flags;
uint64_t sysmemPixelFormat;
uint32_t colorSpaceCount;
const VkSysmemColorSpaceFUCHSIA* pColorSpaces;
} VkImageFormatConstraintsInfoFUCHSIA;
typedef struct VkImageConstraintsInfoFUCHSIA {
VkStructureType sType;
const void* pNext;
uint32_t formatConstraintsCount;
const VkImageFormatConstraintsInfoFUCHSIA* pFormatConstraints;
VkBufferCollectionConstraintsInfoFUCHSIA bufferCollectionConstraints;
VkImageConstraintsInfoFlagsFUCHSIA flags;
} VkImageConstraintsInfoFUCHSIA;
typedef VkResult (VKAPI_PTR *PFN_vkCreateBufferCollectionFUCHSIA)(VkDevice device, const VkBufferCollectionCreateInfoFUCHSIA* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBufferCollectionFUCHSIA* pCollection);
typedef VkResult (VKAPI_PTR *PFN_vkSetBufferCollectionImageConstraintsFUCHSIA)(VkDevice device, VkBufferCollectionFUCHSIA collection, const VkImageConstraintsInfoFUCHSIA* pImageConstraintsInfo);
typedef VkResult (VKAPI_PTR *PFN_vkSetBufferCollectionBufferConstraintsFUCHSIA)(VkDevice device, VkBufferCollectionFUCHSIA collection, const VkBufferConstraintsInfoFUCHSIA* pBufferConstraintsInfo);
typedef void (VKAPI_PTR *PFN_vkDestroyBufferCollectionFUCHSIA)(VkDevice device, VkBufferCollectionFUCHSIA collection, const VkAllocationCallbacks* pAllocator);
typedef VkResult (VKAPI_PTR *PFN_vkGetBufferCollectionPropertiesFUCHSIA)(VkDevice device, VkBufferCollectionFUCHSIA collection, VkBufferCollectionPropertiesFUCHSIA* pProperties);
#ifndef VK_NO_PROTOTYPES
VKAPI_ATTR VkResult VKAPI_CALL vkCreateBufferCollectionFUCHSIA(
VkDevice device,
const VkBufferCollectionCreateInfoFUCHSIA* pCreateInfo,
const VkAllocationCallbacks* pAllocator,
VkBufferCollectionFUCHSIA* pCollection);
VKAPI_ATTR VkResult VKAPI_CALL vkSetBufferCollectionImageConstraintsFUCHSIA(
VkDevice device,
VkBufferCollectionFUCHSIA collection,
const VkImageConstraintsInfoFUCHSIA* pImageConstraintsInfo);
VKAPI_ATTR VkResult VKAPI_CALL vkSetBufferCollectionBufferConstraintsFUCHSIA(
VkDevice device,
VkBufferCollectionFUCHSIA collection,
const VkBufferConstraintsInfoFUCHSIA* pBufferConstraintsInfo);
VKAPI_ATTR void VKAPI_CALL vkDestroyBufferCollectionFUCHSIA(
VkDevice device,
VkBufferCollectionFUCHSIA collection,
const VkAllocationCallbacks* pAllocator);
VKAPI_ATTR VkResult VKAPI_CALL vkGetBufferCollectionPropertiesFUCHSIA(
VkDevice device,
VkBufferCollectionFUCHSIA collection,
VkBufferCollectionPropertiesFUCHSIA* pProperties);
#endif
#ifdef __cplusplus
}
#endif

142
mesa 3D driver/meson.build
View File

@ -30,6 +30,13 @@ project(
default_options : ['buildtype=debugoptimized', 'b_ndebug=if-release', 'c_std=c11', 'cpp_std=c++14']
)
# For meson >= 0.55.0, meson can inject some extra arguments to get richer
# results from gtest based tests.
gtest_test_protocol = 'exitcode'
if meson.version().version_compare('>= 0.55.0')
gtest_test_protocol = 'gtest'
endif
cc = meson.get_compiler('c')
cpp = meson.get_compiler('cpp')
@ -78,7 +85,6 @@ if with_tools.contains('all')
'asahi',
]
endif
with_clc = false
with_any_vulkan_layers = get_option('vulkan-layers').length() != 0
with_intel_tools = with_tools.contains('intel') or with_tools.contains('intel-ui')
@ -205,7 +211,7 @@ if gallium_drivers.contains('auto')
if ['x86', 'x86_64'].contains(host_machine.cpu_family())
gallium_drivers = [
'r300', 'r600', 'radeonsi', 'nouveau', 'virgl', 'svga', 'swrast',
'iris'
'iris', 'crocus'
]
elif ['arm', 'aarch64'].contains(host_machine.cpu_family())
gallium_drivers = [
@ -308,19 +314,9 @@ if with_aco_tests and not with_amd_vk
error('ACO tests require Radv')
endif
dep_clang = dependency(
'clang',
method : 'cmake',
static : true,
modules : [
'clangBasic', 'clangCodeGen', 'clangDriver', 'clangFrontend', 'clangFrontendTool',
'clangHandleCXX', 'clangHandleLLVM',
],
required : get_option('microsoft-clc'),
)
with_microsoft_clc = dep_clang.found()
with_clc = dep_clang.found()
with_microsoft_clc = get_option('microsoft-clc').enabled()
with_clc = with_microsoft_clc
with_libclc = with_clc
with_spirv_to_dxil = get_option('spirv-to-dxil')
if host_machine.system() == 'darwin'
@ -425,6 +421,35 @@ else
with_xlib_lease = _xlib_lease == 'enabled'
endif
if with_platform_wayland
c_args += '-DVK_USE_PLATFORM_WAYLAND_KHR'
#add this once aco and other places can build with it
#cpp_args += '-DVK_USE_PLATFORM_WAYLAND_KHR'
endif
if with_platform_x11
c_args += ['-DVK_USE_PLATFORM_XCB_KHR', '-DVK_USE_PLATFORM_XLIB_KHR']
#add this once aco and other places can build with it
#cpp_args += ['-DVK_USE_PLATFORM_XCB_KHR', '-DVK_USE_PLATFORM_XLIB_KHR']
endif
if with_platform_windows
c_args += '-DVK_USE_PLATFORM_WIN32_KHR'
#add this once aco and other places can build with it
#cpp_args += '-DVK_USE_PLATFORM_WIN32_KHR'
endif
if with_platform_android
c_args += '-DVK_USE_PLATFORM_ANDROID_KHR'
cpp_args += '-DVK_USE_PLATFORM_ANDROID_KHR'
endif
if with_xlib_lease
c_args += '-DVK_USE_PLATFORM_XLIB_XRANDR_EXT'
#add this once aco and other places can build with it
#cpp_args += '-DVK_USE_PLATFORM_XLIB_XRANDR_EXT'
endif
if system_has_kms_drm and not with_platform_android
c_args += '-DVK_USE_PLATFORM_DISPLAY_KHR'
cpp_args += '-DVK_USE_PLATFORM_DISPLAY_KHR'
endif
_egl = get_option('egl')
if _egl == 'true'
_egl = 'enabled'
@ -435,18 +460,19 @@ elif _egl == 'false'
endif
if _egl == 'auto'
with_egl = (
not ['darwin', 'windows'].contains(host_machine.system()) and
with_dri and with_shared_glapi
host_machine.system() != 'darwin' and
(with_platform_windows or with_dri) and
with_shared_glapi
)
elif _egl == 'enabled'
if not with_dri and not with_platform_haiku
error('EGL requires dri')
if not with_dri and not with_platform_haiku and not with_platform_windows
error('EGL requires dri, haiku, or windows')
elif not with_shared_glapi
error('EGL requires shared-glapi')
elif not ['disabled', 'dri'].contains(with_glx)
error('EGL requires dri, but a GLX is being built without dri')
elif ['darwin', 'windows'].contains(host_machine.system())
error('EGL is not available on Windows or MacOS')
elif host_machine.system() == 'darwin'
error('EGL is not available on MacOS')
endif
with_egl = true
else
@ -615,7 +641,7 @@ dep_dxheaders = null_dep
if with_gallium_d3d12 or with_microsoft_clc
dep_dxheaders = dependency('DirectX-Headers', fallback : ['DirectX-Headers', 'dep_dxheaders'],
required : with_gallium_d3d12
)
)
endif
if with_vulkan_overlay_layer or with_aco_tests
@ -818,7 +844,7 @@ if with_gallium_st_nine
error('The nine state tracker requires gallium softpipe/llvmpipe.')
elif not (with_gallium_radeonsi or with_gallium_nouveau or with_gallium_r600
or with_gallium_r300 or with_gallium_svga or with_gallium_i915
or with_gallium_iris or with_gallium_crocus)
or with_gallium_iris or with_gallium_crocus or with_gallium_zink)
error('The nine state tracker requires at least one non-swrast gallium driver.')
endif
if not with_dri3
@ -866,13 +892,20 @@ if _power8 != 'disabled'
endif
endif
if get_option('vmware-mks-stats')
if not with_gallium_svga
error('vmware-mks-stats requires gallium VMware/svga driver.')
endif
pre_args += '-DVMX86_STATS=1'
endif
_opencl = get_option('gallium-opencl')
if _opencl != 'disabled'
if not with_gallium
error('OpenCL Clover implementation requires at least one gallium driver.')
endif
with_clc = true
with_libclc = true
with_gallium_opencl = true
with_opencl_icd = _opencl == 'icd'
else
@ -881,7 +914,7 @@ else
endif
dep_clc = null_dep
if with_clc
if with_libclc
dep_clc = dependency('libclc')
endif
@ -913,6 +946,9 @@ endif
if with_gbm and not with_platform_android
pre_args += '-DHAVE_DRM_PLATFORM'
endif
if with_platform_windows
pre_args += '-DHAVE_WINDOWS_PLATFORM'
endif
with_android_stub = get_option('android-stub')
if with_android_stub and not with_platform_android
@ -1077,6 +1113,7 @@ if cc.get_id() == 'msvc'
'/wd5105', # macro expansion producing 'defined' has undefined behavior (winbase.h, need Windows SDK upgrade)
'/we4020', # Error when passing the wrong number of parameters
'/we4024', # Error when passing different type of parameter
'/Zc:__cplusplus', #Set __cplusplus macro to match the /std:c++<version> on the command line
]
if cc.has_argument(a)
c_args += a
@ -1094,7 +1131,6 @@ else
'-Werror=incompatible-pointer-types',
'-Werror=int-conversion',
'-Wimplicit-fallthrough',
'-Werror=thread-safety',
'-Wno-missing-field-initializers',
'-Wno-format-truncation',
'-fno-math-errno',
@ -1106,6 +1142,10 @@ else
if not (cc.get_id() == 'gcc' and host_machine.system() == 'windows')
_trial += ['-Werror=format', '-Wformat-security']
endif
# FreeBSD annotated <pthread.h> but Mesa isn't ready
if not (cc.get_id() == 'clang' and host_machine.system() == 'freebsd')
_trial += ['-Werror=thread-safety']
endif
foreach a : _trial
if cc.has_argument(a)
c_args += a
@ -1333,7 +1373,7 @@ if not ['linux'].contains(host_machine.system())
endif
endif
foreach h : ['xlocale.h', 'linux/futex.h', 'endian.h', 'dlfcn.h', 'execinfo.h', 'sys/shm.h', 'cet.h', 'pthread_np.h']
foreach h : ['xlocale.h', 'linux/futex.h', 'endian.h', 'dlfcn.h', 'sys/shm.h', 'cet.h', 'pthread_np.h']
if cc.check_header(h)
pre_args += '-DHAVE_@0@'.format(h.to_upper().underscorify())
endif
@ -1595,8 +1635,8 @@ if with_gallium_opencl
]
llvm_optional_modules += ['frontendopenmp']
endif
if with_microsoft_clc
llvm_modules += ['target', 'linker', 'irreader', 'option', 'libdriver']
if with_clc
llvm_modules += ['coverage', 'target', 'linker', 'irreader', 'option', 'libdriver', 'lto']
endif
if with_tests or with_gallium_softpipe
llvm_modules += 'native'
@ -1604,7 +1644,7 @@ endif
if with_amd_vk or with_gallium_radeonsi
_llvm_version = '>= 11.0.0'
elif with_microsoft_clc
elif with_clc
_llvm_version = '>= 10.0.0'
elif with_gallium_opencl
_llvm_version = '>= 8.0.0'
@ -1657,7 +1697,7 @@ if _llvm != 'disabled'
optional_modules : llvm_optional_modules,
required : (
with_amd_vk or with_gallium_radeonsi or with_gallium_swr or
with_gallium_opencl or with_microsoft_clc or _llvm == 'enabled'
with_gallium_opencl or with_clc or _llvm == 'enabled'
),
static : not _shared_llvm,
method : _llvm_method,
@ -1710,17 +1750,19 @@ if with_llvm
language : ['c', 'cpp'],
)
endif
elif with_amd_vk or with_gallium_radeonsi or with_gallium_swr or with_swrast_vk
error('The following drivers require LLVM: Radv, RadeonSI, SWR, Lavapipe. One of these is enabled, but LLVM is disabled.')
elif with_amd_vk and with_aco_tests
error('ACO tests require LLVM, but LLVM is disabled.')
elif with_gallium_radeonsi or with_gallium_swr or with_swrast_vk
error('The following drivers require LLVM: RadeonSI, SWR, Lavapipe. One of these is enabled, but LLVM is disabled.')
elif with_gallium_opencl
error('The OpenCL "Clover" state tracker requires LLVM, but LLVM is disabled.')
elif with_microsoft_clc
error('The Microsoft CLC compiler requires LLVM, but LLVM is disabled.')
elif with_clc
error('The CLC compiler requires LLVM, but LLVM is disabled.')
else
draw_with_llvm = false
endif
with_opencl_spirv = (_opencl != 'disabled' and get_option('opencl-spirv')) or with_microsoft_clc
with_opencl_spirv = (_opencl != 'disabled' and get_option('opencl-spirv')) or with_clc
if with_opencl_spirv
chosen_llvm_version_array = dep_llvm.version().split('.')
chosen_llvm_version_major = chosen_llvm_version_array[0].to_int()
@ -1745,6 +1787,30 @@ else
dep_llvmspirvlib = null_dep
endif
dep_clang = null_dep
if with_clc
llvm_libdir = dep_llvm.get_variable(cmake : 'LLVM_LIBRARY_DIR', configtool: 'libdir')
clang_modules = [
'clangBasic', 'clangAST', 'clangCodeGen', 'clangLex',
'clangDriver', 'clangFrontend', 'clangFrontendTool',
'clangHandleCXX', 'clangHandleLLVM', 'clangSerialization',
'clangSema', 'clangParse', 'clangEdit', 'clangAnalysis'
]
dep_clang = []
foreach m : clang_modules
dep_clang += cpp.find_library(m, dirs : llvm_libdir, required : true)
endforeach
endif
# Be explicit about only using this lib on Windows, to avoid picking
# up random libs with the generic name 'libversion'
dep_version = null_dep
if with_opencl_spirv and host_machine.system() == 'windows'
dep_version = cpp.find_library('version')
endif
with_opencl_native = _opencl != 'disabled' and get_option('opencl-native')
if (with_amd_vk or with_gallium_radeonsi or
@ -1986,6 +2052,7 @@ if with_platform_x11
dep_xcb_present.version().version_compare('>= 1.13'))
pre_args += '-DHAVE_DRI3_MODIFIERS'
endif
dep_xcb_shm = dependency('xcb-shm')
dep_xcb_sync = dependency('xcb-sync')
dep_xshmfence = dependency('xshmfence', version : '>= 1.1')
endif
@ -2187,6 +2254,9 @@ if with_egl
if with_dri3
egl_drivers += 'builtin:egl_dri3'
endif
if with_platform_windows
egl_drivers += 'builtin:wgl'
endif
lines += 'EGL drivers: ' + ' '.join(egl_drivers)
endif
if with_egl or with_any_vk

8
mesa 3D driver/meson_options.txt
View File

@ -482,7 +482,7 @@ option(
'platform-sdk-version',
type : 'integer',
min : 25,
max : 30,
max : 31,
value : 25,
description : 'Android Platform SDK version. Default: Nougat version.'
)
@ -524,3 +524,9 @@ option(
value : '',
description : 'Enable a custom shader replacement mechanism. Note that enabling this option requires adding/generating a shader_replacement.h file that can be included (see shaderapi.c).'
)
option(
'vmware-mks-stats',
type : 'boolean',
value : false,
description : 'Build gallium VMware/svga driver with mksGuestStats instrumentation.'
)

51
mesa 3D driver/src/amd/addrlib/inc/addrinterface.h
View File

@ -1,28 +1,29 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
****************************************************************************************************
*/
/**
****************************************************************************************************

51
mesa 3D driver/src/amd/addrlib/inc/addrtypes.h
View File

@ -1,28 +1,29 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
****************************************************************************************************
*/
/**
****************************************************************************************************

51
mesa 3D driver/src/amd/addrlib/src/addrinterface.cpp
View File

@ -1,28 +1,29 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
****************************************************************************************************
*/
/**
****************************************************************************************************

51
mesa 3D driver/src/amd/addrlib/src/amdgpu_asic_addr.h
View File

@ -1,28 +1,29 @@
/*
* Copyright © 2017-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
***********************************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
***********************************************************************************************************************
*/
#ifndef _AMDGPU_ASIC_ADDR_H
#define _AMDGPU_ASIC_ADDR_H

51
mesa 3D driver/src/amd/addrlib/src/chip/r800/si_gb_reg.h
View File

@ -1,28 +1,29 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
****************************************************************************************************
*/
#if !defined (__SI_GB_REG_H__)
#define __SI_GB_REG_H__

51
mesa 3D driver/src/amd/addrlib/src/core/addrcommon.h
View File

@ -1,28 +1,29 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
****************************************************************************************************
*/
/**
****************************************************************************************************

51
mesa 3D driver/src/amd/addrlib/src/core/addrelemlib.cpp
View File

@ -1,28 +1,29 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
****************************************************************************************************
*/
/**
****************************************************************************************************

52
mesa 3D driver/src/amd/addrlib/src/core/addrelemlib.h
View File

@ -1,28 +1,30 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
****************************************************************************************************
*/
/**
****************************************************************************************************

51
mesa 3D driver/src/amd/addrlib/src/core/addrlib.cpp
View File

@ -1,28 +1,29 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
****************************************************************************************************
*/
/**
****************************************************************************************************

51
mesa 3D driver/src/amd/addrlib/src/core/addrlib.h
View File

@ -1,28 +1,29 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
****************************************************************************************************
*/
/**
****************************************************************************************************

51
mesa 3D driver/src/amd/addrlib/src/core/addrlib1.cpp
View File

@ -1,28 +1,29 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
****************************************************************************************************
*/
/**
****************************************************************************************************

52
mesa 3D driver/src/amd/addrlib/src/core/addrlib1.h
View File

@ -1,28 +1,30 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
****************************************************************************************************
*/
/**
****************************************************************************************************

52
mesa 3D driver/src/amd/addrlib/src/core/addrlib2.cpp
View File

@ -1,28 +1,30 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
************************************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
************************************************************************************************************************
*/
/**
************************************************************************************************************************

52
mesa 3D driver/src/amd/addrlib/src/core/addrlib2.h
View File

@ -1,28 +1,30 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
************************************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
************************************************************************************************************************
*/
/**
************************************************************************************************************************

52
mesa 3D driver/src/amd/addrlib/src/core/addrobject.cpp
View File

@ -1,28 +1,30 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
****************************************************************************************************
*/
/**
****************************************************************************************************

52
mesa 3D driver/src/amd/addrlib/src/core/addrobject.h
View File

@ -1,28 +1,30 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
****************************************************************************************************
*/
/**
****************************************************************************************************

51
mesa 3D driver/src/amd/addrlib/src/core/coord.cpp
View File

@ -1,29 +1,30 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
****************************************************************************************************
*/
// Coordinate class implementation
#include "addrcommon.h"

51
mesa 3D driver/src/amd/addrlib/src/core/coord.h
View File

@ -1,28 +1,29 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
****************************************************************************************************
*/
// Class used to define a coordinate bit

53
mesa 3D driver/src/amd/addrlib/src/gfx10/gfx10SwizzlePattern.h
View File

@ -1,28 +1,29 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
************************************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
************************************************************************************************************************
*/
/**
************************************************************************************************************************
@ -3739,7 +3740,6 @@ const ADDR_SW_PATINFO GFX10_SW_VAR_Z_X_8xaa_RBPLUS_PATINFO[] =
{ 3, 27, 344, 365, 124, } , // 64 pipes (32 PKRs) 16 bpe @ SW_VAR_Z_X 8xaa @ RbPlus
};
const UINT_64 GFX10_SW_PATTERN_NIBBLE01[][8] =
{
{X0, X1, X2, X3, Y0, Y1, Y2, Y3, }, // 0
@ -5849,7 +5849,6 @@ const UINT_8 GFX10_CMASK_VAR_RBPLUS_PATIDX[] =
31, // 64 pipes (32 PKRs) 8 bpe pa @ CMASK_VAR @ RbPlus
};
const UINT_64 GFX10_DCC_64K_R_X_SW_PATTERN[][17] =
{
{0, X4, Y4, X5, Y5, X6, Y6, X7, Y7, X8, Y8, X9, Y9, 0, 0, 0, 0, }, //0

125
mesa 3D driver/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp
View File

@ -1,28 +1,29 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
************************************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
************************************************************************************************************************
*/
/**
************************************************************************************************************************
@ -66,46 +67,46 @@ namespace V2
const SwizzleModeFlags Gfx10Lib::SwizzleModeTable[ADDR_SW_MAX_TYPE] =
{//Linear 256B 4KB 64KB Var Z Std Disp Rot XOR T RtOpt Reserved
{1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // ADDR_SW_LINEAR
{0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0}, // ADDR_SW_256B_S
{0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0}, // ADDR_SW_256B_D
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Reserved
{{1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // ADDR_SW_LINEAR
{{0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0}}, // ADDR_SW_256B_S
{{0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0}}, // ADDR_SW_256B_D
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // Reserved
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Reserved
{0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0}, // ADDR_SW_4KB_S
{0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0}, // ADDR_SW_4KB_D
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Reserved
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // Reserved
{{0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0}}, // ADDR_SW_4KB_S
{{0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0}}, // ADDR_SW_4KB_D
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // Reserved
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Reserved
{0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0}, // ADDR_SW_64KB_S
{0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0}, // ADDR_SW_64KB_D
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Reserved
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // Reserved
{{0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0}}, // ADDR_SW_64KB_S
{{0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0}}, // ADDR_SW_64KB_D
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // Reserved
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Reserved
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Reserved
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Reserved
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Reserved
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // Reserved
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // Reserved
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // Reserved
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // Reserved
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Reserved
{0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 1, 0, 0}, // ADDR_SW_64KB_S_T
{0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 0, 0}, // ADDR_SW_64KB_D_T
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Reserved
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // Reserved
{{0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 1, 0, 0}}, // ADDR_SW_64KB_S_T
{{0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 0, 0}}, // ADDR_SW_64KB_D_T
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // Reserved
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Reserved
{0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0}, // ADDR_SW_4KB_S_X
{0, 0, 1, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0}, // ADDR_SW_4KB_D_X
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Reserved
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // Reserved
{{0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0}}, // ADDR_SW_4KB_S_X
{{0, 0, 1, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0}}, // ADDR_SW_4KB_D_X
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // Reserved
{0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0}, // ADDR_SW_64KB_Z_X
{0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0}, // ADDR_SW_64KB_S_X
{0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0}, // ADDR_SW_64KB_D_X
{0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0}, // ADDR_SW_64KB_R_X
{{0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0}}, // ADDR_SW_64KB_Z_X
{{0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0}}, // ADDR_SW_64KB_S_X
{{0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0}}, // ADDR_SW_64KB_D_X
{{0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0}}, // ADDR_SW_64KB_R_X
{0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0}, // ADDR_SW_VAR_Z_X
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Reserved
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Reserved
{0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 1, 0}, // ADDR_SW_VAR_R_X
{1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // ADDR_SW_LINEAR_GENERAL
{{0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0}}, // ADDR_SW_VAR_Z_X
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // Reserved
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // Reserved
{{0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 1, 0}}, // ADDR_SW_VAR_R_X
{{1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // ADDR_SW_LINEAR_GENERAL
};
const Dim3d Gfx10Lib::Block256_3d[] = {{8, 4, 8}, {4, 4, 8}, {4, 4, 4}, {4, 2, 4}, {2, 2, 4}};
@ -611,7 +612,6 @@ ADDR_E_RETURNCODE Gfx10Lib::HwlComputeCmaskAddrFromCoord(
(pIn->swizzleMode == ADDR_SW_VAR_Z_X) ? GFX10_CMASK_VAR_RBPLUS_PATIDX :
(m_settings.supportRbPlus ? GFX10_CMASK_64K_RBPLUS_PATIDX : GFX10_CMASK_64K_PATIDX);
const UINT_32 blkSizeLog2 = Log2(output.metaBlkWidth) + Log2(output.metaBlkHeight) - 7;
const UINT_32 blkMask = (1 << blkSizeLog2) - 1;
const UINT_32 blkOffset = ComputeOffsetFromSwizzlePattern(GFX10_CMASK_SW_PATTERN[patIdxTable[index]],
@ -680,7 +680,6 @@ ADDR_E_RETURNCODE Gfx10Lib::HwlComputeHtileAddrFromCoord(
const UINT_32 index = m_xmaskBaseIndex + numSampleLog2;
const UINT_8* patIdxTable = m_settings.supportRbPlus ? GFX10_HTILE_RBPLUS_PATIDX : GFX10_HTILE_PATIDX;
const UINT_32 blkSizeLog2 = Log2(output.metaBlkWidth) + Log2(output.metaBlkHeight) - 4;
const UINT_32 blkMask = (1 << blkSizeLog2) - 1;
const UINT_32 blkOffset = ComputeOffsetFromSwizzlePattern(GFX10_HTILE_SW_PATTERN[patIdxTable[index]],
@ -992,7 +991,6 @@ BOOL_32 Gfx10Lib::HwlInitGlobalParams(
m_blockVarSizeLog2 = m_pipesLog2 + 14;
}
if (valid)
{
InitEquationTable();
@ -2511,7 +2509,6 @@ BOOL_32 Gfx10Lib::ValidateNonSwModeParams(
const BOOL_32 tex1d = IsTex1d(rsrcType);
const BOOL_32 stereo = flags.qbStereo;
// Resource type check
if (tex1d)
{
@ -2640,7 +2637,6 @@ BOOL_32 Gfx10Lib::ValidateSwModeParams(
ADDR_ASSERT_ALWAYS();
valid = FALSE;
}
}
else if (tex3d)
{
@ -2956,7 +2952,6 @@ ADDR_E_RETURNCODE Gfx10Lib::HwlGetPreferredSurfaceSetting(
case ADDR_RSRC_TEX_2D:
allowedSwModeSet.value &= pIn->flags.prt ? Gfx10Rsrc2dPrtSwModeMask : Gfx10Rsrc2dSwModeMask;
break;
case ADDR_RSRC_TEX_3D:
@ -3522,7 +3517,6 @@ ADDR_E_RETURNCODE Gfx10Lib::HwlComputeSurfaceInfoTiled(
return ret;
}
/**
************************************************************************************************************************
* Gfx10Lib::ComputeSurfaceInfoMicroTiled
@ -4329,7 +4323,6 @@ const ADDR_SW_PATINFO* Gfx10Lib::GetSwizzlePatternInfo(
return (patInfo != NULL) ? &patInfo[index] : NULL;
}
/**
************************************************************************************************************************
* Gfx10Lib::ComputeSurfaceAddrFromCoordMicroTiled

52
mesa 3D driver/src/amd/addrlib/src/gfx10/gfx10addrlib.h
View File

@ -1,28 +1,29 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
************************************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
************************************************************************************************************************
*/
/**
************************************************************************************************************************
@ -355,7 +356,6 @@ class Gfx10Lib : public Lib
const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
UINT_32 ComputeOffsetFromSwizzlePattern(
const UINT_64* pPattern,
UINT_32 numBits,

117
mesa 3D driver/src/amd/addrlib/src/gfx9/gfx9addrlib.cpp
View File

@ -1,28 +1,29 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
****************************************************************************************************
*/
/**
************************************************************************************************************************
@ -68,46 +69,46 @@ namespace V2
const SwizzleModeFlags Gfx9Lib::SwizzleModeTable[ADDR_SW_MAX_TYPE] =
{//Linear 256B 4KB 64KB Var Z Std Disp Rot XOR T RtOpt Reserved
{1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // ADDR_SW_LINEAR
{0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0}, // ADDR_SW_256B_S
{0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0}, // ADDR_SW_256B_D
{0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0}, // ADDR_SW_256B_R
{{1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // ADDR_SW_LINEAR
{{0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0}}, // ADDR_SW_256B_S
{{0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0}}, // ADDR_SW_256B_D
{{0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0}}, // ADDR_SW_256B_R
{0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0}, // ADDR_SW_4KB_Z
{0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0}, // ADDR_SW_4KB_S
{0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0}, // ADDR_SW_4KB_D
{0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0}, // ADDR_SW_4KB_R
{{0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0}}, // ADDR_SW_4KB_Z
{{0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0}}, // ADDR_SW_4KB_S
{{0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0}}, // ADDR_SW_4KB_D
{{0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0}}, // ADDR_SW_4KB_R
{0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0}, // ADDR_SW_64KB_Z
{0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0}, // ADDR_SW_64KB_S
{0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0}, // ADDR_SW_64KB_D
{0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0}, // ADDR_SW_64KB_R
{{0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0}}, // ADDR_SW_64KB_Z
{{0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0}}, // ADDR_SW_64KB_S
{{0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0}}, // ADDR_SW_64KB_D
{{0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0}}, // ADDR_SW_64KB_R
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Reserved
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Reserved
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Reserved
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Reserved
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // Reserved
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // Reserved
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // Reserved
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // Reserved
{0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0}, // ADDR_SW_64KB_Z_T
{0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 1, 0, 0}, // ADDR_SW_64KB_S_T
{0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 0, 0}, // ADDR_SW_64KB_D_T
{0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0}, // ADDR_SW_64KB_R_T
{{0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0}}, // ADDR_SW_64KB_Z_T
{{0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 1, 0, 0}}, // ADDR_SW_64KB_S_T
{{0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 0, 0}}, // ADDR_SW_64KB_D_T
{{0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0}}, // ADDR_SW_64KB_R_T
{0, 0, 1, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0}, // ADDR_SW_4KB_Z_x
{0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0}, // ADDR_SW_4KB_S_x
{0, 0, 1, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0}, // ADDR_SW_4KB_D_x
{0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0}, // ADDR_SW_4KB_R_x
{{0, 0, 1, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0}}, // ADDR_SW_4KB_Z_x
{{0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0}}, // ADDR_SW_4KB_S_x
{{0, 0, 1, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0}}, // ADDR_SW_4KB_D_x
{{0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0}}, // ADDR_SW_4KB_R_x
{0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0}, // ADDR_SW_64KB_Z_X
{0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0}, // ADDR_SW_64KB_S_X
{0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0}, // ADDR_SW_64KB_D_X
{0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0}, // ADDR_SW_64KB_R_X
{{0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0}}, // ADDR_SW_64KB_Z_X
{{0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0}}, // ADDR_SW_64KB_S_X
{{0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0}}, // ADDR_SW_64KB_D_X
{{0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0}}, // ADDR_SW_64KB_R_X
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Reserved
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Reserved
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Reserved
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // Reserved
{1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, // ADDR_SW_LINEAR_GENERAL
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // Reserved
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // Reserved
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // Reserved
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // Reserved
{{1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, // ADDR_SW_LINEAR_GENERAL
};
const UINT_32 Gfx9Lib::MipTailOffset256B[] = {2048, 1024, 512, 256, 128, 64, 32, 16, 8, 6, 5, 4, 3, 2, 1, 0};

51
mesa 3D driver/src/amd/addrlib/src/gfx9/gfx9addrlib.h
View File

@ -1,28 +1,29 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
****************************************************************************************************
*/
/**
************************************************************************************************************************

51
mesa 3D driver/src/amd/addrlib/src/r800/ciaddrlib.cpp
View File

@ -1,28 +1,29 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
****************************************************************************************************
*/
/**
****************************************************************************************************

51
mesa 3D driver/src/amd/addrlib/src/r800/ciaddrlib.h
View File

@ -1,28 +1,29 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
****************************************************************************************************
*/
/**
****************************************************************************************************

51
mesa 3D driver/src/amd/addrlib/src/r800/egbaddrlib.cpp
View File

@ -1,28 +1,29 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
****************************************************************************************************
*/
/**
****************************************************************************************************
* @file egbaddrlib.cpp

51
mesa 3D driver/src/amd/addrlib/src/r800/egbaddrlib.h
View File

@ -1,28 +1,29 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
****************************************************************************************************
*/
/**
****************************************************************************************************

51
mesa 3D driver/src/amd/addrlib/src/r800/siaddrlib.cpp
View File

@ -1,28 +1,29 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
****************************************************************************************************
*/
/**
****************************************************************************************************

51
mesa 3D driver/src/amd/addrlib/src/r800/siaddrlib.h
View File

@ -1,28 +1,29 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
*
* Copyright © 2007-2021 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
*
****************************************************************************************************
*/
/**
****************************************************************************************************

10
mesa 3D driver/src/amd/ci/deqp-radv-bonaire-aco-skips.txt
View File

@ -1,12 +1,2 @@
# Exclude this test which might fail when a new extension is implemented.
dEQP-VK.info.device_extensions
# Exclude WSI related tests.
dEQP-VK.image.swapchain_mutable.*
dEQP-VK.wsi.*
# This subset of CTS randomly hangs but it's fine when using only one thread.
dEQP-VK.synchronization.*
# Exclude this test which timeout most of the time.
dEQP-VK.memory.pipeline_barrier.transfer_src_transfer_dst.1048576

10
mesa 3D driver/src/amd/ci/deqp-radv-hawaii-aco-skips.txt
View File

@ -1,12 +1,2 @@
# Exclude this test which might fail when a new extension is implemented.
dEQP-VK.info.device_extensions
# Exclude WSI related tests.
dEQP-VK.image.swapchain_mutable.*
dEQP-VK.wsi.*
# This subset of CTS randomly hangs but it's fine when using only one thread.
dEQP-VK.synchronization.*
# Exclude this test which timeout most of the time.
dEQP-VK.memory.pipeline_barrier.transfer_src_transfer_dst.1048576

2
mesa 3D driver/src/amd/ci/deqp-radv-raven-aco-flakes.txt Normal file
View File

@ -0,0 +1,2 @@
dEQP-VK.api.object_management.multithreaded_per_thread_device.image_2d
dEQP-VK.api.object_management.multithreaded_per_thread_resources.image_2d

12
mesa 3D driver/src/amd/ci/deqp-radv-raven-aco-skips.txt
View File

@ -1,13 +1,3 @@
# Exclude this test which might fail when a new extension is implemented.
dEQP-VK.info.device_extensions
# Exclude WSI related tests.
dEQP-VK.image.swapchain_mutable.*
dEQP-VK.wsi.*
# This subset of CTS seems to randomly hangs on RAVEN only.
# This subset of CTS seems to randomly hang on RAVEN and BONAIRE.
# This needs to be investigated and fixed!
dEQP-VK.synchronization.*
# Exclude this test which timeout most of the time.
dEQP-VK.memory.pipeline_barrier.transfer_src_transfer_dst.1048576

2
mesa 3D driver/src/amd/ci/deqp-radv-renoir-aco-flakes.txt Normal file
View File

@ -0,0 +1,2 @@
dEQP-VK.api.object_management.multithreaded_per_thread_device.image_2d
dEQP-VK.api.object_management.multithreaded_per_thread_resources.image_2d

9
mesa 3D driver/src/amd/ci/deqp-radv-skips.txt Normal file
View File

@ -0,0 +1,9 @@
# Exclude this test which might fail when a new extension is implemented.
dEQP-VK.info.device_extensions
# Exclude WSI related tests.
dEQP-VK.image.swapchain_mutable.*
dEQP-VK.wsi.*
# Exclude this test which timeout most of the time.
dEQP-VK.memory.pipeline_barrier.transfer_src_transfer_dst.1048576

10
mesa 3D driver/src/amd/ci/deqp-radv-stoney-aco-skips.txt
View File

@ -1,13 +1,3 @@
# Exclude this test which might fail when a new extension is implemented.
dEQP-VK.info.device_extensions
# Exclude WSI related tests.
dEQP-VK.image.swapchain_mutable.*
dEQP-VK.wsi.*
# Exclude this test which timeout most of the time.
dEQP-VK.memory.pipeline_barrier.transfer_src_transfer_dst.1048576
# These tests take too long to run on the current STONEY testing hardware, skip them.
dEQP-VK.texture.explicit_lod.2d.sizes.128x128_linear_linear_mipmap_linear_clamp
dEQP-VK.texture.explicit_lod.2d.sizes.128x128_linear_linear_mipmap_linear_repeat

0
mesa 3D driver/src/amd/ci/deqp-radv-vangogh-aco-fails.txt Normal file
View File

2
mesa 3D driver/src/amd/ci/deqp-radv-vega10-aco-flakes.txt Normal file
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@ -0,0 +1,2 @@
dEQP-VK.api.object_management.multithreaded_per_thread_device.image_2d
dEQP-VK.api.object_management.multithreaded_per_thread_resources.image_2d

6
mesa 3D driver/src/amd/ci/gitlab-ci.yml
View File

@ -4,6 +4,7 @@
- .radv-rules
variables:
VK_DRIVER: radeon
DRIVER_NAME: radv
ACO_DEBUG: validateir,validatera
MESA_VK_IGNORE_CONFORMANCE_WARNING: 1
@ -50,7 +51,7 @@ radv_polaris10_vkcts:
- .test-radv
- .test-manual
variables:
GPU_VERSION: radv-polaris10
GPU_VERSION: radv-polaris10-aco
tags:
- polaris10
@ -63,7 +64,7 @@ radv_stoney_vkcts:amd64:
variables:
DEQP_VER: vk
DEQP_FRACTION: 10
DEQP_PARALLEL: 4
FDO_CI_CONCURRENT: 4
DEQP_EXPECTED_RENDERER: STONEY
DEVICE_TYPE: hp-11A-G6-EE-grunt
DTB: ""
@ -73,6 +74,7 @@ radv_stoney_vkcts:amd64:
HWCI_KERNEL_MODULES: amdgpu
HWCI_FREQ_MAX: "true"
VK_DRIVER: radeon
DRIVER_NAME: radv
tags:
- mesa-ci-x86-64-lava-hp-11A-G6-EE-grunt

64
mesa 3D driver/src/amd/common/ac_debug.c
View File

@ -42,6 +42,8 @@
#include <assert.h>
#include <inttypes.h>
DEBUG_GET_ONCE_BOOL_OPTION(color, "AMD_COLOR", true);
/* Parsed IBs are difficult to read without colors. Use "less -R file" to
* read them, or use "aha -b -f file" to convert them to html.
*/
@ -51,6 +53,12 @@
#define COLOR_YELLOW "\033[1;33m"
#define COLOR_CYAN "\033[1;36m"
#define O_COLOR_RESET (debug_get_option_color() ? COLOR_RESET : "")
#define O_COLOR_RED (debug_get_option_color() ? COLOR_RED : "")
#define O_COLOR_GREEN (debug_get_option_color() ? COLOR_GREEN : "")
#define O_COLOR_YELLOW (debug_get_option_color() ? COLOR_YELLOW : "")
#define O_COLOR_CYAN (debug_get_option_color() ? COLOR_CYAN : "")
#define INDENT_PKT 8
struct ac_ib_parser {
@ -95,7 +103,9 @@ static void print_value(FILE *file, uint32_t value, int bits)
static void print_named_value(FILE *file, const char *name, uint32_t value, int bits)
{
print_spaces(file, INDENT_PKT);
fprintf(file, COLOR_YELLOW "%s" COLOR_RESET " <- ", name);
fprintf(file, "%s%s%s <- ",
O_COLOR_YELLOW, name,
O_COLOR_RESET);
print_value(file, value, bits);
}
@ -157,7 +167,9 @@ void ac_dump_reg(FILE *file, enum chip_class chip_class, unsigned offset, uint32
bool first_field = true;
print_spaces(file, INDENT_PKT);
fprintf(file, COLOR_YELLOW "%s" COLOR_RESET " <- ", reg_name);
fprintf(file, "%s%s%s <- ",
O_COLOR_YELLOW, reg_name,
O_COLOR_RESET);
if (!reg->num_fields) {
print_value(file, value, 32);
@ -190,7 +202,9 @@ void ac_dump_reg(FILE *file, enum chip_class chip_class, unsigned offset, uint32
}
print_spaces(file, INDENT_PKT);
fprintf(file, COLOR_YELLOW "0x%05x" COLOR_RESET " <- 0x%08x\n", offset, value);
fprintf(file, "%s0x%05x%s <- 0x%08x\n",
O_COLOR_YELLOW, offset,
O_COLOR_RESET, value);
}
static uint32_t ac_ib_get(struct ac_ib_parser *ib)
@ -208,7 +222,8 @@ static uint32_t ac_ib_get(struct ac_ib_parser *ib)
* and radeon_emit is performance sensitive...
*/
if (VALGRIND_CHECK_VALUE_IS_DEFINED(v))
fprintf(ib->f, COLOR_RED "Valgrind: The next DWORD is garbage" COLOR_RESET "\n");
fprintf(ib->f, "%sValgrind: The next DWORD is garbage%s\n",
debug_get_option_color() ? COLOR_RED : "", O_COLOR_RESET);
#endif
fprintf(ib->f, "\n\035#%08x ", v);
} else {
@ -255,11 +270,11 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
if (op == PKT3_SET_CONTEXT_REG || op == PKT3_SET_CONFIG_REG || op == PKT3_SET_UCONFIG_REG ||
op == PKT3_SET_UCONFIG_REG_INDEX || op == PKT3_SET_SH_REG)
fprintf(f, COLOR_CYAN "%s%s" COLOR_CYAN ":\n", name, predicate);
fprintf(f, "%s%s%s%s:\n", O_COLOR_CYAN, name, predicate, O_COLOR_RESET);
else
fprintf(f, COLOR_GREEN "%s%s" COLOR_RESET ":\n", name, predicate);
fprintf(f, "%s%s%s%s:\n", O_COLOR_GREEN, name, predicate, O_COLOR_RESET);
} else
fprintf(f, COLOR_RED "PKT3_UNKNOWN 0x%x%s" COLOR_RESET ":\n", op, predicate);
fprintf(f, "%sPKT3_UNKNOWN 0x%x%s%s:\n", O_COLOR_RED, op, predicate, O_COLOR_RESET);
/* Print the contents. */
switch (op) {
@ -459,7 +474,7 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
unsigned packet_id = AC_GET_TRACE_POINT_ID(ib->ib[ib->cur_dw]);
print_spaces(f, INDENT_PKT);
fprintf(f, COLOR_RED "Trace point ID: %u\n", packet_id);
fprintf(f, "%sTrace point ID: %u%s\n", O_COLOR_RED, packet_id, O_COLOR_RESET);
if (!ib->trace_id_count)
break; /* tracing was disabled */
@ -467,17 +482,22 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
*current_trace_id = packet_id;
print_spaces(f, INDENT_PKT);
if (packet_id < *ib->trace_ids)
fprintf(f, COLOR_RED "This trace point was reached by the CP." COLOR_RESET "\n");
else if (packet_id == *ib->trace_ids)
fprintf(f, COLOR_RED "!!!!! This is the last trace point that "
"was reached by the CP !!!!!" COLOR_RESET "\n");
else if (packet_id + 1 == *ib->trace_ids)
fprintf(f, COLOR_RED "!!!!! This is the first trace point that "
"was NOT been reached by the CP !!!!!" COLOR_RESET "\n");
else
fprintf(f, COLOR_RED "!!!!! This trace point was NOT reached "
"by the CP !!!!!" COLOR_RESET "\n");
if (packet_id < *ib->trace_ids) {
fprintf(f, "%sThis trace point was reached by the CP.%s\n",
O_COLOR_RED, O_COLOR_RESET);
} else if (packet_id == *ib->trace_ids) {
fprintf(f, "%s!!!!! This is the last trace point that "
"was reached by the CP !!!!!%s\n",
O_COLOR_RED, O_COLOR_RESET);
} else if (packet_id + 1 == *ib->trace_ids) {
fprintf(f, "%s!!!!! This is the first trace point that "
"was NOT been reached by the CP !!!!!%s\n",
O_COLOR_RED, O_COLOR_RESET);
} else {
fprintf(f, "%s!!!!! This trace point was NOT reached "
"by the CP !!!!!%s\n",
O_COLOR_RED, O_COLOR_RESET);
}
break;
}
break;
@ -488,7 +508,8 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
ac_ib_get(ib);
if (ib->cur_dw > first_dw + count + 1)
fprintf(f, COLOR_RED " !!!!! count in header too low !!!!!" COLOR_RESET "\n");
fprintf(f, "%s !!!!! count in header too low !!!!!%s\n",
O_COLOR_RED, O_COLOR_RESET);
}
/**
@ -509,7 +530,8 @@ static void ac_do_parse_ib(FILE *f, struct ac_ib_parser *ib)
case 2:
/* type-2 nop */
if (header == 0x80000000) {
fprintf(f, COLOR_GREEN "NOP (type 2)" COLOR_RESET "\n");
fprintf(f, "%sNOP (type 2)%s\n",
O_COLOR_GREEN, O_COLOR_RESET);
break;
}
FALLTHROUGH;

2
mesa 3D driver/src/amd/common/ac_exp_param.h
View File

@ -35,7 +35,7 @@ enum
AC_EXP_PARAM_DEFAULT_VAL_0001,
AC_EXP_PARAM_DEFAULT_VAL_1110,
AC_EXP_PARAM_DEFAULT_VAL_1111,
AC_EXP_PARAM_UNDEFINED = 255,
AC_EXP_PARAM_UNDEFINED = 255, /* deprecated, use AC_EXP_PARAM_DEFAULT_VAL_0000 instead */
};
#endif

26
mesa 3D driver/src/amd/common/ac_gpu_info.c
View File

@ -32,6 +32,7 @@
#include "util/u_math.h"
#include <stdio.h>
#include <ctype.h>
#ifdef _WIN32
#define DRM_CAP_ADDFB2_MODIFIERS 0x10
@ -553,10 +554,6 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->all_vram_visible = info->vram_size * 0.9 < info->vram_vis_size;
util_cpu_detect();
info->smart_access_memory = info->all_vram_visible &&
info->chip_class >= GFX10_3 &&
util_get_cpu_caps()->family >= CPU_AMD_ZEN3 &&
util_get_cpu_caps()->family < CPU_AMD_LAST;
/* Set chip identification. */
info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
@ -636,6 +633,10 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
return false;
}
memset(info->lowercase_name, 0, sizeof(info->lowercase_name));
for (unsigned i = 0; info->name[i] && i < ARRAY_SIZE(info->lowercase_name) - 1; i++)
info->lowercase_name[i] = tolower(info->name[i]);
if (info->family >= CHIP_SIENNA_CICHLID)
info->chip_class = GFX10_3;
else if (info->family >= CHIP_NAVI10)
@ -653,6 +654,11 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
return false;
}
info->smart_access_memory = info->all_vram_visible &&
info->chip_class >= GFX10_3 &&
util_get_cpu_caps()->family >= CPU_AMD_ZEN3 &&
util_get_cpu_caps()->family < CPU_AMD_LAST;
info->family_id = amdinfo->family_id;
info->chip_external_rev = amdinfo->chip_external_rev;
info->marketing_name = amdgpu_get_marketing_name(dev);
@ -869,6 +875,13 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
/* Whether chips support double rate packed math instructions. */
info->has_packed_math_16bit = info->chip_class >= GFX9;
/* Whether chips support dot product instructions. A subset of these support a smaller
* instruction encoding which accumulates with the destination.
*/
info->has_accelerated_dot_product =
info->family == CHIP_ARCTURUS || info->family == CHIP_ALDEBARAN ||
info->family == CHIP_VEGA20 || info->family >= CHIP_NAVI12;
/* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
info->has_load_ctx_reg_pkt =
info->chip_class >= GFX9 || (info->chip_class >= GFX8 && info->me_fw_feature >= 41);
@ -900,9 +913,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
*/
info->has_two_planes_iterate256_bug = info->chip_class == GFX10;
/* GE has a bug when a legacy GS draw follows an NGG draw and it requires
* a VGT_FLUSH to fix that.
*/
/* GFX10+Sienna: NGG->legacy transitions require VGT_FLUSH. */
info->has_vgt_flush_ngg_legacy_bug = info->chip_class == GFX10 ||
info->family == CHIP_SIENNA_CICHLID;
@ -1127,6 +1138,7 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f)
info->pci_dev, info->pci_func);
fprintf(f, " name = %s\n", info->name);
fprintf(f, " lowercase_name = %s\n", info->lowercase_name);
fprintf(f, " marketing_name = %s\n", info->marketing_name);
fprintf(f, " is_pro_graphics = %u\n", info->is_pro_graphics);
fprintf(f, " pci_id = 0x%x\n", info->pci_id);

2
mesa 3D driver/src/amd/common/ac_gpu_info.h
View File

@ -48,6 +48,7 @@ struct radeon_info {
/* Device info. */
const char *name;
char lowercase_name[32];
const char *marketing_name;
bool is_pro_graphics;
uint32_t pci_id;
@ -70,6 +71,7 @@ struct radeon_info {
bool has_load_ctx_reg_pkt;
bool has_out_of_order_rast;
bool has_packed_math_16bit;
bool has_accelerated_dot_product;
bool cpdma_prefetch_writes_memory;
bool has_gfx9_scissor_bug;
bool has_tc_compat_zrange_bug;

21
mesa 3D driver/src/amd/common/ac_nir.h
View File

@ -91,26 +91,19 @@ bool
ac_nir_lower_indirect_derefs(nir_shader *shader,
enum chip_class chip_class);
typedef struct
{
unsigned lds_bytes_if_culling_off;
bool can_cull;
bool passthrough;
bool early_prim_export;
uint64_t nggc_inputs_read_by_pos;
uint64_t nggc_inputs_read_by_others;
} ac_nir_ngg_config;
ac_nir_ngg_config
void
ac_nir_lower_ngg_nogs(nir_shader *shader,
unsigned max_num_es_vertices,
unsigned num_vertices_per_primitive,
unsigned max_workgroup_size,
unsigned wave_size,
bool consider_culling,
bool consider_passthrough,
bool can_cull,
bool early_prim_export,
bool passthrough,
bool export_prim_id,
bool provoking_vtx_last);
bool provoking_vtx_last,
bool use_edgeflags,
uint32_t instance_rate_inputs);
void
ac_nir_lower_ngg_gs(nir_shader *shader,

9
mesa 3D driver/src/amd/common/ac_nir_cull.c
View File

@ -75,7 +75,14 @@ cull_face(nir_builder *b, nir_ssa_def *pos[3][4], const position_w_info *w_info)
nir_ssa_def *cull_front = nir_build_load_cull_front_face_enabled_amd(b);
nir_ssa_def *cull_back = nir_build_load_cull_back_face_enabled_amd(b);
return nir_inot(b, nir_bcsel(b, front_facing, cull_front, cull_back));
nir_ssa_def *face_culled = nir_bcsel(b, front_facing, cull_front, cull_back);
/* Don't reject NaN and +/-infinity, these are tricky.
* Just trust fixed-function HW to handle these cases correctly.
*/
face_culled = nir_iand(b, face_culled, nir_fisfinite(b, det));
return nir_inot(b, face_culled);
}
static nir_ssa_def *

4
mesa 3D driver/src/amd/common/ac_nir_lower_esgs_io_to_mem.c
View File

@ -169,8 +169,8 @@ gs_per_vertex_input_vertex_offset_gfx9(nir_builder *b, nir_src *vertex_src)
{
if (nir_src_is_const(*vertex_src)) {
unsigned vertex = nir_src_as_uint(*vertex_src);
return nir_ubfe(b, nir_build_load_gs_vertex_offset_amd(b, .base = vertex / 2u * 2u),
nir_imm_int(b, (vertex % 2u) * 16u), nir_imm_int(b, 16u));
return nir_ubfe(b, nir_build_load_gs_vertex_offset_amd(b, .base = vertex / 2u),
nir_imm_int(b, (vertex & 1u) * 16u), nir_imm_int(b, 16u));
}
nir_ssa_def *vertex_offset = nir_build_load_gs_vertex_offset_amd(b, .base = 0);

422
mesa 3D driver/src/amd/common/ac_nir_lower_ngg.c
View File

@ -51,6 +51,7 @@ typedef struct
bool passthrough;
bool export_prim_id;
bool early_prim_export;
bool use_edgeflags;
unsigned wave_size;
unsigned max_num_waves;
unsigned num_vertices_per_primitives;
@ -60,6 +61,10 @@ typedef struct
uint64_t inputs_needed_by_pos;
uint64_t inputs_needed_by_others;
uint32_t instance_rate_inputs;
nir_instr *compact_arg_stores[4];
nir_intrinsic_instr *overwrite_args;
} lower_ngg_nogs_state;
typedef struct
@ -97,11 +102,6 @@ typedef struct {
nir_variable *pos_value_replacement;
} remove_extra_position_output_state;
typedef struct {
nir_ssa_def *reduction_result;
nir_ssa_def *excl_scan_result;
} wg_scan_result;
/* Per-vertex LDS layout of culling shaders */
enum {
/* Position of the ES vertex (at the beginning for alignment reasons) */
@ -134,6 +134,70 @@ typedef struct {
nir_ssa_def *repacked_invocation_index;
} wg_repack_result;
/**
* Computes a horizontal sum of 8-bit packed values loaded from LDS.
*
* Each lane N will sum packed bytes 0 to N-1.
* We only care about the results from up to wave_id+1 lanes.
* (Other lanes are not deactivated but their calculation is not used.)
*/
static nir_ssa_def *
summarize_repack(nir_builder *b, nir_ssa_def *packed_counts, unsigned num_lds_dwords)
{
/* We'll use shift to filter out the bytes not needed by the current lane.
*
* Need to shift by: num_lds_dwords * 4 - lane_id (in bytes).
* However, two shifts are needed because one can't go all the way,
* so the shift amount is half that (and in bits).
*
* When v_dot4_u32_u8 is available, we right-shift a series of 0x01 bytes.
* This will yield 0x01 at wanted byte positions and 0x00 at unwanted positions,
* therefore v_dot can get rid of the unneeded values.
* This sequence is preferable because it better hides the latency of the LDS.
*
* If the v_dot instruction can't be used, we left-shift the packed bytes.
* This will shift out the unneeded bytes and shift in zeroes instead,
* then we sum them using v_sad_u8.
*/
nir_ssa_def *lane_id = nir_load_subgroup_invocation(b);
nir_ssa_def *shift = nir_iadd_imm_nuw(b, nir_imul_imm(b, lane_id, -4u), num_lds_dwords * 16);
bool use_dot = b->shader->options->has_dot_4x8;
if (num_lds_dwords == 1) {
nir_ssa_def *dot_op = !use_dot ? NULL : nir_ushr(b, nir_ushr(b, nir_imm_int(b, 0x01010101), shift), shift);
/* Broadcast the packed data we read from LDS (to the first 16 lanes, but we only care up to num_waves). */
nir_ssa_def *packed = nir_build_lane_permute_16_amd(b, packed_counts, nir_imm_int(b, 0), nir_imm_int(b, 0));
/* Horizontally add the packed bytes. */
if (use_dot) {
return nir_udot_4x8_uadd(b, packed, dot_op, nir_imm_int(b, 0));
} else {
nir_ssa_def *sad_op = nir_ishl(b, nir_ishl(b, packed, shift), shift);
return nir_sad_u8x4(b, sad_op, nir_imm_int(b, 0), nir_imm_int(b, 0));
}
} else if (num_lds_dwords == 2) {
nir_ssa_def *dot_op = !use_dot ? NULL : nir_ushr(b, nir_ushr(b, nir_imm_int64(b, 0x0101010101010101), shift), shift);
/* Broadcast the packed data we read from LDS (to the first 16 lanes, but we only care up to num_waves). */
nir_ssa_def *packed_dw0 = nir_build_lane_permute_16_amd(b, nir_unpack_64_2x32_split_x(b, packed_counts), nir_imm_int(b, 0), nir_imm_int(b, 0));
nir_ssa_def *packed_dw1 = nir_build_lane_permute_16_amd(b, nir_unpack_64_2x32_split_y(b, packed_counts), nir_imm_int(b, 0), nir_imm_int(b, 0));
/* Horizontally add the packed bytes. */
if (use_dot) {
nir_ssa_def *sum = nir_udot_4x8_uadd(b, packed_dw0, nir_unpack_64_2x32_split_x(b, dot_op), nir_imm_int(b, 0));
return nir_udot_4x8_uadd(b, packed_dw1, nir_unpack_64_2x32_split_y(b, dot_op), sum);
} else {
nir_ssa_def *sad_op = nir_ishl(b, nir_ishl(b, nir_pack_64_2x32_split(b, packed_dw0, packed_dw1), shift), shift);
nir_ssa_def *sum = nir_sad_u8x4(b, nir_unpack_64_2x32_split_x(b, sad_op), nir_imm_int(b, 0), nir_imm_int(b, 0));
return nir_sad_u8x4(b, nir_unpack_64_2x32_split_y(b, sad_op), nir_imm_int(b, 0), sum);
}
} else {
unreachable("Unimplemented NGG wave count");
}
}
/**
* Repacks invocations in the current workgroup to eliminate gaps between them.
*
@ -209,41 +273,7 @@ repack_invocations_in_workgroup(nir_builder *b, nir_ssa_def *input_bool,
*/
nir_ssa_def *num_waves = nir_build_load_num_subgroups(b);
/* sel = 0x01010101 * lane_id + 0x03020100 */
nir_ssa_def *lane_id = nir_load_subgroup_invocation(b);
nir_ssa_def *packed_id = nir_build_byte_permute_amd(b, nir_imm_int(b, 0), lane_id, nir_imm_int(b, 0));
nir_ssa_def *sel = nir_iadd_imm_nuw(b, packed_id, 0x03020100);
nir_ssa_def *sum = NULL;
if (num_lds_dwords == 1) {
/* Broadcast the packed data we read from LDS (to the first 16 lanes, but we only care up to num_waves). */
nir_ssa_def *packed_dw = nir_build_lane_permute_16_amd(b, packed_counts, nir_imm_int(b, 0), nir_imm_int(b, 0));
/* Use byte-permute to filter out the bytes not needed by the current lane. */
nir_ssa_def *filtered_packed = nir_build_byte_permute_amd(b, packed_dw, nir_imm_int(b, 0), sel);
/* Horizontally add the packed bytes. */
sum = nir_sad_u8x4(b, filtered_packed, nir_imm_int(b, 0), nir_imm_int(b, 0));
} else if (num_lds_dwords == 2) {
/* Create selectors for the byte-permutes below. */
nir_ssa_def *dw0_selector = nir_build_lane_permute_16_amd(b, sel, nir_imm_int(b, 0x44443210), nir_imm_int(b, 0x4));
nir_ssa_def *dw1_selector = nir_build_lane_permute_16_amd(b, sel, nir_imm_int(b, 0x32100000), nir_imm_int(b, 0x4));
/* Broadcast the packed data we read from LDS (to the first 16 lanes, but we only care up to num_waves). */
nir_ssa_def *packed_dw0 = nir_build_lane_permute_16_amd(b, nir_unpack_64_2x32_split_x(b, packed_counts), nir_imm_int(b, 0), nir_imm_int(b, 0));
nir_ssa_def *packed_dw1 = nir_build_lane_permute_16_amd(b, nir_unpack_64_2x32_split_y(b, packed_counts), nir_imm_int(b, 0), nir_imm_int(b, 0));
/* Use byte-permute to filter out the bytes not needed by the current lane. */
nir_ssa_def *filtered_packed_dw0 = nir_build_byte_permute_amd(b, packed_dw0, nir_imm_int(b, 0), dw0_selector);
nir_ssa_def *filtered_packed_dw1 = nir_build_byte_permute_amd(b, packed_dw1, nir_imm_int(b, 0), dw1_selector);
/* Horizontally add the packed bytes. */
sum = nir_sad_u8x4(b, filtered_packed_dw0, nir_imm_int(b, 0), nir_imm_int(b, 0));
sum = nir_sad_u8x4(b, filtered_packed_dw1, nir_imm_int(b, 0), sum);
} else {
unreachable("Unimplemented NGG wave count");
}
nir_ssa_def *sum = summarize_repack(b, packed_counts, num_lds_dwords);
nir_ssa_def *wg_repacked_index_base = nir_build_read_invocation(b, sum, wave_id);
nir_ssa_def *wg_num_repacked_invocations = nir_build_read_invocation(b, sum, num_waves);
@ -265,9 +295,10 @@ pervertex_lds_addr(nir_builder *b, nir_ssa_def *vertex_idx, unsigned per_vtx_byt
static nir_ssa_def *
emit_pack_ngg_prim_exp_arg(nir_builder *b, unsigned num_vertices_per_primitives,
nir_ssa_def *vertex_indices[3], nir_ssa_def *is_null_prim)
nir_ssa_def *vertex_indices[3], nir_ssa_def *is_null_prim,
bool use_edgeflags)
{
nir_ssa_def *arg = b->shader->info.stage == MESA_SHADER_VERTEX
nir_ssa_def *arg = use_edgeflags
? nir_build_load_initial_edgeflags_amd(b)
: nir_imm_int(b, 0);
@ -289,9 +320,8 @@ emit_pack_ngg_prim_exp_arg(nir_builder *b, unsigned num_vertices_per_primitives,
static nir_ssa_def *
ngg_input_primitive_vertex_index(nir_builder *b, unsigned vertex)
{
/* TODO: This is RADV specific. We'll need to refactor RADV and/or RadeonSI to match. */
return nir_ubfe(b, nir_build_load_gs_vertex_offset_amd(b, .base = vertex / 2u * 2u),
nir_imm_int(b, (vertex % 2u) * 16u), nir_imm_int(b, 16u));
return nir_ubfe(b, nir_build_load_gs_vertex_offset_amd(b, .base = vertex / 2u),
nir_imm_int(b, (vertex & 1u) * 16u), nir_imm_int(b, 16u));
}
static nir_ssa_def *
@ -311,7 +341,7 @@ emit_ngg_nogs_prim_exp_arg(nir_builder *b, lower_ngg_nogs_state *st)
? ngg_input_primitive_vertex_index(b, 2)
: nir_imm_zero(b, 1, 32);
return emit_pack_ngg_prim_exp_arg(b, st->num_vertices_per_primitives, vtx_idx, NULL);
return emit_pack_ngg_prim_exp_arg(b, st->num_vertices_per_primitives, vtx_idx, NULL, st->use_edgeflags);
}
}
@ -532,6 +562,105 @@ remove_extra_pos_outputs(nir_shader *shader, lower_ngg_nogs_state *nogs_state)
nir_metadata_block_index | nir_metadata_dominance, &s);
}
static bool
remove_compacted_arg(lower_ngg_nogs_state *state, nir_builder *b, unsigned idx)
{
nir_instr *store_instr = state->compact_arg_stores[idx];
if (!store_instr)
return false;
/* Simply remove the store. */
nir_instr_remove(store_instr);
/* Find the intrinsic that overwrites the shader arguments,
* and change its corresponding source.
* This will cause NIR's DCE to recognize the load and its phis as dead.
*/
b->cursor = nir_before_instr(&state->overwrite_args->instr);
nir_ssa_def *undef_arg = nir_ssa_undef(b, 1, 32);
nir_ssa_def_rewrite_uses(state->overwrite_args->src[idx].ssa, undef_arg);
state->compact_arg_stores[idx] = NULL;
return true;
}
static bool
cleanup_culling_shader_after_dce(nir_shader *shader,
nir_function_impl *function_impl,
lower_ngg_nogs_state *state)
{
bool uses_vs_vertex_id = false;
bool uses_vs_instance_id = false;
bool uses_tes_u = false;
bool uses_tes_v = false;
bool uses_tes_rel_patch_id = false;
bool uses_tes_patch_id = false;
bool progress = false;
nir_builder b;
nir_builder_init(&b, function_impl);
nir_foreach_block_reverse_safe(block, function_impl) {
nir_foreach_instr_reverse_safe(instr, block) {
if (instr->type != nir_instr_type_intrinsic)
continue;
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
switch (intrin->intrinsic) {
case nir_intrinsic_alloc_vertices_and_primitives_amd:
goto cleanup_culling_shader_after_dce_done;
case nir_intrinsic_load_vertex_id:
case nir_intrinsic_load_vertex_id_zero_base:
uses_vs_vertex_id = true;
break;
case nir_intrinsic_load_instance_id:
uses_vs_instance_id = true;
break;
case nir_intrinsic_load_input:
if (state->instance_rate_inputs &
(1 << (nir_intrinsic_base(intrin) - VERT_ATTRIB_GENERIC0)))
uses_vs_instance_id = true;
else
uses_vs_vertex_id = true;
break;
case nir_intrinsic_load_tess_coord:
uses_tes_u = uses_tes_v = true;
break;
case nir_intrinsic_load_tess_rel_patch_id_amd:
uses_tes_rel_patch_id = true;
break;
case nir_intrinsic_load_primitive_id:
if (shader->info.stage == MESA_SHADER_TESS_EVAL)
uses_tes_patch_id = true;
break;
default:
break;
}
}
}
cleanup_culling_shader_after_dce_done:
if (shader->info.stage == MESA_SHADER_VERTEX) {
if (!uses_vs_vertex_id)
progress |= remove_compacted_arg(state, &b, 0);
if (!uses_vs_instance_id)
progress |= remove_compacted_arg(state, &b, 1);
} else if (shader->info.stage == MESA_SHADER_TESS_EVAL) {
if (!uses_tes_u)
progress |= remove_compacted_arg(state, &b, 0);
if (!uses_tes_v)
progress |= remove_compacted_arg(state, &b, 1);
if (!uses_tes_rel_patch_id)
progress |= remove_compacted_arg(state, &b, 2);
if (!uses_tes_patch_id)
progress |= remove_compacted_arg(state, &b, 3);
}
return progress;
}
/**
* Perform vertex compaction after culling.
*
@ -548,6 +677,9 @@ compact_vertices_after_culling(nir_builder *b,
nir_variable **gs_vtxaddr_vars,
nir_ssa_def *invocation_index,
nir_ssa_def *es_vertex_lds_addr,
nir_ssa_def *es_exporter_tid,
nir_ssa_def *num_live_vertices_in_workgroup,
nir_ssa_def *fully_culled,
unsigned ngg_scratch_lds_base_addr,
unsigned pervertex_lds_bytes,
unsigned max_exported_args)
@ -557,15 +689,7 @@ compact_vertices_after_culling(nir_builder *b,
nir_variable *position_value_var = nogs_state->position_value_var;
nir_variable *prim_exp_arg_var = nogs_state->prim_exp_arg_var;
nir_ssa_def *es_accepted = nir_load_var(b, es_accepted_var);
/* Repack the vertices that survived the culling. */
wg_repack_result rep = repack_invocations_in_workgroup(b, es_accepted, ngg_scratch_lds_base_addr,
nogs_state->max_num_waves, nogs_state->wave_size);
nir_ssa_def *num_live_vertices_in_workgroup = rep.num_repacked_invocations;
nir_ssa_def *es_exporter_tid = rep.repacked_invocation_index;
nir_if *if_es_accepted = nir_push_if(b, es_accepted);
nir_if *if_es_accepted = nir_push_if(b, nir_load_var(b, es_accepted_var));
{
nir_ssa_def *exporter_addr = pervertex_lds_addr(b, es_exporter_tid, pervertex_lds_bytes);
@ -579,25 +703,13 @@ compact_vertices_after_culling(nir_builder *b,
/* Store the current thread's repackable arguments to the exporter thread's LDS space */
for (unsigned i = 0; i < max_exported_args; ++i) {
nir_ssa_def *arg_val = nir_load_var(b, repacked_arg_vars[i]);
nir_build_store_shared(b, arg_val, exporter_addr, .base = lds_es_arg_0 + 4u * i, .align_mul = 4u, .write_mask = 0x1u);
nir_intrinsic_instr *store = nir_build_store_shared(b, arg_val, exporter_addr, .base = lds_es_arg_0 + 4u * i, .align_mul = 4u, .write_mask = 0x1u);
nogs_state->compact_arg_stores[i] = &store->instr;
}
}
nir_pop_if(b, if_es_accepted);
/* If all vertices are culled, set primitive count to 0 as well. */
nir_ssa_def *num_exported_prims = nir_build_load_workgroup_num_input_primitives_amd(b);
nir_ssa_def *fully_culled = nir_ieq_imm(b, num_live_vertices_in_workgroup, 0u);
num_exported_prims = nir_bcsel(b, fully_culled, nir_imm_int(b, 0u), num_exported_prims);
nir_if *if_wave_0 = nir_push_if(b, nir_ieq(b, nir_build_load_subgroup_id(b), nir_imm_int(b, 0)));
{
/* Tell the final vertex and primitive count to the HW.
* We do this here to mask some of the latency of the LDS.
*/
nir_build_alloc_vertices_and_primitives_amd(b, num_live_vertices_in_workgroup, num_exported_prims);
}
nir_pop_if(b, if_wave_0);
/* TODO: Consider adding a shortcut exit.
* Waves that have no vertices and primitives left can s_endpgm right here.
*/
@ -618,6 +730,12 @@ compact_vertices_after_culling(nir_builder *b,
nir_store_var(b, repacked_arg_vars[i], arg_val, 0x1u);
}
}
nir_push_else(b, if_packed_es_thread);
{
nir_store_var(b, position_value_var, nir_ssa_undef(b, 4, 32), 0xfu);
for (unsigned i = 0; i < max_exported_args; ++i)
nir_store_var(b, repacked_arg_vars[i], nir_ssa_undef(b, 1, 32), 0x1u);
}
nir_pop_if(b, if_packed_es_thread);
nir_if *if_gs_accepted = nir_push_if(b, nir_load_var(b, gs_accepted_var));
@ -631,7 +749,7 @@ compact_vertices_after_culling(nir_builder *b,
exporter_vtx_indices[v] = nir_u2u32(b, exporter_vtx_idx);
}
nir_ssa_def *prim_exp_arg = emit_pack_ngg_prim_exp_arg(b, 3, exporter_vtx_indices, NULL);
nir_ssa_def *prim_exp_arg = emit_pack_ngg_prim_exp_arg(b, 3, exporter_vtx_indices, NULL, nogs_state->use_edgeflags);
nir_store_var(b, prim_exp_arg_var, prim_exp_arg, 0x1u);
}
nir_pop_if(b, if_gs_accepted);
@ -735,34 +853,27 @@ analyze_shader_before_culling(nir_shader *shader, lower_ngg_nogs_state *nogs_sta
static void
save_reusable_variables(nir_builder *b, lower_ngg_nogs_state *nogs_state)
{
ASSERTED int vec_ok = u_vector_init(&nogs_state->saved_uniforms, sizeof(saved_uniform), 4 * sizeof(saved_uniform));
ASSERTED int vec_ok = u_vector_init(&nogs_state->saved_uniforms, 4, sizeof(saved_uniform));
assert(vec_ok);
unsigned loop_depth = 0;
nir_foreach_block_safe(block, b->impl) {
/* Check whether we're in a loop. */
nir_cf_node *next_cf_node = nir_cf_node_next(&block->cf_node);
nir_cf_node *prev_cf_node = nir_cf_node_prev(&block->cf_node);
if (next_cf_node && next_cf_node->type == nir_cf_node_loop)
loop_depth++;
if (prev_cf_node && prev_cf_node->type == nir_cf_node_loop)
loop_depth--;
/* The following code doesn't make sense in loops, so just skip it then. */
if (loop_depth)
continue;
nir_block *block = nir_start_block(b->impl);
while (block) {
/* Process the instructions in the current block. */
nir_foreach_instr_safe(instr, block) {
/* Find instructions whose SSA definitions are used by both
* the top and bottom parts of the shader. In this case, it
* makes sense to try to reuse these from the top part.
* the top and bottom parts of the shader (before and after culling).
* Only in this case, it makes sense for the bottom part
* to try to reuse these from the top part.
*/
if ((instr->pass_flags & nggc_passflag_used_by_both) != nggc_passflag_used_by_both)
continue;
/* Determine if we can reuse the current SSA value.
* When vertex compaction is used, it is possible that the same shader invocation
* processes a different vertex in the top and bottom part of the shader.
* Therefore, we only reuse uniform values.
*/
nir_ssa_def *ssa = NULL;
switch (instr->type) {
case nir_instr_type_alu: {
nir_alu_instr *alu = nir_instr_as_alu(instr);
@ -796,6 +907,7 @@ save_reusable_variables(nir_builder *b, lower_ngg_nogs_state *nogs_state)
assert(ssa);
/* Determine a suitable type for the SSA value. */
enum glsl_base_type base_type = GLSL_TYPE_UINT;
switch (ssa->bit_size) {
case 8: base_type = GLSL_TYPE_UINT8; break;
@ -812,6 +924,10 @@ save_reusable_variables(nir_builder *b, lower_ngg_nogs_state *nogs_state)
saved_uniform *saved = (saved_uniform *) u_vector_add(&nogs_state->saved_uniforms);
assert(saved);
/* Create a new NIR variable where we store the reusable value.
* Then, we reload the variable and replace the uses of the value
* with the reloaded variable.
*/
saved->var = nir_local_variable_create(b->impl, t, NULL);
saved->ssa = ssa;
@ -822,6 +938,35 @@ save_reusable_variables(nir_builder *b, lower_ngg_nogs_state *nogs_state)
nir_ssa_def *reloaded = nir_load_var(b, saved->var);
nir_ssa_def_rewrite_uses_after(ssa, reloaded, reloaded->parent_instr);
}
/* Look at the next CF node. */
nir_cf_node *next_cf_node = nir_cf_node_next(&block->cf_node);
if (next_cf_node) {
/* It makes no sense to try to reuse things from within loops. */
bool next_is_loop = next_cf_node->type == nir_cf_node_loop;
/* Don't reuse if we're in divergent control flow.
*
* Thanks to vertex repacking, the same shader invocation may process a different vertex
* in the top and bottom part, and it's even possible that this different vertex was initially
* processed in a different wave. So the two parts may take a different divergent code path.
* Therefore, these variables in divergent control flow may stay undefined.
*
* Note that this problem doesn't exist if vertices are not repacked or if the
* workgroup only has a single wave.
*/
bool next_is_divergent_if =
next_cf_node->type == nir_cf_node_if &&
nir_cf_node_as_if(next_cf_node)->condition.ssa->divergent;
if (next_is_loop || next_is_divergent_if) {
block = nir_cf_node_cf_tree_next(next_cf_node);
continue;
}
}
/* Go to the next block. */
block = nir_block_cf_tree_next(block);
}
}
@ -846,8 +991,7 @@ apply_reusable_variables(nir_builder *b, lower_ngg_nogs_state *nogs_state)
/* When we found any of these intrinsics, it means
* we reached the top part and we must stop.
*/
if (intrin->intrinsic == nir_intrinsic_alloc_vertices_and_primitives_amd ||
intrin->intrinsic == nir_intrinsic_export_primitive_amd)
if (intrin->intrinsic == nir_intrinsic_alloc_vertices_and_primitives_amd)
goto done;
if (intrin->intrinsic != nir_intrinsic_store_deref)
@ -1045,10 +1189,31 @@ add_deferred_attribute_culling(nir_builder *b, nir_cf_list *original_extracted_c
}
nir_pop_if(b, if_es_thread);
nir_ssa_def *es_accepted = nir_load_var(b, es_accepted_var);
/* Repack the vertices that survived the culling. */
wg_repack_result rep = repack_invocations_in_workgroup(b, es_accepted, ngg_scratch_lds_base_addr,
nogs_state->max_num_waves, nogs_state->wave_size);
nir_ssa_def *num_live_vertices_in_workgroup = rep.num_repacked_invocations;
nir_ssa_def *es_exporter_tid = rep.repacked_invocation_index;
/* If all vertices are culled, set primitive count to 0 as well. */
nir_ssa_def *num_exported_prims = nir_build_load_workgroup_num_input_primitives_amd(b);
nir_ssa_def *fully_culled = nir_ieq_imm(b, num_live_vertices_in_workgroup, 0u);
num_exported_prims = nir_bcsel(b, fully_culled, nir_imm_int(b, 0u), num_exported_prims);
nir_if *if_wave_0 = nir_push_if(b, nir_ieq(b, nir_build_load_subgroup_id(b), nir_imm_int(b, 0)));
{
/* Tell the final vertex and primitive count to the HW. */
nir_build_alloc_vertices_and_primitives_amd(b, num_live_vertices_in_workgroup, num_exported_prims);
}
nir_pop_if(b, if_wave_0);
/* Vertex compaction. */
compact_vertices_after_culling(b, nogs_state,
repacked_arg_vars, gs_vtxaddr_vars,
invocation_index, es_vertex_lds_addr,
es_exporter_tid, num_live_vertices_in_workgroup, fully_culled,
ngg_scratch_lds_base_addr, pervertex_lds_bytes, max_exported_args);
}
nir_push_else(b, if_cull_en);
@ -1083,56 +1248,36 @@ add_deferred_attribute_culling(nir_builder *b, nir_cf_list *original_extracted_c
*/
if (b->shader->info.stage == MESA_SHADER_VERTEX)
nir_build_overwrite_vs_arguments_amd(b,
nir_load_var(b, repacked_arg_vars[0]), nir_load_var(b, repacked_arg_vars[1]));
nogs_state->overwrite_args =
nir_build_overwrite_vs_arguments_amd(b,
nir_load_var(b, repacked_arg_vars[0]), nir_load_var(b, repacked_arg_vars[1]));
else if (b->shader->info.stage == MESA_SHADER_TESS_EVAL)
nir_build_overwrite_tes_arguments_amd(b,
nir_load_var(b, repacked_arg_vars[0]), nir_load_var(b, repacked_arg_vars[1]),
nir_load_var(b, repacked_arg_vars[2]), nir_load_var(b, repacked_arg_vars[3]));
nogs_state->overwrite_args =
nir_build_overwrite_tes_arguments_amd(b,
nir_load_var(b, repacked_arg_vars[0]), nir_load_var(b, repacked_arg_vars[1]),
nir_load_var(b, repacked_arg_vars[2]), nir_load_var(b, repacked_arg_vars[3]));
else
unreachable("Should be VS or TES.");
}
static bool
can_use_deferred_attribute_culling(nir_shader *shader)
{
/* When the shader writes memory, it is difficult to guarantee correctness.
* Future work:
* - if only write-only SSBOs are used
* - if we can prove that non-position outputs don't rely on memory stores
* then may be okay to keep the memory stores in the 1st shader part, and delete them from the 2nd.
*/
if (shader->info.writes_memory)
return false;
/* When the shader relies on the subgroup invocation ID, we'd break it, because the ID changes after the culling.
* Future work: try to save this to LDS and reload, but it can still be broken in subtle ways.
*/
if (BITSET_TEST(shader->info.system_values_read, SYSTEM_VALUE_SUBGROUP_INVOCATION))
return false;
return true;
}
ac_nir_ngg_config
void
ac_nir_lower_ngg_nogs(nir_shader *shader,
unsigned max_num_es_vertices,
unsigned num_vertices_per_primitives,
unsigned max_workgroup_size,
unsigned wave_size,
bool consider_culling,
bool consider_passthrough,
bool can_cull,
bool early_prim_export,
bool passthrough,
bool export_prim_id,
bool provoking_vtx_last)
bool provoking_vtx_last,
bool use_edgeflags,
uint32_t instance_rate_inputs)
{
nir_function_impl *impl = nir_shader_get_entrypoint(shader);
assert(impl);
assert(max_num_es_vertices && max_workgroup_size && wave_size);
bool can_cull = consider_culling && (num_vertices_per_primitives == 3) &&
can_use_deferred_attribute_culling(shader);
bool passthrough = consider_passthrough && !can_cull &&
!(shader->info.stage == MESA_SHADER_VERTEX && export_prim_id);
assert(!(can_cull && passthrough));
nir_variable *position_value_var = nir_local_variable_create(impl, glsl_vec4_type(), "position_value");
nir_variable *prim_exp_arg_var = nir_local_variable_create(impl, glsl_uint_type(), "prim_exp_arg");
@ -1142,7 +1287,8 @@ ac_nir_lower_ngg_nogs(nir_shader *shader,
lower_ngg_nogs_state state = {
.passthrough = passthrough,
.export_prim_id = export_prim_id,
.early_prim_export = exec_list_is_singular(&impl->body),
.early_prim_export = early_prim_export,
.use_edgeflags = use_edgeflags,
.num_vertices_per_primitives = num_vertices_per_primitives,
.provoking_vtx_idx = provoking_vtx_last ? (num_vertices_per_primitives - 1) : 0,
.position_value_var = position_value_var,
@ -1152,15 +1298,13 @@ ac_nir_lower_ngg_nogs(nir_shader *shader,
.max_num_waves = DIV_ROUND_UP(max_workgroup_size, wave_size),
.max_es_num_vertices = max_num_es_vertices,
.wave_size = wave_size,
.instance_rate_inputs = instance_rate_inputs,
};
/* We need LDS space when VS needs to export the primitive ID. */
if (shader->info.stage == MESA_SHADER_VERTEX && export_prim_id)
state.total_lds_bytes = max_num_es_vertices * 4u;
/* The shader only needs this much LDS when culling is turned off. */
unsigned lds_bytes_if_culling_off = state.total_lds_bytes;
nir_builder builder;
nir_builder *b = &builder; /* This is to avoid the & */
nir_builder_init(b, impl);
@ -1267,20 +1411,12 @@ ac_nir_lower_ngg_nogs(nir_shader *shader,
NIR_PASS(progress, shader, nir_opt_undef);
NIR_PASS(progress, shader, nir_opt_dce);
NIR_PASS(progress, shader, nir_opt_dead_cf);
if (can_cull)
progress |= cleanup_culling_shader_after_dce(shader, b->impl, &state);
} while (progress);
shader->info.shared_size = state.total_lds_bytes;
ac_nir_ngg_config ret = {
.lds_bytes_if_culling_off = lds_bytes_if_culling_off,
.can_cull = can_cull,
.passthrough = passthrough,
.early_prim_export = state.early_prim_export,
.nggc_inputs_read_by_pos = state.inputs_needed_by_pos,
.nggc_inputs_read_by_others = state.inputs_needed_by_others,
};
return ret;
}
static nir_ssa_def *
@ -1568,7 +1704,7 @@ ngg_gs_export_primitives(nir_builder *b, nir_ssa_def *max_num_out_prims, nir_ssa
}
}
nir_ssa_def *arg = emit_pack_ngg_prim_exp_arg(b, s->num_vertices_per_primitive, vtx_indices, is_null_prim);
nir_ssa_def *arg = emit_pack_ngg_prim_exp_arg(b, s->num_vertices_per_primitive, vtx_indices, is_null_prim, false);
nir_build_export_primitive_amd(b, arg);
nir_pop_if(b, if_prim_export_thread);
}

12
mesa 3D driver/src/amd/common/ac_nir_lower_tess_io_to_mem.c
View File

@ -154,7 +154,8 @@ typedef struct {
} lower_tess_io_state;
static bool
match_mask(nir_intrinsic_instr *intrin,
match_mask(gl_shader_stage stage,
nir_intrinsic_instr *intrin,
uint64_t mask,
bool match_indirect)
{
@ -163,7 +164,8 @@ match_mask(nir_intrinsic_instr *intrin,
return match_indirect;
uint64_t slot = nir_intrinsic_io_semantics(intrin).location;
if (intrin->intrinsic != nir_intrinsic_load_per_vertex_input &&
if (stage == MESA_SHADER_TESS_CTRL &&
intrin->intrinsic != nir_intrinsic_load_per_vertex_input &&
intrin->intrinsic != nir_intrinsic_store_per_vertex_output)
slot -= VARYING_SLOT_PATCH0;
@ -178,7 +180,7 @@ tcs_output_needs_vmem(nir_intrinsic_instr *intrin,
? st->tes_inputs_read
: st->tes_patch_inputs_read;
return match_mask(intrin, mask, true);
return match_mask(MESA_SHADER_TESS_CTRL, intrin, mask, true);
}
static bool
@ -189,7 +191,7 @@ tcs_output_needs_lds(nir_intrinsic_instr *intrin,
? shader->info.outputs_read
: shader->info.patch_outputs_read;
return match_mask(intrin, mask, true);
return match_mask(MESA_SHADER_TESS_CTRL, intrin, mask, true);
}
static bool
@ -208,7 +210,7 @@ lower_ls_output_store(nir_builder *b,
lower_tess_io_state *st = (lower_tess_io_state *) state;
/* If this is a temp-only TCS input, we don't need to use shared memory at all. */
if (match_mask(intrin, st->tcs_temp_only_inputs, false))
if (match_mask(MESA_SHADER_VERTEX, intrin, st->tcs_temp_only_inputs, false))
return false;
b->cursor = nir_before_instr(instr);

29
mesa 3D driver/src/amd/common/ac_rgp.c
View File

@ -61,10 +61,6 @@
enum sqtt_version
{
SQTT_VERSION_NONE = 0x0,
SQTT_VERSION_1_0 = 0x1,
SQTT_VERSION_1_1 = 0x2,
SQTT_VERSION_2_0 = 0x3, /* GFX6 */
SQTT_VERSION_2_1 = 0x4, /* GFX7 */
SQTT_VERSION_2_2 = 0x5, /* GFX8 */
SQTT_VERSION_2_3 = 0x6, /* GFX9 */
SQTT_VERSION_2_4 = 0x7 /* GFX10+ */
@ -368,10 +364,6 @@ static_assert(sizeof(struct sqtt_file_chunk_asic_info) == 720,
static enum sqtt_gfxip_level ac_chip_class_to_sqtt_gfxip_level(enum chip_class chip_class)
{
switch (chip_class) {
case GFX6:
return SQTT_GFXIP_LEVEL_GFXIP_6;
case GFX7:
return SQTT_GFXIP_LEVEL_GFXIP_7;
case GFX8:
return SQTT_GFXIP_LEVEL_GFXIP_8;
case GFX9:
@ -454,13 +446,20 @@ static void ac_sqtt_fill_asic_info(struct radeon_info *rad_info,
if (rad_info->chip_class < GFX9)
chunk->flags |= SQTT_FILE_CHUNK_ASIC_INFO_FLAG_SC_PACKER_NUMBERING;
/* Only FIJI and GFX9+ support PS1 events. */
if (rad_info->family == CHIP_FIJI || rad_info->chip_class >= GFX9)
/* Only GFX9+ support PS1 events. */
if (rad_info->chip_class >= GFX9)
chunk->flags |= SQTT_FILE_CHUNK_ASIC_INFO_FLAG_PS1_EVENT_TOKENS_ENABLED;
chunk->trace_shader_core_clock = rad_info->max_shader_clock * 1000000;
chunk->trace_memory_clock = rad_info->max_memory_clock * 1000000;
/* RGP gets very confused if these clocks are 0. The 1 GHz clocks are not necessarily correct,
* but the resulting traces are at least somewhat useful. */
if (!chunk->trace_shader_core_clock)
chunk->trace_shader_core_clock = 1e9;
if (!chunk->trace_memory_clock)
chunk->trace_memory_clock = 1e9;
chunk->device_id = rad_info->pci_id;
chunk->device_revision_id = rad_info->pci_rev_id;
chunk->vgprs_per_simd = rad_info->num_physical_wave64_vgprs_per_simd * (has_wave32 ? 2 : 1);
@ -725,10 +724,6 @@ static_assert(sizeof(struct sqtt_file_chunk_sqtt_desc) == 32,
static enum sqtt_version ac_chip_class_to_sqtt_version(enum chip_class chip_class)
{
switch (chip_class) {
case GFX6:
return SQTT_VERSION_2_0;
case GFX7:
return SQTT_VERSION_2_1;
case GFX8:
return SQTT_VERSION_2_2;
case GFX9:
@ -790,8 +785,6 @@ static void ac_sqtt_fill_sqtt_data(struct sqtt_file_chunk_sqtt_data *chunk, int3
*/
enum elf_gfxip_level
{
EF_AMDGPU_MACH_AMDGCN_GFX600 = 0x020,
EF_AMDGPU_MACH_AMDGCN_GFX700 = 0x022,
EF_AMDGPU_MACH_AMDGCN_GFX801 = 0x028,
EF_AMDGPU_MACH_AMDGCN_GFX900 = 0x02c,
EF_AMDGPU_MACH_AMDGCN_GFX1010 = 0x033,
@ -801,10 +794,6 @@ enum elf_gfxip_level
static enum elf_gfxip_level ac_chip_class_to_elf_gfxip_level(enum chip_class chip_class)
{
switch (chip_class) {
case GFX6:
return EF_AMDGPU_MACH_AMDGCN_GFX600;
case GFX7:
return EF_AMDGPU_MACH_AMDGCN_GFX700;
case GFX8:
return EF_AMDGPU_MACH_AMDGCN_GFX801;
case GFX9:

2
mesa 3D driver/src/amd/common/ac_rgp.h
View File

@ -52,6 +52,8 @@ struct rgp_shader_data {
uint8_t *code;
uint32_t vgpr_count;
uint32_t sgpr_count;
uint32_t scratch_memory_size;
uint32_t wavefront_size;
uint64_t base_address;
uint32_t elf_symbol_offset;
uint32_t hw_stage;

10
mesa 3D driver/src/amd/common/ac_rgp_elf_object_pack.c
View File

@ -149,7 +149,7 @@ ac_rgp_write_msgpack(FILE *output,
ac_msgpack_add_fixstr(&msgpack, hw_stage_string[
record->shader_data[i].hw_stage]);
ac_msgpack_add_fixmap_op(&msgpack, 3);
ac_msgpack_add_fixmap_op(&msgpack, 5);
ac_msgpack_add_fixstr(&msgpack, ".entry_point");
ac_msgpack_add_fixstr(&msgpack, hw_stage_symbol_string[
record->shader_data[i].hw_stage]);
@ -161,6 +161,14 @@ ac_rgp_write_msgpack(FILE *output,
ac_msgpack_add_fixstr(&msgpack, ".vgpr_count");
ac_msgpack_add_uint(&msgpack,
record->shader_data[i].vgpr_count);
ac_msgpack_add_fixstr(&msgpack, ".scratch_memory_size");
ac_msgpack_add_uint(&msgpack,
record->shader_data[i].scratch_memory_size);
ac_msgpack_add_fixstr(&msgpack, ".wavefront_size");
ac_msgpack_add_uint(&msgpack,
record->shader_data[i].wavefront_size);
}
/* 5 */

4
mesa 3D driver/src/amd/common/ac_shader_args.h
View File

@ -107,7 +107,7 @@ struct ac_shader_args {
struct ac_arg es2gs_offset; /* separate legacy ES */
struct ac_arg gs2vs_offset; /* legacy GS */
struct ac_arg gs_wave_id; /* legacy GS */
struct ac_arg gs_vtx_offset[6]; /* separate legacy GS */
struct ac_arg gs_vtx_offset[6]; /* GFX6-8: [0-5], GFX9+: [0-2] packed */
struct ac_arg gs_prim_id;
struct ac_arg gs_invocation_id;
@ -139,10 +139,10 @@ struct ac_shader_args {
/* Vulkan only */
struct ac_arg push_constants;
struct ac_arg inline_push_consts[AC_MAX_INLINE_PUSH_CONSTS];
unsigned num_inline_push_consts;
unsigned base_inline_push_consts;
struct ac_arg view_index;
struct ac_arg sbt_descriptors;
struct ac_arg ray_launch_size;
};
void ac_add_arg(struct ac_shader_args *info, enum ac_arg_regfile regfile, unsigned registers,

70
mesa 3D driver/src/amd/common/ac_shader_util.c
View File

@ -25,6 +25,7 @@
#include "ac_gpu_info.h"
#include "sid.h"
#include "u_math.h"
#include <assert.h>
#include <stdlib.h>
@ -511,3 +512,72 @@ void ac_compute_late_alloc(const struct radeon_info *info, bool ngg, bool ngg_cu
else /* VS */
*late_alloc_wave64 = MIN2(*late_alloc_wave64, G_00B11C_LIMIT(~0u));
}
unsigned ac_compute_cs_workgroup_size(uint16_t sizes[3], bool variable, unsigned max)
{
if (variable)
return max;
return sizes[0] * sizes[1] * sizes[2];
}
unsigned ac_compute_lshs_workgroup_size(enum chip_class chip_class, gl_shader_stage stage,
unsigned tess_num_patches,
unsigned tess_patch_in_vtx,
unsigned tess_patch_out_vtx)
{
/* When tessellation is used, API VS runs on HW LS, API TCS runs on HW HS.
* These two HW stages are merged on GFX9+.
*/
bool merged_shaders = chip_class >= GFX9;
unsigned ls_workgroup_size = tess_num_patches * tess_patch_in_vtx;
unsigned hs_workgroup_size = tess_num_patches * tess_patch_out_vtx;
if (merged_shaders)
return MAX2(ls_workgroup_size, hs_workgroup_size);
else if (stage == MESA_SHADER_VERTEX)
return ls_workgroup_size;
else if (stage == MESA_SHADER_TESS_CTRL)
return hs_workgroup_size;
else
unreachable("invalid LSHS shader stage");
}
unsigned ac_compute_esgs_workgroup_size(enum chip_class chip_class, unsigned wave_size,
unsigned es_verts, unsigned gs_inst_prims)
{
/* ESGS may operate in workgroups if on-chip GS (LDS rings) are enabled.
*
* GFX6: Not possible in the HW.
* GFX7-8 (unmerged): possible in the HW, but not implemented in Mesa.
* GFX9+ (merged): implemented in Mesa.
*/
if (chip_class <= GFX8)
return wave_size;
unsigned workgroup_size = MAX2(es_verts, gs_inst_prims);
return CLAMP(workgroup_size, 1, 256);
}
unsigned ac_compute_ngg_workgroup_size(unsigned es_verts, unsigned gs_inst_prims,
unsigned max_vtx_out, unsigned prim_amp_factor)
{
/* NGG always operates in workgroups.
*
* For API VS/TES/GS:
* - 1 invocation per input vertex
* - 1 invocation per input primitive
*
* The same invocation can process both an input vertex and primitive,
* however 1 invocation can only output up to 1 vertex and 1 primitive.
*/
unsigned max_vtx_in = es_verts < 256 ? es_verts : 3 * gs_inst_prims;
unsigned max_prim_in = gs_inst_prims;
unsigned max_prim_out = gs_inst_prims * prim_amp_factor;
unsigned workgroup_size = MAX4(max_vtx_in, max_vtx_out, max_prim_in, max_prim_out);
return CLAMP(workgroup_size, 1, 256);
}

14
mesa 3D driver/src/amd/common/ac_shader_util.h
View File

@ -27,6 +27,7 @@
#include "ac_binary.h"
#include "amd_family.h"
#include "compiler/nir/nir.h"
#include "compiler/shader_enums.h"
#include <stdbool.h>
#include <stdint.h>
@ -104,6 +105,19 @@ void ac_choose_spi_color_formats(unsigned format, unsigned swap, unsigned ntype,
void ac_compute_late_alloc(const struct radeon_info *info, bool ngg, bool ngg_culling,
bool uses_scratch, unsigned *late_alloc_wave64, unsigned *cu_mask);
unsigned ac_compute_cs_workgroup_size(uint16_t sizes[3], bool variable, unsigned max);
unsigned ac_compute_lshs_workgroup_size(enum chip_class chip_class, gl_shader_stage stage,
unsigned tess_num_patches,
unsigned tess_patch_in_vtx,
unsigned tess_patch_out_vtx);
unsigned ac_compute_esgs_workgroup_size(enum chip_class chip_class, unsigned wave_size,
unsigned es_verts, unsigned gs_inst_prims);
unsigned ac_compute_ngg_workgroup_size(unsigned es_verts, unsigned gs_inst_prims,
unsigned max_vtx_out, unsigned prim_amp_factor);
#ifdef __cplusplus
}
#endif

149
mesa 3D driver/src/amd/common/ac_surface.c
View File

@ -105,6 +105,57 @@ bool ac_modifier_has_dcc_retile(uint64_t modifier)
return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC_RETILE, modifier);
}
bool ac_modifier_supports_dcc_image_stores(uint64_t modifier)
{
if (!ac_modifier_has_dcc(modifier))
return false;
return (!AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier) &&
AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier) &&
AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier) == AMD_FMT_MOD_DCC_BLOCK_128B) ||
(AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && /* gfx10.3 */
AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier) &&
AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier) &&
AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier) == AMD_FMT_MOD_DCC_BLOCK_64B);
}
bool ac_surface_supports_dcc_image_stores(enum chip_class chip_class,
const struct radeon_surf *surf)
{
/* DCC image stores is only available for GFX10+. */
if (chip_class < GFX10)
return false;
/* DCC image stores support the following settings:
* - INDEPENDENT_64B_BLOCKS = 0
* - INDEPENDENT_128B_BLOCKS = 1
* - MAX_COMPRESSED_BLOCK_SIZE = 128B
* - MAX_UNCOMPRESSED_BLOCK_SIZE = 256B (always used)
*
* gfx10.3 also supports the following setting:
* - INDEPENDENT_64B_BLOCKS = 1
* - INDEPENDENT_128B_BLOCKS = 1
* - MAX_COMPRESSED_BLOCK_SIZE = 64B
* - MAX_UNCOMPRESSED_BLOCK_SIZE = 256B (always used)
*
* The compressor only looks at MAX_COMPRESSED_BLOCK_SIZE to determine
* the INDEPENDENT_xx_BLOCKS settings. 128B implies INDEP_128B, while 64B
* implies INDEP_64B && INDEP_128B.
*
* The same limitations apply to SDMA compressed stores because
* SDMA uses the same DCC codec.
*/
return (!surf->u.gfx9.color.dcc.independent_64B_blocks &&
surf->u.gfx9.color.dcc.independent_128B_blocks &&
surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_128B) ||
(chip_class >= GFX10_3 && /* gfx10.3 */
surf->u.gfx9.color.dcc.independent_64B_blocks &&
surf->u.gfx9.color.dcc.independent_128B_blocks &&
surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B);
}
static
AddrSwizzleMode ac_modifier_gfx9_swizzle_mode(uint64_t modifier)
{
@ -302,6 +353,19 @@ bool ac_get_supported_modifiers(const struct radeon_info *info,
AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B))
if (info->chip_class >= GFX10_3) {
if (info->max_render_backends == 1) {
ADD_MOD(AMD_FMT_MOD | common_dcc |
AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B))
}
ADD_MOD(AMD_FMT_MOD | common_dcc |
AMD_FMT_MOD_SET(DCC_RETILE, 1) |
AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B))
}
if (info->family == CHIP_NAVI12 || info->family == CHIP_NAVI14 || info->chip_class >= GFX10_3) {
bool independent_128b = info->chip_class >= GFX10_3;
@ -1402,12 +1466,47 @@ ASSERTED static bool is_dcc_supported_by_L2(const struct radeon_info *info,
/* 128B is recommended, but 64B can be set too if needed for 4K by DCN.
* Since there is no reason to ever disable 128B, require it.
* DCC image stores are always supported.
* If 64B is used, DCC image stores are unsupported.
*/
return surf->u.gfx9.color.dcc.independent_128B_blocks &&
surf->u.gfx9.color.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B;
}
static bool gfx10_DCN_requires_independent_64B_blocks(const struct radeon_info *info,
const struct ac_surf_config *config)
{
assert(info->chip_class >= GFX10);
/* Older kernels have buggy DAL. */
if (info->drm_minor <= 43)
return true;
/* For 4K, DCN requires INDEPENDENT_64B_BLOCKS = 1 and MAX_COMPRESSED_BLOCK_SIZE = 64B. */
return config->info.width > 2560 || config->info.height > 2560;
}
void ac_modifier_max_extent(const struct radeon_info *info,
uint64_t modifier, uint32_t *width, uint32_t *height)
{
if (ac_modifier_has_dcc(modifier)) {
bool independent_64B_blocks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier);
if (info->chip_class >= GFX10 && !independent_64B_blocks) {
/* For 4K, DCN requires INDEPENDENT_64B_BLOCKS = 1 and MAX_COMPRESSED_BLOCK_SIZE = 64B. */
*width = 2560;
*height = 2560;
} else {
/* DCC is not supported on surfaces above resolutions af 5760. */
*width = 5760;
*height = 5760;
}
} else {
/* Non-dcc modifiers */
*width = 16384;
*height = 16384;
}
}
static bool is_dcc_supported_by_DCN(const struct radeon_info *info,
const struct ac_surf_config *config,
const struct radeon_surf *surf, bool rb_aligned,
@ -1424,13 +1523,12 @@ static bool is_dcc_supported_by_DCN(const struct radeon_info *info,
if (info->use_display_dcc_unaligned && (rb_aligned || pipe_aligned))
return false;
/* Big resolutions don't support DCC. */
if (config->info.width > 5760 || config->info.height > 5760)
return false;
switch (info->chip_class) {
case GFX9:
/* Only support 64KB_S_X, so that we have only 1 variant of the retile shader. */
if (info->use_display_dcc_with_retile_blit &&
surf->u.gfx9.swizzle_mode != ADDR_SW_64KB_S_X)
return false;
/* There are more constraints, but we always set
* INDEPENDENT_64B_BLOCKS = 1 and MAX_COMPRESSED_BLOCK_SIZE = 64B,
* which always works.
@ -1440,17 +1538,11 @@ static bool is_dcc_supported_by_DCN(const struct radeon_info *info,
return true;
case GFX10:
case GFX10_3:
/* Only support 64KB_R_X, so that we have only 1 variant of the retile shader. */
if (info->use_display_dcc_with_retile_blit &&
surf->u.gfx9.swizzle_mode != ADDR_SW_64KB_R_X)
return false;
/* DCN requires INDEPENDENT_128B_BLOCKS = 0 only on Navi1x. */
if (info->chip_class == GFX10 && surf->u.gfx9.color.dcc.independent_128B_blocks)
return false;
/* For 4K, DCN requires INDEPENDENT_64B_BLOCKS = 1. */
return ((config->info.width <= 2560 && config->info.height <= 2560) ||
return (!gfx10_DCN_requires_independent_64B_blocks(info, config) ||
(surf->u.gfx9.color.dcc.independent_64B_blocks &&
surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B));
default:
@ -2038,14 +2130,17 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_
ac_modifier_fill_dcc_params(surf->modifier, surf, &AddrSurfInfoIn);
} else if (!AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.stencil) {
/* Optimal values for the L2 cache. */
if (info->chip_class == GFX9) {
surf->u.gfx9.color.dcc.independent_64B_blocks = 1;
surf->u.gfx9.color.dcc.independent_128B_blocks = 0;
surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
} else if (info->chip_class >= GFX10) {
surf->u.gfx9.color.dcc.independent_64B_blocks = 0;
surf->u.gfx9.color.dcc.independent_128B_blocks = 1;
surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
/* Don't change the DCC settings for imported buffers - they might differ. */
if (!(surf->flags & RADEON_SURF_IMPORTED)) {
if (info->chip_class == GFX9) {
surf->u.gfx9.color.dcc.independent_64B_blocks = 1;
surf->u.gfx9.color.dcc.independent_128B_blocks = 0;
surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
} else if (info->chip_class >= GFX10) {
surf->u.gfx9.color.dcc.independent_64B_blocks = 0;
surf->u.gfx9.color.dcc.independent_128B_blocks = 1;
surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
}
}
if (AddrSurfInfoIn.flags.display) {
@ -2062,7 +2157,9 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_
}
/* Adjust DCC settings to meet DCN requirements. */
if (info->use_display_dcc_unaligned || info->use_display_dcc_with_retile_blit) {
/* Don't change the DCC settings for imported buffers - they might differ. */
if (!(surf->flags & RADEON_SURF_IMPORTED) &&
(info->use_display_dcc_unaligned || info->use_display_dcc_with_retile_blit)) {
/* Only Navi12/14 support independent 64B blocks in L2,
* but without DCC image stores.
*/
@ -2072,7 +2169,13 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_
surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
}
if (info->chip_class >= GFX10_3) {
if ((info->chip_class >= GFX10_3 && info->family <= CHIP_YELLOW_CARP) ||
/* Newer chips will skip this when possible to get better performance.
* This is also possible for other gfx10.3 chips, but is disabled for
* interoperability between different Mesa versions.
*/
(info->family > CHIP_YELLOW_CARP &&
gfx10_DCN_requires_independent_64B_blocks(info, config))) {
surf->u.gfx9.color.dcc.independent_64B_blocks = 1;
surf->u.gfx9.color.dcc.independent_128B_blocks = 1;
surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;

6
mesa 3D driver/src/amd/common/ac_surface.h
View File

@ -454,6 +454,9 @@ bool ac_get_supported_modifiers(const struct radeon_info *info,
uint64_t *mods);
bool ac_modifier_has_dcc(uint64_t modifier);
bool ac_modifier_has_dcc_retile(uint64_t modifier);
bool ac_modifier_supports_dcc_image_stores(uint64_t modifier);
void ac_modifier_max_extent(const struct radeon_info *info,
uint64_t modifier, uint32_t *width, uint32_t *height);
unsigned ac_surface_get_nplanes(const struct radeon_surf *surf);
uint64_t ac_surface_get_plane_offset(enum chip_class chip_class,
@ -469,6 +472,9 @@ uint64_t ac_surface_get_plane_size(const struct radeon_surf *surf,
void ac_surface_print_info(FILE *out, const struct radeon_info *info,
const struct radeon_surf *surf);
bool ac_surface_supports_dcc_image_stores(enum chip_class chip_class,
const struct radeon_surf *surf);
#ifdef AC_SURFACE_INCLUDE_NIR
nir_ssa_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info *info,
unsigned bpe, struct gfx9_meta_equation *equation,

2
mesa 3D driver/src/amd/common/ac_surface_modifier_test.c
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@ -397,7 +397,7 @@ int main()
STATIC_ASSERT(sizeof(struct test_entry) == 64);
struct u_vector test_entries;
u_vector_init(&test_entries, sizeof(struct test_entry), 4096);
u_vector_init_pow2(&test_entries, 64, sizeof(struct test_entry));
for (unsigned i = 0; i < ARRAY_SIZE(testcases); ++i) {
struct radeon_info info = get_radeon_info(&testcases[i]);

10
mesa 3D driver/src/amd/compiler/README-ISA.md
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@ -113,6 +113,16 @@ Some instructions have a `_LEGACY` variant which implements "DX9 rules", in whic
the zero "wins" in multiplications, ie. `0.0*x` is always `0.0`. The VEGA ISA
mentions `V_MAC_LEGACY_F32` but this instruction is not really there on VEGA.
## `m0` with LDS instructions on Vega and newer
The Vega ISA doc (both the old one and the "7nm" one) claims that LDS instructions
use the `m0` register for address clamping like older GPUs, but this is not the case.
In reality, only the `_addtid` variants of LDS instructions use `m0` on Vega and
newer GPUs, so the relevant section of the RDNA ISA doc seems to apply.
LLVM also doesn't emit any initialization of `m0` for LDS instructions, and this
was also confirmed by AMD devs.
## RDNA L0, L1 cache and DLC, GLC bits
The old L1 cache was renamed to L0, and a new L1 cache was added to RDNA. The

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