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phase 14

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This commit is contained in:
Raziel K. Crowe 2022-04-02 17:34:24 +05:00
parent e8c95beb2b
commit b8247e41e7
974 changed files with 41055 additions and 17441 deletions
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3
arch/arm/Kbuild
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@ -9,3 +9,6 @@ obj-y += kernel/ mm/ common/
obj-y += probes/
obj-y += net/
obj-y += crypto/
# for cleaning
subdir- += boot

28
arch/arm/Kconfig
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@ -3,6 +3,7 @@ config ARM
bool
default y
select ARCH_32BIT_OFF_T
select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND
select ARCH_HAS_BINFMT_FLAT
select ARCH_HAS_DEBUG_VIRTUAL if MMU
select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
@ -64,11 +65,11 @@ config ARM
select GENERIC_PCI_IOMAP
select GENERIC_SCHED_CLOCK
select GENERIC_SMP_IDLE_THREAD
select HANDLE_DOMAIN_IRQ
select HARDIRQS_SW_RESEND
select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL
select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
select HAVE_ARCH_MMAP_RND_BITS if MMU
@ -82,6 +83,7 @@ config ARM
select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
select HAVE_CONTEXT_TRACKING
select HAVE_C_RECORDMCOUNT
select HAVE_BUILDTIME_MCOUNT_SORT
select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
select HAVE_DMA_CONTIGUOUS if MMU
select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
@ -91,8 +93,7 @@ config ARM
select HAVE_FAST_GUP if ARM_LPAE
select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
select HAVE_FUNCTION_TRACER if !XIP_KERNEL
select HAVE_FUTEX_CMPXCHG if FUTEX
select HAVE_FUNCTION_TRACER if !XIP_KERNEL && !(THUMB2_KERNEL && CC_IS_CLANG)
select HAVE_GCC_PLUGINS
select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
select HAVE_IRQ_TIME_ACCOUNTING
@ -126,6 +127,7 @@ config ARM
select PERF_USE_VMALLOC
select RTC_LIB
select SYS_SUPPORTS_APM_EMULATION
select THREAD_INFO_IN_TASK if CURRENT_POINTER_IN_TPIDRURO
select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M
# Above selects are sorted alphabetically; please add new ones
# according to that. Thanks.
@ -265,10 +267,12 @@ config PHYS_OFFSET
hex "Physical address of main memory" if MMU
depends on !ARM_PATCH_PHYS_VIRT
default DRAM_BASE if !MMU
default 0x00000000 if ARCH_FOOTBRIDGE
default 0x00000000 if ARCH_FOOTBRIDGE || ARCH_IXP4XX
default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
default 0x20000000 if ARCH_S5PV210
default 0xc0000000 if ARCH_SA1100
default 0x30000000 if ARCH_S3C24XX
default 0xa0000000 if ARCH_IOP32X || ARCH_PXA
default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100
default 0
help
Please provide the physical address corresponding to the
location of main memory in your system.
@ -348,7 +352,7 @@ config ARCH_EP93XX
select CLKSRC_MMIO
select CPU_ARM920T
select GPIOLIB
select HAVE_LEGACY_CLK
select COMMON_CLK
help
This enables support for the Cirrus EP93xx series of CPUs.
@ -433,6 +437,7 @@ config ARCH_PXA
config ARCH_RPC
bool "RiscPC"
depends on MMU
depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000
select ARCH_ACORN
select ARCH_MAY_HAVE_PC_FDC
select ARCH_SPARSEMEM_ENABLE
@ -475,8 +480,6 @@ config ARCH_S3C24XX
select GPIO_SAMSUNG
select GPIOLIB
select GENERIC_IRQ_MULTI_HANDLER
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C_RTC if RTC_CLASS
select NEED_MACH_IO_H
select S3C2410_WATCHDOG
select SAMSUNG_ATAGS
@ -1158,6 +1161,11 @@ config SMP_ON_UP
If you don't know what to do here, say Y.
config CURRENT_POINTER_IN_TPIDRURO
def_bool y
depends on SMP && CPU_32v6K && !CPU_V6
config ARM_CPU_TOPOLOGY
bool "Support cpu topology definition"
depends on SMP && CPU_V7
@ -1602,7 +1610,7 @@ config XEN
config STACKPROTECTOR_PER_TASK
bool "Use a unique stack canary value for each task"
depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
depends on GCC_PLUGINS && STACKPROTECTOR && THREAD_INFO_IN_TASK && !XIP_DEFLATED_DATA
select GCC_PLUGIN_ARM_SSP_PER_TASK
default y
help

13
arch/arm/Kconfig.debug
View File

@ -66,8 +66,6 @@ config UNWINDER_FRAME_POINTER
config UNWINDER_ARM
bool "ARM EABI stack unwinder"
depends on AEABI && !FUNCTION_GRAPH_TRACER
# https://github.com/ClangBuiltLinux/linux/issues/732
depends on !LD_IS_LLD || LLD_VERSION >= 110000
select ARM_UNWIND
help
This option enables stack unwinding support in the kernel
@ -81,6 +79,17 @@ endchoice
config ARM_UNWIND
bool
config BACKTRACE_VERBOSE
bool "Verbose backtrace"
depends on EXPERT
help
When the kernel produces a warning or oops, the kernel prints a
trace of the call chain. This option controls whether we include
the numeric addresses or only include the symbolic information.
In most cases, say N here, unless you are intending to debug the
kernel and have access to the kernel binary image.
config FRAME_POINTER
bool

13
arch/arm/Makefile
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@ -113,6 +113,10 @@ ifeq ($(CONFIG_CC_IS_CLANG),y)
CFLAGS_ABI += -meabi gnu
endif
ifeq ($(CONFIG_CURRENT_POINTER_IN_TPIDRURO),y)
CFLAGS_ABI += -mtp=cp15
endif
# Accept old syntax despite ".syntax unified"
AFLAGS_NOWARN :=$(call as-option,-Wa$(comma)-mno-warn-deprecated,-Wa$(comma)-W)
@ -273,11 +277,8 @@ ifeq ($(CONFIG_STACKPROTECTOR_PER_TASK),y)
prepare: stack_protector_prepare
stack_protector_prepare: prepare0
$(eval SSP_PLUGIN_CFLAGS := \
-fplugin-arg-arm_ssp_per_task_plugin-tso=$(shell \
awk '{if ($$2 == "THREAD_SZ_ORDER") print $$3;}'\
include/generated/asm-offsets.h) \
-fplugin-arg-arm_ssp_per_task_plugin-offset=$(shell \
awk '{if ($$2 == "TI_STACK_CANARY") print $$3;}'\
awk '{if ($$2 == "TSK_STACK_CANARY") print $$3;}'\
include/generated/asm-offsets.h))
$(eval KBUILD_CFLAGS += $(SSP_PLUGIN_CFLAGS))
$(eval GCC_PLUGINS_CFLAGS += $(SSP_PLUGIN_CFLAGS))
@ -317,10 +318,6 @@ ifeq ($(CONFIG_VDSO),y)
$(Q)$(MAKE) $(build)=arch/arm/vdso $@
endif
# We use MRPROPER_FILES and CLEAN_FILES now
archclean:
$(Q)$(MAKE) $(clean)=$(boot)
# My testing targets (bypasses dependencies)
bp:; $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/bootpImage

5
arch/arm/boot/compressed/.gitignore vendored
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@ -1,9 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
ashldi3.S
bswapsdi2.S
font.c
lib1funcs.S
hyp-stub.S
piggy_data
vmlinux
vmlinux.lds

41
arch/arm/boot/compressed/Makefile
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@ -13,7 +13,6 @@ ifeq ($(CONFIG_DEBUG_UNCOMPRESS),y)
OBJS += debug.o
AFLAGS_head.o += -DDEBUG
endif
FONTC = $(srctree)/lib/fonts/font_acorn_8x8.c
# string library code (-Os is enforced to keep it much smaller)
OBJS += string.o
@ -77,10 +76,10 @@ CPPFLAGS_vmlinux.lds += -DTEXT_OFFSET="$(TEXT_OFFSET)"
CPPFLAGS_vmlinux.lds += -DMALLOC_SIZE="$(MALLOC_SIZE)"
compress-$(CONFIG_KERNEL_GZIP) = gzip
compress-$(CONFIG_KERNEL_LZO) = lzo
compress-$(CONFIG_KERNEL_LZMA) = lzma
compress-$(CONFIG_KERNEL_XZ) = xzkern
compress-$(CONFIG_KERNEL_LZ4) = lz4
compress-$(CONFIG_KERNEL_LZO) = lzo_with_size
compress-$(CONFIG_KERNEL_LZMA) = lzma_with_size
compress-$(CONFIG_KERNEL_XZ) = xzkern_with_size
compress-$(CONFIG_KERNEL_LZ4) = lz4_with_size
libfdt_objs := fdt_rw.o fdt_ro.o fdt_wip.o fdt.o
@ -99,11 +98,8 @@ $(foreach o, $(libfdt_objs) atags_to_fdt.o fdt_check_mem_start.o, \
$(eval CFLAGS_$(o) := -I $(srctree)/scripts/dtc/libfdt -fno-stack-protector))
targets := vmlinux vmlinux.lds piggy_data piggy.o \
lib1funcs.o ashldi3.o bswapsdi2.o \
head.o $(OBJS)
clean-files += lib1funcs.S ashldi3.S bswapsdi2.S hyp-stub.S
KBUILD_CFLAGS += -DDISABLE_BRANCH_PROFILING
ccflags-y := -fpic $(call cc-option,-mno-single-pic-base,) -fno-builtin \
@ -134,23 +130,7 @@ endif
# Next argument is a linker script
LDFLAGS_vmlinux += -T
# For __aeabi_uidivmod
lib1funcs = $(obj)/lib1funcs.o
$(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S
$(call cmd,shipped)
# For __aeabi_llsl
ashldi3 = $(obj)/ashldi3.o
$(obj)/ashldi3.S: $(srctree)/arch/$(SRCARCH)/lib/ashldi3.S
$(call cmd,shipped)
# For __bswapsi2, __bswapdi2
bswapsdi2 = $(obj)/bswapsdi2.o
$(obj)/bswapsdi2.S: $(srctree)/arch/$(SRCARCH)/lib/bswapsdi2.S
$(call cmd,shipped)
OBJS += lib1funcs.o ashldi3.o bswapsdi2.o
# We need to prevent any GOTOFF relocs being used with references
# to symbols in the .bss section since we cannot relocate them
@ -175,8 +155,8 @@ fi
efi-obj-$(CONFIG_EFI_STUB) := $(objtree)/drivers/firmware/efi/libstub/lib.a
$(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.o \
$(addprefix $(obj)/, $(OBJS)) $(lib1funcs) $(ashldi3) \
$(bswapsdi2) $(efi-obj-y) FORCE
$(addprefix $(obj)/, $(OBJS)) \
$(efi-obj-y) FORCE
@$(check_for_multiple_zreladdr)
$(call if_changed,ld)
@$(check_for_bad_syms)
@ -187,11 +167,4 @@ $(obj)/piggy_data: $(obj)/../Image FORCE
$(obj)/piggy.o: $(obj)/piggy_data
CFLAGS_font.o := -Dstatic=
$(obj)/font.c: $(FONTC)
$(call cmd,shipped)
AFLAGS_hyp-stub.o := -Wa,-march=armv7-a
$(obj)/hyp-stub.S: $(srctree)/arch/$(SRCARCH)/kernel/hyp-stub.S
$(call cmd,shipped)

3
arch/arm/boot/compressed/ashldi3.S Normal file
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@ -0,0 +1,3 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* For __aeabi_llsl */
#include "../../lib/ashldi3.S"

3
arch/arm/boot/compressed/bswapsdi2.S Normal file
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@ -0,0 +1,3 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* For __bswapsi2, __bswapdi2 */
#include "../../lib/bswapsdi2.S"

48
arch/arm/boot/compressed/fdt_check_mem_start.c
View File

@ -55,16 +55,17 @@ static uint64_t get_val(const fdt32_t *cells, uint32_t ncells)
* DTB, and, if out-of-range, replace it by the real start address.
* To preserve backwards compatibility (systems reserving a block of memory
* at the start of physical memory, kdump, ...), the traditional method is
* always used if it yields a valid address.
* used if it yields a valid address, unless the "linux,usable-memory-range"
* property is present.
*
* Return value: start address of physical memory to use
*/
uint32_t fdt_check_mem_start(uint32_t mem_start, const void *fdt)
{
uint32_t addr_cells, size_cells, base;
uint32_t addr_cells, size_cells, usable_base, base;
uint32_t fdt_mem_start = 0xffffffff;
const fdt32_t *reg, *endp;
uint64_t size, end;
const fdt32_t *usable, *reg, *endp;
uint64_t size, usable_end, end;
const char *type;
int offset, len;
@ -80,6 +81,27 @@ uint32_t fdt_check_mem_start(uint32_t mem_start, const void *fdt)
if (addr_cells > 2 || size_cells > 2)
return mem_start;
/*
* Usable memory in case of a crash dump kernel
* This property describes a limitation: memory within this range is
* only valid when also described through another mechanism
*/
usable = get_prop(fdt, "/chosen", "linux,usable-memory-range",
(addr_cells + size_cells) * sizeof(fdt32_t));
if (usable) {
size = get_val(usable + addr_cells, size_cells);
if (!size)
return mem_start;
if (addr_cells > 1 && fdt32_ld(usable)) {
/* Outside 32-bit address space */
return mem_start;
}
usable_base = fdt32_ld(usable + addr_cells - 1);
usable_end = usable_base + size;
}
/* Walk all memory nodes and regions */
for (offset = fdt_next_node(fdt, -1, NULL); offset >= 0;
offset = fdt_next_node(fdt, offset, NULL)) {
@ -107,7 +129,20 @@ uint32_t fdt_check_mem_start(uint32_t mem_start, const void *fdt)
base = fdt32_ld(reg + addr_cells - 1);
end = base + size;
if (mem_start >= base && mem_start < end) {
if (usable) {
/*
* Clip to usable range, which takes precedence
* over mem_start
*/
if (base < usable_base)
base = usable_base;
if (end > usable_end)
end = usable_end;
if (end <= base)
continue;
} else if (mem_start >= base && mem_start < end) {
/* Calculated address is valid, use it */
return mem_start;
}
@ -123,7 +158,8 @@ uint32_t fdt_check_mem_start(uint32_t mem_start, const void *fdt)
}
/*
* The calculated address is not usable.
* The calculated address is not usable, or was overridden by the
* "linux,usable-memory-range" property.
* Use the lowest usable physical memory address from the DTB instead,
* and make sure this is a multiple of 2 MiB for phys/virt patching.
*/

2
arch/arm/boot/compressed/font.c Normal file
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@ -0,0 +1,2 @@
// SPDX-License-Identifier: GPL-2.0-only
#include "../../../../lib/fonts/font_acorn_8x8.c"

2
arch/arm/boot/compressed/hyp-stub.S Normal file
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@ -0,0 +1,2 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include "../../kernel/hyp-stub.S"

3
arch/arm/boot/compressed/lib1funcs.S Normal file
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@ -0,0 +1,3 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* For __aeabi_uidivmod */
#include "../../lib/lib1funcs.S"

1
arch/arm/boot/compressed/string.c
View File

@ -5,6 +5,7 @@
* Small subset of simple string routines
*/
#define __NO_FORTIFY
#include <linux/string.h>
/*

63
arch/arm/boot/dts/Makefile
View File

@ -45,6 +45,7 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
usb_a9263.dtb \
at91-foxg20.dtb \
at91-kizbox.dtb \
at91-lmu5000.dtb \
at91sam9g20ek.dtb \
at91sam9g20ek_2mmc.dtb \
tny_a9g20.dtb \
@ -60,6 +61,7 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
at91-kizboxmini-base.dtb \
at91-kizboxmini-mb.dtb \
at91-kizboxmini-rd.dtb \
at91-q5xr5.dtb \
at91-smartkiz.dtb \
at91-wb45n.dtb \
at91sam9g15ek.dtb \
@ -79,6 +81,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \
at91-sama5d2_icp.dtb \
at91-sama5d2_ptc_ek.dtb \
at91-sama5d2_xplained.dtb \
at91-sama5d3_ksz9477_evb.dtb \
at91-sama5d3_xplained.dtb \
at91-dvk_som60.dtb \
at91-gatwick.dtb \
@ -112,6 +115,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \
bcm2837-rpi-cm3-io3.dtb \
bcm2711-rpi-400.dtb \
bcm2711-rpi-4-b.dtb \
bcm2711-rpi-cm4-io.dtb \
bcm2835-rpi-zero.dtb \
bcm2835-rpi-zero-w.dtb
dtb-$(CONFIG_ARCH_BCM_5301X) += \
@ -137,6 +141,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm4709-netgear-r7000.dtb \
bcm4709-netgear-r8000.dtb \
bcm4709-tplink-archer-c9-v1.dtb \
bcm47094-asus-rt-ac88u.dtb \
bcm47094-dlink-dir-885l.dtb \
bcm47094-linksys-panamera.dtb \
bcm47094-luxul-abr-4500.dtb \
@ -177,6 +182,12 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \
bcm958525xmc.dtb \
bcm958622hr.dtb \
bcm958623hr.dtb \
bcm958625-meraki-mx64.dtb \
bcm958625-meraki-mx64-a0.dtb \
bcm958625-meraki-mx64w.dtb \
bcm958625-meraki-mx64w-a0.dtb \
bcm958625-meraki-mx65.dtb \
bcm958625-meraki-mx65w.dtb \
bcm958625hr.dtb \
bcm988312hr.dtb \
bcm958625k.dtb
@ -239,9 +250,11 @@ dtb-$(CONFIG_ARCH_GEMINI) += \
gemini-dlink-dir-685.dtb \
gemini-dlink-dns-313.dtb \
gemini-nas4220b.dtb \
gemini-ns2502.dtb \
gemini-rut1xx.dtb \
gemini-sl93512r.dtb \
gemini-sq201.dtb \
gemini-ssi1328.dtb \
gemini-wbd111.dtb \
gemini-wbd222.dtb
dtb-$(CONFIG_ARCH_HI3xxx) += \
@ -271,12 +284,14 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \
intel-ixp46x-ixdp465.dtb \
intel-ixp42x-adi-coyote.dtb \
intel-ixp42x-ixdpg425.dtb \
intel-ixp42x-goramo-multilink.dtb \
intel-ixp42x-iomega-nas100d.dtb \
intel-ixp42x-dlink-dsm-g600.dtb \
intel-ixp42x-gateworks-gw2348.dtb \
intel-ixp43x-gateworks-gw2358.dtb \
intel-ixp42x-netgear-wg302v2.dtb \
intel-ixp42x-arcom-vulcan.dtb
intel-ixp42x-arcom-vulcan.dtb \
intel-ixp42x-gateway-7001.dtb
dtb-$(CONFIG_ARCH_KEYSTONE) += \
keystone-k2hk-evm.dtb \
keystone-k2l-evm.dtb \
@ -491,6 +506,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-icore-rqs.dtb \
imx6dl-lanmcu.dtb \
imx6dl-mamoj.dtb \
imx6dl-mba6a.dtb \
imx6dl-mba6b.dtb \
imx6dl-nit6xlite.dtb \
imx6dl-nitrogen6x.dtb \
imx6dl-phytec-mira-rdk-nand.dtb \
@ -592,6 +609,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-kp-tpc.dtb \
imx6q-logicpd.dtb \
imx6q-marsboard.dtb \
imx6q-mba6a.dtb \
imx6q-mba6b.dtb \
imx6q-mccmon6.dtb \
imx6q-nitrogen6x.dtb \
imx6q-nitrogen6_max.dtb \
@ -636,7 +655,9 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-wandboard.dtb \
imx6q-wandboard-revb1.dtb \
imx6q-wandboard-revd1.dtb \
imx6q-yapp4-crux.dtb \
imx6q-zii-rdu2.dtb \
imx6qp-mba6b.dtb \
imx6qp-nitrogen6_max.dtb \
imx6qp-nitrogen6_som2.dtb \
imx6qp-phytec-mira-rdk-nand.dtb \
@ -649,16 +670,19 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6qp-tx6qp-8137-mb7.dtb \
imx6qp-vicutp.dtb \
imx6qp-wandboard-revd1.dtb \
imx6qp-yapp4-crux-plus.dtb \
imx6qp-zii-rdu2.dtb \
imx6s-dhcom-drc02.dtb
dtb-$(CONFIG_SOC_IMX6SL) += \
imx6sl-evk.dtb \
imx6sl-tolino-shine2hd.dtb \
imx6sl-tolino-shine3.dtb \
imx6sl-tolino-vision5.dtb \
imx6sl-warp.dtb
dtb-$(CONFIG_SOC_IMX6SLL) += \
imx6sll-evk.dtb \
imx6sll-kobo-clarahd.dtb
imx6sll-kobo-clarahd.dtb \
imx6sll-kobo-librah2o.dtb
dtb-$(CONFIG_SOC_IMX6SX) += \
imx6sx-nitrogen6sx.dtb \
imx6sx-sabreauto.dtb \
@ -691,14 +715,17 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
imx6ull-14x14-evk.dtb \
imx6ull-colibri-emmc-eval-v3.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-colibri-wifi-eval-v3.dtb \
imx6ull-jozacp.dtb \
imx6ull-myir-mys-6ulx-eval.dtb \
imx6ull-opos6uldev.dtb \
imx6ull-phytec-segin-ff-rdk-nand.dtb \
imx6ull-phytec-segin-ff-rdk-emmc.dtb \
imx6ull-phytec-segin-lc-rdk-nand.dtb \
imx6ulz-14x14-evk.dtb
imx6ulz-14x14-evk.dtb \
imx6ulz-bsh-smm-m2.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-cl-som-imx7.dtb \
imx7d-colibri-aster.dtb \
@ -960,6 +987,8 @@ dtb-$(CONFIG_ARCH_OXNAS) += \
ox810se-wd-mbwe.dtb \
ox820-cloudengines-pogoplug-series-3.dtb
dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8016-sbc.dtb \
qcom-apq8026-lg-lenok.dtb \
qcom-apq8060-dragonboard.dtb \
qcom-apq8064-cm-qs600.dtb \
qcom-apq8064-ifc6410.dtb \
@ -980,6 +1009,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq8064-rb3011.dtb \
qcom-msm8226-samsung-s3ve3g.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8916-samsung-serranove.dtb \
qcom-msm8960-cdp.dtb \
qcom-msm8974-fairphone-fp2.dtb \
qcom-msm8974-lge-nexus5-hammerhead.dtb \
@ -990,7 +1020,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-mdm9615-wp8548-mangoh-green.dtb \
qcom-sdx55-mtp.dtb \
qcom-sdx55-t55.dtb \
qcom-sdx55-telit-fn980-tlb.dtb
qcom-sdx55-telit-fn980-tlb.dtb \
qcom-sdx65-mtp.dtb
dtb-$(CONFIG_ARCH_RDA) += \
rda8810pl-orangepi-2g-iot.dtb \
rda8810pl-orangepi-i96.dtb
@ -1096,6 +1127,7 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
s5pv210-torbreck.dtb
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
socfpga_arria10_mercury_aa1.dtb \
socfpga_arria10_socdk_nand.dtb \
socfpga_arria10_socdk_qspi.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
@ -1134,6 +1166,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32h743i-eval.dtb \
stm32h743i-disco.dtb \
stm32h750i-art-pi.dtb \
stm32mp135f-dk.dtb \
stm32mp153c-dhcom-drc02.dtb \
stm32mp157a-avenger96.dtb \
stm32mp157a-dhcor-avenger96.dtb \
@ -1142,6 +1175,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
stm32mp157a-icore-stm32mp1-ctouch2.dtb \
stm32mp157a-icore-stm32mp1-ctouch2-of10.dtb \
stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
stm32mp157a-stinger96.dtb \
stm32mp157c-dhcom-pdk2.dtb \
@ -1306,6 +1340,7 @@ dtb-$(CONFIG_MACH_SUNIV) += \
suniv-f1c100s-licheepi-nano.dtb
dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
tegra20-acer-a500-picasso.dtb \
tegra20-asus-tf101.dtb \
tegra20-harmony.dtb \
tegra20-colibri-eval-v3.dtb \
tegra20-colibri-iris.dtb \
@ -1322,12 +1357,18 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \
tegra30-asus-nexus7-grouper-PM269.dtb \
tegra30-asus-nexus7-grouper-E1565.dtb \
tegra30-asus-nexus7-tilapia-E1565.dtb \
tegra30-asus-tf201.dtb \
tegra30-asus-tf300t.dtb \
tegra30-asus-tf300tg.dtb \
tegra30-asus-tf700t.dtb \
tegra30-beaver.dtb \
tegra30-cardhu-a02.dtb \
tegra30-cardhu-a04.dtb \
tegra30-colibri-eval-v3.dtb \
tegra30-ouya.dtb
tegra30-ouya.dtb \
tegra30-pegatron-chagall.dtb
dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \
tegra114-asus-tf701t.dtb \
tegra114-dalmore.dtb \
tegra114-roth.dtb \
tegra114-tn7.dtb
@ -1336,6 +1377,7 @@ dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \
tegra124-apalis-v1.2-eval.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
tegra124-nyan-big-fhd.dtb \
tegra124-nyan-blaze.dtb \
tegra124-venice2.dtb
dtb-$(CONFIG_ARCH_U8500) += \
@ -1408,6 +1450,7 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \
dtb-$(CONFIG_MACH_ARMADA_375) += \
armada-375-db.dtb
dtb-$(CONFIG_MACH_ARMADA_38X) += \
armada-381-netgear-gs110emx.dtb \
armada-382-rd-ac3x-48g4x2xl.dtb \
armada-385-atl-x530.dtb\
armada-385-clearfog-gtr-s4.dtb \
@ -1458,6 +1501,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt2701-evb.dtb \
mt6580-evbp1.dtb \
mt6589-aquaris5.dtb \
mt6589-fairphone-fp1.dtb \
mt6592-evb.dtb \
mt7623a-rfb-emmc.dtb \
mt7623a-rfb-nand.dtb \
@ -1483,6 +1527,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-arm-stardragon4800-rep2.dtb \
aspeed-bmc-asrock-e3c246d4i.dtb \
aspeed-bmc-bytedance-g220a.dtb \
aspeed-bmc-facebook-bletchley.dtb \
aspeed-bmc-facebook-cloudripper.dtb \
aspeed-bmc-facebook-cmm.dtb \
aspeed-bmc-facebook-elbert.dtb \
@ -1518,7 +1563,13 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-opp-zaius.dtb \
aspeed-bmc-portwell-neptune.dtb \
aspeed-bmc-quanta-q71l.dtb \
aspeed-bmc-supermicro-x11spi.dtb
aspeed-bmc-supermicro-x11spi.dtb \
aspeed-bmc-inventec-transformers.dtb \
aspeed-bmc-tyan-s7106.dtb \
aspeed-bmc-tyan-s8036.dtb \
aspeed-bmc-vegman-n110.dtb \
aspeed-bmc-vegman-rx20.dtb \
aspeed-bmc-vegman-sx20.dtb
targets += dtbs dtbs_install
targets += $(dtb-y)

1
arch/arm/boot/dts/am335x-bone-common.dtsi
View File

@ -399,6 +399,7 @@ &sham {
&rtc {
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
system-power-controller;
};
&pruss_tm {

4
arch/arm/boot/dts/am335x-boneblack-common.dtsi
View File

@ -22,10 +22,6 @@ &mmc2 {
non-removable;
};
&rtc {
system-power-controller;
};
/ {
memory@80000000 {
device_type = "memory";

2
arch/arm/boot/dts/am335x-boneblue.dts
View File

@ -341,7 +341,7 @@ i2c-gate {
#address-cells = <1>;
#size-cells = <0>;
ax8975@c {
compatible = "ak,ak8975";
compatible = "asahi-kasei,ak8975";
reg = <0x0c>;
};
};

4
arch/arm/boot/dts/am335x-icev2.dts
View File

@ -512,3 +512,7 @@ ethphy1: ethernet-phy@3 {
&pruss_tm {
status = "okay";
};
&rtc {
system-power-controller;
};

2
arch/arm/boot/dts/am335x-osd3358-sm-red.dts
View File

@ -84,7 +84,7 @@ i2c-gate {
#address-cells = <1>;
#size-cells = <0>;
ax8975@c {
compatible = "ak,ak8975";
compatible = "asahi-kasei,ak8975";
reg = <0x0c>;
};
};

1
arch/arm/boot/dts/am335x-pocketbeagle.dts
View File

@ -205,6 +205,7 @@ &gpio3 {
&am33xx_pinmux {
compatible = "pinconf-single";
pinctrl-names = "default";
pinctrl-0 = < &P2_03_gpio &P1_34_gpio &P2_19_gpio &P2_24_gpio

8
arch/arm/boot/dts/am437x-gp-evm.dts
View File

@ -775,6 +775,14 @@ adc {
};
};
&magadc {
status = "okay";
adc {
ti,adc-channels = <0 1 2 3 4 5 6 7>;
};
};
&ecap0 {
status = "okay";
pinctrl-names = "default";

31
arch/arm/boot/dts/am437x-l4.dtsi
View File

@ -2378,11 +2378,38 @@ hdq: hdq@0 {
};
target-module@4c000 { /* 0x4834c000, ap 114 72.0 */
compatible = "ti,sysc";
status = "disabled";
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x4c000 0x4>,
<0x4c010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
clocks = <&l3s_clkctrl AM4_L3S_ADC1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4c000 0x2000>;
magadc: magadc@0 {
compatible = "ti,am4372-magadc";
reg = <0x0 0x2000>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&adc_mag_fck>;
clock-names = "fck";
dmas = <&edma 54 0>, <&edma 55 0>;
dma-names = "fifo0", "fifo1";
status = "disabled";
mag {
compatible = "ti,am4372-mag";
};
adc {
#io-channel-cells = <1>;
compatible ="ti,am4372-adc";
};
};
};
target-module@80000 { /* 0x48380000, ap 123 42.0 */

7
arch/arm/boot/dts/am43xx-clocks.dtsi
View File

@ -444,6 +444,13 @@ wdt1_fck: wdt1_fck@422c {
reg = <0x422c>;
};
adc_mag_fck: adc_mag_fck@424c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&dpll_per_m2_ck>;
reg = <0x424c>;
};
l3_gclk: l3_gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";

42
arch/arm/boot/dts/arm-realview-eb.dtsi
View File

@ -198,96 +198,112 @@ fpga {
syscon: syscon@10000000 {
compatible = "arm,realview-eb-syscon", "syscon", "simple-mfd";
reg = <0x10000000 0x1000>;
ranges = <0x0 0x10000000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
led@08.0 {
led@8,0 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x01>;
label = "versatile:0";
linux,default-trigger = "heartbeat";
default-state = "on";
};
led@08.1 {
led@8,1 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x02>;
label = "versatile:1";
linux,default-trigger = "mmc0";
default-state = "off";
};
led@08.2 {
led@8,2 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x04>;
label = "versatile:2";
linux,default-trigger = "cpu0";
default-state = "off";
};
led@08.3 {
led@8,3 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x08>;
label = "versatile:3";
default-state = "off";
};
led@08.4 {
led@8,4 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x10>;
label = "versatile:4";
default-state = "off";
};
led@08.5 {
led@8,5 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x20>;
label = "versatile:5";
default-state = "off";
};
led@08.6 {
led@8,6 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x40>;
label = "versatile:6";
default-state = "off";
};
led@08.7 {
led@8,7 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x80>;
label = "versatile:7";
default-state = "off";
};
oscclk0: osc0@0c {
oscclk0: clock-controller@c {
compatible = "arm,syscon-icst307";
reg = <0x0c 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x0C>;
clocks = <&xtal24mhz>;
};
oscclk1: osc1@10 {
oscclk1: clock-controller@10 {
compatible = "arm,syscon-icst307";
reg = <0x10 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x10>;
clocks = <&xtal24mhz>;
};
oscclk2: osc2@14 {
oscclk2: clock-controller@14 {
compatible = "arm,syscon-icst307";
reg = <0x14 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x14>;
clocks = <&xtal24mhz>;
};
oscclk3: osc3@18 {
oscclk3: clock-controller@18 {
compatible = "arm,syscon-icst307";
reg = <0x18 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x18>;
clocks = <&xtal24mhz>;
};
oscclk4: osc4@1c {
oscclk4: clock-controller@1c {
compatible = "arm,syscon-icst307";
reg = <0x1c 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x1c>;

42
arch/arm/boot/dts/arm-realview-pb1176.dts
View File

@ -216,96 +216,112 @@ soc {
syscon: syscon@10000000 {
compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd";
reg = <0x10000000 0x1000>;
ranges = <0x0 0x10000000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
led@08.0 {
led@8,0 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x01>;
label = "versatile:0";
linux,default-trigger = "heartbeat";
default-state = "on";
};
led@08.1 {
led@8,1 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x02>;
label = "versatile:1";
linux,default-trigger = "mmc0";
default-state = "off";
};
led@08.2 {
led@8,2 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x04>;
label = "versatile:2";
linux,default-trigger = "cpu0";
default-state = "off";
};
led@08.3 {
led@8,3 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x08>;
label = "versatile:3";
default-state = "off";
};
led@08.4 {
led@8,4 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x10>;
label = "versatile:4";
default-state = "off";
};
led@08.5 {
led@8,5 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x20>;
label = "versatile:5";
default-state = "off";
};
led@08.6 {
led@8,6 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x40>;
label = "versatile:6";
default-state = "off";
};
led@08.7 {
led@8,7 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x80>;
label = "versatile:7";
default-state = "off";
};
oscclk0: osc0@0c {
oscclk0: clock-controller@c {
compatible = "arm,syscon-icst307";
reg = <0x0c 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x0C>;
clocks = <&xtal24mhz>;
};
oscclk1: osc1@10 {
oscclk1: clock-controller@10 {
compatible = "arm,syscon-icst307";
reg = <0x10 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x10>;
clocks = <&xtal24mhz>;
};
oscclk2: osc2@14 {
oscclk2: clock-controller@14 {
compatible = "arm,syscon-icst307";
reg = <0x14 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x14>;
clocks = <&xtal24mhz>;
};
oscclk3: osc3@18 {
oscclk3: clock-controller@18 {
compatible = "arm,syscon-icst307";
reg = <0x18 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x18>;
clocks = <&xtal24mhz>;
};
oscclk4: osc4@1c {
oscclk4: clock-controller@1c {
compatible = "arm,syscon-icst307";
reg = <0x1c 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x1c>;

48
arch/arm/boot/dts/arm-realview-pb11mp.dts
View File

@ -303,114 +303,132 @@ soc {
pb11mp_syscon: syscon@10000000 {
compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd";
reg = <0x10000000 0x1000>;
ranges = <0x0 0x10000000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
led@08.0 {
led@8,0 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x01>;
label = "versatile:0";
linux,default-trigger = "heartbeat";
default-state = "on";
};
led@08.1 {
led@8,1 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x02>;
label = "versatile:1";
linux,default-trigger = "mmc0";
default-state = "off";
};
led@08.2 {
led@8,2 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x04>;
label = "versatile:2";
linux,default-trigger = "cpu0";
default-state = "off";
};
led@08.3 {
led@8,3 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x08>;
label = "versatile:3";
linux,default-trigger = "cpu1";
default-state = "off";
};
led@08.4 {
led@8,4 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x10>;
label = "versatile:4";
linux,default-trigger = "cpu2";
default-state = "off";
};
led@08.5 {
led@8,5 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x20>;
label = "versatile:5";
linux,default-trigger = "cpu3";
default-state = "off";
};
led@08.6 {
led@8,6 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x40>;
label = "versatile:6";
default-state = "off";
};
led@08.7 {
led@8,7 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x80>;
label = "versatile:7";
default-state = "off";
};
oscclk0: osc0@0c {
oscclk0: clock-controller@c {
compatible = "arm,syscon-icst307";
reg = <0x0c 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x0C>;
clocks = <&xtal24mhz>;
};
oscclk1: osc1@10 {
oscclk1: clock-controller@10 {
compatible = "arm,syscon-icst307";
reg = <0x10 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x10>;
clocks = <&xtal24mhz>;
};
oscclk2: osc2@14 {
oscclk2: clock-controller@14 {
compatible = "arm,syscon-icst307";
reg = <0x14 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x14>;
clocks = <&xtal24mhz>;
};
oscclk3: osc3@18 {
oscclk3: clock-controller@18 {
compatible = "arm,syscon-icst307";
reg = <0x18 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x18>;
clocks = <&xtal24mhz>;
};
oscclk4: osc4@1c {
oscclk4: clock-controller@1c {
compatible = "arm,syscon-icst307";
reg = <0x1c 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x1c>;
clocks = <&xtal24mhz>;
};
oscclk5: osc5@d4 {
oscclk5: clock-controller@d4 {
compatible = "arm,syscon-icst307";
reg = <0xd4 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0xd4>;
clocks = <&xtal24mhz>;
};
oscclk6: osc6@d8 {
oscclk6: clock-controller@d8 {
compatible = "arm,syscon-icst307";
reg = <0xd8 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0xd8>;

42
arch/arm/boot/dts/arm-realview-pbx.dtsi
View File

@ -220,96 +220,112 @@ soc: soc {
syscon: syscon@10000000 {
compatible = "arm,realview-pbx-syscon", "syscon", "simple-mfd";
reg = <0x10000000 0x1000>;
ranges = <0x0 0x10000000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
led@08.0 {
led@8,0 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x01>;
label = "versatile:0";
linux,default-trigger = "heartbeat";
default-state = "on";
};
led@08.1 {
led@8,1 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x02>;
label = "versatile:1";
linux,default-trigger = "mmc0";
default-state = "off";
};
led@08.2 {
led@8,2 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x04>;
label = "versatile:2";
linux,default-trigger = "cpu0";
default-state = "off";
};
led@08.3 {
led@8,3 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x08>;
label = "versatile:3";
default-state = "off";
};
led@08.4 {
led@8,4 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x10>;
label = "versatile:4";
default-state = "off";
};
led@08.5 {
led@8,5 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x20>;
label = "versatile:5";
default-state = "off";
};
led@08.6 {
led@8,6 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x40>;
label = "versatile:6";
default-state = "off";
};
led@08.7 {
led@8,7 {
compatible = "register-bit-led";
reg = <0x08 0x04>;
offset = <0x08>;
mask = <0x80>;
label = "versatile:7";
default-state = "off";
};
oscclk0: osc0@0c {
oscclk0: clock-controller@c {
compatible = "arm,syscon-icst307";
reg = <0x0c 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x0C>;
clocks = <&xtal24mhz>;
};
oscclk1: osc1@10 {
oscclk1: clock-controller@10 {
compatible = "arm,syscon-icst307";
reg = <0x10 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x10>;
clocks = <&xtal24mhz>;
};
oscclk2: osc2@14 {
oscclk2: clock-controller@14 {
compatible = "arm,syscon-icst307";
reg = <0x14 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x14>;
clocks = <&xtal24mhz>;
};
oscclk3: osc3@18 {
oscclk3: clock-controller@18 {
compatible = "arm,syscon-icst307";
reg = <0x18 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x18>;
clocks = <&xtal24mhz>;
};
oscclk4: osc4@1c {
oscclk4: clock-controller@1c {
compatible = "arm,syscon-icst307";
reg = <0x1c 0x04>;
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x1c>;

295
arch/arm/boot/dts/armada-381-netgear-gs110emx.dts Normal file
View File

@ -0,0 +1,295 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, Marcel Ziswiler <marcel@ziswiler.com> */
/dts-v1/;
#include "armada-385.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Netgear GS110EMX";
compatible = "netgear,gs110emx", "marvell,armada380";
aliases {
/* So that mvebu u-boot can update the MAC addresses */
ethernet1 = &eth0;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&front_button_pins>;
pinctrl-names = "default";
factory_default {
label = "Factory Default";
gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000>; /* 128 MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
internal-regs {
rtc@a3800 {
/*
* If the rtc doesn't work, run "date reset"
* twice in u-boot.
*/
status = "okay";
};
};
};
};
&eth0 {
/* ethernet@70000 */
bm,pool-long = <0>;
bm,pool-short = <1>;
buffer-manager = <&bm>;
phy-mode = "rgmii-id";
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
status = "okay";
fixed-link {
full-duplex;
pause;
speed = <1000>;
};
};
&mdio {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
status = "okay";
switch@0 {
compatible = "marvell,mv88e6190";
#address-cells = <1>;
#interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&switch_interrupt_pins>;
pinctrl-names = "default";
#size-cells = <0>;
reg = <0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy1: switch0phy1@1 {
reg = <0x1>;
};
switch0phy2: switch0phy2@2 {
reg = <0x2>;
};
switch0phy3: switch0phy3@3 {
reg = <0x3>;
};
switch0phy4: switch0phy4@4 {
reg = <0x4>;
};
switch0phy5: switch0phy5@5 {
reg = <0x5>;
};
switch0phy6: switch0phy6@6 {
reg = <0x6>;
};
switch0phy7: switch0phy7@7 {
reg = <0x7>;
};
switch0phy8: switch0phy8@8 {
reg = <0x8>;
};
};
mdio-external {
compatible = "marvell,mv88e6xxx-mdio-external";
#address-cells = <1>;
#size-cells = <0>;
phy1: ethernet-phy@b {
reg = <0xb>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy2: ethernet-phy@c {
reg = <0xc>;
compatible = "ethernet-phy-ieee802.3-c45";
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
ethernet = <&eth0>;
label = "cpu";
reg = <0>;
fixed-link {
full-duplex;
pause;
speed = <1000>;
};
};
port@1 {
label = "lan1";
phy-handle = <&switch0phy1>;
reg = <1>;
};
port@2 {
label = "lan2";
phy-handle = <&switch0phy2>;
reg = <2>;
};
port@3 {
label = "lan3";
phy-handle = <&switch0phy3>;
reg = <3>;
};
port@4 {
label = "lan4";
phy-handle = <&switch0phy4>;
reg = <4>;
};
port@5 {
label = "lan5";
phy-handle = <&switch0phy5>;
reg = <5>;
};
port@6 {
label = "lan6";
phy-handle = <&switch0phy6>;
reg = <6>;
};
port@7 {
label = "lan7";
phy-handle = <&switch0phy7>;
reg = <7>;
};
port@8 {
label = "lan8";
phy-handle = <&switch0phy8>;
reg = <8>;
};
port@9 {
/* 88X3310P external phy */
label = "lan9";
phy-handle = <&phy1>;
phy-mode = "xaui";
reg = <9>;
};
port@a {
/* 88X3310P external phy */
label = "lan10";
phy-handle = <&phy2>;
phy-mode = "xaui";
reg = <0xa>;
};
};
};
};
&pinctrl {
front_button_pins: front-button-pins {
marvell,pins = "mpp38";
marvell,function = "gpio";
};
switch_interrupt_pins: switch-interrupt-pins {
marvell,pins = "mpp39";
marvell,function = "gpio";
};
};
&spi0 {
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <3000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "boot";
read-only;
reg = <0x00000000 0x00100000>;
};
partition@100000 {
label = "env";
reg = <0x00100000 0x00010000>;
};
partition@200000 {
label = "rsv";
reg = <0x00110000 0x00010000>;
};
partition@300000 {
label = "image0";
reg = <0x00120000 0x00900000>;
};
partition@400000 {
label = "config";
reg = <0x00a20000 0x00300000>;
};
partition@480000 {
label = "debug";
reg = <0x00d20000 0x002e0000>;
};
};
};
};
&uart0 {
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
status = "okay";
};

5
arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts
View File

@ -159,6 +159,11 @@ &i2c2 {
//24LC128 EEPROM
&i2c3 {
status = "okay";
eeprom@50 {
compatible = "atmel,24c256";
reg = <0x50>;
pagesize = <64>;
};
};
//P0 Power regulators

288
arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts
View File

@ -7,6 +7,50 @@ / {
model = "Ampere Mt. Jade BMC";
compatible = "ampere,mtjade-bmc", "aspeed,ast2500";
aliases {
/*
* i2c bus 50-57 assigned to NVMe slot 0-7
*/
i2c50 = &nvmeslot_0;
i2c51 = &nvmeslot_1;
i2c52 = &nvmeslot_2;
i2c53 = &nvmeslot_3;
i2c54 = &nvmeslot_4;
i2c55 = &nvmeslot_5;
i2c56 = &nvmeslot_6;
i2c57 = &nvmeslot_7;
/*
* i2c bus 60-67 assigned to NVMe slot 8-15
*/
i2c60 = &nvmeslot_8;
i2c61 = &nvmeslot_9;
i2c62 = &nvmeslot_10;
i2c63 = &nvmeslot_11;
i2c64 = &nvmeslot_12;
i2c65 = &nvmeslot_13;
i2c66 = &nvmeslot_14;
i2c67 = &nvmeslot_15;
/*
* i2c bus 70-77 assigned to NVMe slot 16-23
*/
i2c70 = &nvmeslot_16;
i2c71 = &nvmeslot_17;
i2c72 = &nvmeslot_18;
i2c73 = &nvmeslot_19;
i2c74 = &nvmeslot_20;
i2c75 = &nvmeslot_21;
i2c76 = &nvmeslot_22;
i2c77 = &nvmeslot_23;
/*
* i2c bus 80-81 assigned to NVMe M2 slot 0-1
*/
i2c80 = &nvme_m2_0;
i2c81 = &nvme_m2_1;
};
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200 earlycon";
@ -86,6 +130,18 @@ S0_cpu_fault {
linux,code = <ASPEED_GPIO(J, 1)>;
};
S0_scp_auth_fail {
label = "S0_SCP_AUTH_FAIL";
gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(J, 2)>;
};
S1_scp_auth_fail {
label = "S1_SCP_AUTH_FAIL";
gpios = <&gpio ASPEED_GPIO(Z, 5) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(Z, 5)>;
};
S1_overtemp {
label = "S1_OVERTEMP";
gpios = <&gpio ASPEED_GPIO(Z, 6) GPIO_ACTIVE_LOW>;
@ -318,6 +374,15 @@ flash@0 {
m25p,fast-read;
label = "pnor";
/* spi-max-frequency = <100000000>; */
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
uefi@400000 {
reg = <0x400000 0x1C00000>;
label = "pnor-uefi";
};
};
};
};
@ -433,6 +498,220 @@ rtc@51 {
&i2c5 {
status = "okay";
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
i2c-mux-idle-disconnect;
nvmeslot_0_7: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
};
};
i2c-mux@71 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x71>;
i2c-mux-idle-disconnect;
nvmeslot_8_15: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4>;
};
nvmeslot_16_23: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
};
};
i2c-mux@72 {
compatible = "nxp,pca9545";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x72>;
i2c-mux-idle-disconnect;
nvme_m2_0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
};
nvme_m2_1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>;
};
};
};
&nvmeslot_0_7 {
status = "okay";
i2c-mux@75 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x75>;
i2c-mux-idle-disconnect;
nvmeslot_0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
};
nvmeslot_1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>;
};
nvmeslot_2: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
};
nvmeslot_3: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
};
nvmeslot_4: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4>;
};
nvmeslot_5: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x5>;
};
nvmeslot_6: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x6>;
};
nvmeslot_7: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x7>;
};
};
};
&nvmeslot_8_15 {
status = "okay";
i2c-mux@75 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x75>;
i2c-mux-idle-disconnect;
nvmeslot_8: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
};
nvmeslot_9: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>;
};
nvmeslot_10: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
};
nvmeslot_11: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
};
nvmeslot_12: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4>;
};
nvmeslot_13: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x5>;
};
nvmeslot_14: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x6>;
};
nvmeslot_15: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x7>;
};
};
};
&nvmeslot_16_23 {
status = "okay";
i2c-mux@75 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x75>;
i2c-mux-idle-disconnect;
nvmeslot_16: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
};
nvmeslot_17: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>;
};
nvmeslot_18: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
};
nvmeslot_19: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
};
nvmeslot_20: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4>;
};
nvmeslot_21: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x5>;
};
nvmeslot_22: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x6>;
};
nvmeslot_23: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x7>;
};
};
};
&i2c6 {
@ -590,7 +869,7 @@ &gpio {
/*Q0-Q7*/ "","","","","","UID_BUTTON","","",
/*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN",
"OCP_MAIN_PWREN","RESET_BUTTON","","",
/*S0-S7*/ "","","","","","","","",
/*S0-S7*/ "","","","","RTC_BAT_SEN_EN","","","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "","","","","","","","",
@ -604,4 +883,11 @@ &gpio {
"S1_BMC_DDR_ADR","","","","",
/*AC0-AC7*/ "SYS_PWR_GD","","","","","BMC_READY","SLAVE_PRESENT_L",
"BMC_OCP_PG";
i2c4_o_en {
gpio-hog;
gpios = <ASPEED_GPIO(Y, 2) GPIO_ACTIVE_HIGH>;
output-high;
line-name = "BMC_I2C4_O_EN";
};
};

12
arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts
View File

@ -260,6 +260,13 @@ flash@0 {
spi-max-frequency = <50000000>;
#include "openbmc-flash-layout-64.dtsi"
};
flash@1 {
status = "okay";
label = "alt-bmc";
m25p,fast-read;
spi-max-frequency = <50000000>;
#include "openbmc-flash-layout-64-alt.dtsi"
};
};
&spi1 {
@ -278,6 +285,11 @@ &adc {
status = "okay";
};
&wdt2 {
status = "okay";
aspeed,alt-boot;
};
&gpio {
status = "okay";
gpio-line-names =

756
arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts Normal file
View File

@ -0,0 +1,756 @@
// SPDX-License-Identifier: GPL-2.0+
// Copyright (c) 2021 Facebook Inc.
/dts-v1/;
#include "aspeed-g6.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
#include <dt-bindings/usb/pd.h>
/ {
model = "Facebook Bletchley BMC";
compatible = "facebook,bletchley-bmc", "aspeed,ast2600";
aliases {
serial4 = &uart5;
};
chosen {
bootargs = "console=ttyS4,57600n8";
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
<&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>,
<&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>,
<&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>;
};
spi_gpio: spi-gpio {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
gpio-sck = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
gpio-mosi = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
gpio-miso = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>;
num-chipselects = <1>;
cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>;
tpmdev@0 {
compatible = "tcg,tpm_tis-spi";
spi-max-frequency = <33000000>;
reg = <0>;
};
};
switchphy: ethernet-phy@0 {
// Fixed link
};
leds {
compatible = "gpio-leds";
sys_log_id {
retain-state-shutdown;
default-state = "keep";
gpios = <&front_leds 0 GPIO_ACTIVE_HIGH>;
};
fan0_blue {
retain-state-shutdown;
default-state = "on";
gpios = <&fan_ioexp 8 GPIO_ACTIVE_HIGH>;
};
fan1_blue {
retain-state-shutdown;
default-state = "on";
gpios = <&fan_ioexp 9 GPIO_ACTIVE_HIGH>;
};
fan2_blue {
retain-state-shutdown;
default-state = "on";
gpios = <&fan_ioexp 10 GPIO_ACTIVE_HIGH>;
};
fan3_blue {
retain-state-shutdown;
default-state = "on";
gpios = <&fan_ioexp 11 GPIO_ACTIVE_HIGH>;
};
fan0_amber {
retain-state-shutdown;
default-state = "off";
gpios = <&fan_ioexp 12 GPIO_ACTIVE_HIGH>;
};
fan1_amber {
retain-state-shutdown;
default-state = "off";
gpios = <&fan_ioexp 13 GPIO_ACTIVE_HIGH>;
};
fan2_amber {
retain-state-shutdown;
default-state = "off";
gpios = <&fan_ioexp 14 GPIO_ACTIVE_HIGH>;
};
fan3_amber {
retain-state-shutdown;
default-state = "off";
gpios = <&fan_ioexp 15 GPIO_ACTIVE_HIGH>;
};
sled0_amber {
retain-state-shutdown;
default-state = "off";
gpios = <&sled0_leds 0 GPIO_ACTIVE_LOW>;
};
sled0_blue {
retain-state-shutdown;
default-state = "off";
gpios = <&sled0_leds 1 GPIO_ACTIVE_LOW>;
};
sled1_amber {
retain-state-shutdown;
default-state = "off";
gpios = <&sled1_leds 0 GPIO_ACTIVE_LOW>;
};
sled1_blue {
retain-state-shutdown;
default-state = "off";
gpios = <&sled1_leds 1 GPIO_ACTIVE_LOW>;
};
sled2_amber {
retain-state-shutdown;
default-state = "off";
gpios = <&sled2_leds 0 GPIO_ACTIVE_LOW>;
};
sled2_blue {
retain-state-shutdown;
default-state = "off";
gpios = <&sled2_leds 1 GPIO_ACTIVE_LOW>;
};
sled3_amber {
retain-state-shutdown;
default-state = "off";
gpios = <&sled3_leds 0 GPIO_ACTIVE_LOW>;
};
sled3_blue {
retain-state-shutdown;
default-state = "off";
gpios = <&sled3_leds 1 GPIO_ACTIVE_LOW>;
};
sled4_amber {
retain-state-shutdown;
default-state = "off";
gpios = <&sled4_leds 0 GPIO_ACTIVE_LOW>;
};
sled4_blue {
retain-state-shutdown;
default-state = "off";
gpios = <&sled4_leds 1 GPIO_ACTIVE_LOW>;
};
sled5_amber {
retain-state-shutdown;
default-state = "off";
gpios = <&sled5_leds 0 GPIO_ACTIVE_LOW>;
};
sled5_blue {
retain-state-shutdown;
default-state = "off";
gpios = <&sled5_leds 1 GPIO_ACTIVE_LOW>;
};
};
};
&mac2 {
status = "okay";
phy-mode = "rgmii";
phy-handle = <&switchphy>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii3_default>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&rtc {
status = "okay";
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
spi-max-frequency = <50000000>;
#include "openbmc-flash-layout-128.dtsi"
};
};
&spi2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2_default>;
flash@0 {
status = "okay";
m25p,fast-read;
label = "pnor";
spi-max-frequency = <100000000>;
};
};
&i2c0 {
status = "okay";
/* TODO: Add ADC INA230 */
mp5023@40 {
compatible = "mps,mp5023";
reg = <0x40>;
};
tmp421@4f {
compatible = "ti,tmp421";
reg = <0x4f>;
};
sled0_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"SLED0_MS_DETECT1","SLED0_VBUS_BMC_EN","SLED0_INA230_ALERT","SLED0_P12V_STBY_ALERT",
"SLED0_SSD_ALERT","SLED0_MS_DETECT0","SLED0_RST_CCG5","SLED0_FUSB302_INT",
"SLED0_MD_STBY_RESET","SLED0_MD_IOEXP_EN_FAULT","SLED0_MD_DIR","SLED0_MD_DECAY",
"SLED0_MD_MODE1","SLED0_MD_MODE2","SLED0_MD_MODE3","power-host0";
};
sled0_leds: pca9552@67 {
compatible = "nxp,pca9552";
reg = <0x67>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"led-sled0-amber","led-sled0-blue","SLED0_RST_IOEXP","",
"","","","",
"","","","",
"","","","";
};
sled0_fusb302: typec-portc@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
try-power-role = "sink";
data-role = "dual";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(3000, 12000, 3000)
PDO_PPS_APDO(3000, 11000, 3000)>;
op-sink-microwatt = <10000000>;
};
};
};
&i2c1 {
status = "okay";
/* TODO: Add ADC INA230 */
mp5023@40 {
compatible = "mps,mp5023";
reg = <0x40>;
};
tmp421@4f {
compatible = "ti,tmp421";
reg = <0x4f>;
};
sled1_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"SLED1_MS_DETECT1","SLED1_VBUS_BMC_EN","SLED1_INA230_ALERT","SLED1_P12V_STBY_ALERT",
"SLED1_SSD_ALERT","SLED1_MS_DETECT0","SLED1_RST_CCG5","SLED1_FUSB302_INT",
"SLED1_MD_STBY_RESET","SLED1_MD_IOEXP_EN_FAULT","SLED1_MD_DIR","SLED1_MD_DECAY",
"SLED1_MD_MODE1","SLED1_MD_MODE2","SLED1_MD_MODE3","power-host1";
};
sled1_leds: pca9552@67 {
compatible = "nxp,pca9552";
reg = <0x67>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"led-sled1-amber","led-sled1-blue","SLED1_RST_IOEXP","",
"","","","",
"","","","",
"","","","";
};
sled1_fusb302: typec-portc@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
try-power-role = "sink";
data-role = "dual";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(3000, 12000, 3000)
PDO_PPS_APDO(3000, 11000, 3000)>;
op-sink-microwatt = <10000000>;
};
};
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
/* TODO: Add ADC INA230 */
mp5023@40 {
compatible = "mps,mp5023";
reg = <0x40>;
};
tmp421@4f {
compatible = "ti,tmp421";
reg = <0x4f>;
};
sled2_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"SLED2_MS_DETECT1","SLED2_VBUS_BMC_EN","SLED2_INA230_ALERT","SLED2_P12V_STBY_ALERT",
"SLED2_SSD_ALERT","SLED2_MS_DETECT0","SLED2_RST_CCG5","SLED2_FUSB302_INT",
"SLED2_MD_STBY_RESET","SLED2_MD_IOEXP_EN_FAULT","SLED2_MD_DIR","SLED2_MD_DECAY",
"SLED2_MD_MODE1","SLED2_MD_MODE2","SLED2_MD_MODE3","power-host2";
};
sled2_leds: pca9552@67 {
compatible = "nxp,pca9552";
reg = <0x67>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"led-sled2-amber","led-sled2-blue","SLED2_RST_IOEXP","",
"","","","",
"","","","",
"","","","";
};
sled2_fusb302: typec-portc@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
try-power-role = "sink";
data-role = "dual";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(3000, 12000, 3000)
PDO_PPS_APDO(3000, 11000, 3000)>;
op-sink-microwatt = <10000000>;
};
};
};
&i2c3 {
status = "okay";
/* TODO: Add ADC INA230 */
mp5023@40 {
compatible = "mps,mp5023";
reg = <0x40>;
};
tmp421@4f {
compatible = "ti,tmp421";
reg = <0x4f>;
};
sled3_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"SLED3_MS_DETECT1","SLED3_VBUS_BMC_EN","SLED3_INA230_ALERT","SLED3_P12V_STBY_ALERT",
"SLED3_SSD_ALERT","SLED3_MS_DETECT0","SLED3_RST_CCG5","SLED3_FUSB302_INT",
"SLED3_MD_STBY_RESET","SLED3_MD_IOEXP_EN_FAULT","SLED3_MD_DIR","SLED3_MD_DECAY",
"SLED3_MD_MODE1","SLED3_MD_MODE2","SLED3_MD_MODE3","power-host3";
};
sled3_leds: pca9552@67 {
compatible = "nxp,pca9552";
reg = <0x67>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"led-sled3-amber","led-sled3-blue","SLED3_RST_IOEXP","",
"","","","",
"","","","",
"","","","";
};
sled3_fusb302: typec-portc@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
try-power-role = "sink";
data-role = "dual";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(3000, 12000, 3000)
PDO_PPS_APDO(3000, 11000, 3000)>;
op-sink-microwatt = <10000000>;
};
};
};
&i2c4 {
status = "okay";
/* TODO: Add ADC INA230 */
mp5023@40 {
compatible = "mps,mp5023";
reg = <0x40>;
};
tmp421@4f {
compatible = "ti,tmp421";
reg = <0x4f>;
};
sled4_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"SLED4_MS_DETECT1","SLED4_VBUS_BMC_EN","SLED4_INA230_ALERT","SLED4_P12V_STBY_ALERT",
"SLED4_SSD_ALERT","SLED4_MS_DETECT0","SLED4_RST_CCG5","SLED4_FUSB302_INT",
"SLED4_MD_STBY_RESET","SLED4_MD_IOEXP_EN_FAULT","SLED4_MD_DIR","SLED4_MD_DECAY",
"SLED4_MD_MODE1","SLED4_MD_MODE2","SLED4_MD_MODE3","power-host4";
};
sled4_leds: pca9552@67 {
compatible = "nxp,pca9552";
reg = <0x67>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"led-sled4-amber","led-sled4-blue","SLED4_RST_IOEXP","",
"","","","",
"","","","",
"","","","";
};
sled4_fusb302: typec-portc@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
try-power-role = "sink";
data-role = "dual";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(3000, 12000, 3000)
PDO_PPS_APDO(3000, 11000, 3000)>;
op-sink-microwatt = <10000000>;
};
};
};
&i2c5 {
status = "okay";
/* TODO: Add ADC INA230 */
mp5023@40 {
compatible = "mps,mp5023";
reg = <0x40>;
};
tmp421@4f {
compatible = "ti,tmp421";
reg = <0x4f>;
};
sled5_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"SLED5_MS_DETECT1","SLED5_VBUS_BMC_EN","SLED5_INA230_ALERT","SLED5_P12V_STBY_ALERT",
"SLED5_SSD_ALERT","SLED5_MS_DETECT0","SLED5_RST_CCG5","SLED5_FUSB302_INT",
"SLED5_MD_STBY_RESET","SLED5_MD_IOEXP_EN_FAULT","SLED5_MD_DIR","SLED5_MD_DECAY",
"SLED5_MD_MODE1","SLED5_MD_MODE2","SLED5_MD_MODE3","power-host5";
};
sled5_leds: pca9552@67 {
compatible = "nxp,pca9552";
reg = <0x67>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"led-sled5-amber","led-sled5-blue","SLED5_RST_IOEXP","",
"","","","",
"","","","",
"","","","";
};
sled5_fusb302: typec-portc@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
try-power-role = "sink";
data-role = "dual";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(3000, 12000, 3000)
PDO_PPS_APDO(3000, 11000, 3000)>;
op-sink-microwatt = <10000000>;
};
};
};
&i2c6 {
status = "okay";
eeprom@56 {
compatible = "atmel,24c64";
reg = <0x56>;
};
rtc@51 {
compatible = "nxp,pcf85263";
reg = <0x51>;
};
};
&i2c7 {
status = "okay";
eeprom@54 {
compatible = "atmel,24c64";
reg = <0x54>;
};
};
&i2c9 {
status = "okay";
tmp421@4f {
compatible = "ti,tmp421";
reg = <0x4f>;
};
};
&i2c10 {
status = "okay";
tmp421@4f {
compatible = "ti,tmp421";
reg = <0x4f>;
};
hdc1080@40 {
compatible = "ti,hdc1080";
reg = <0x40>;
};
front_leds: pca9552@67 {
compatible = "nxp,pca9552";
reg = <0x67>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"led-fault-identify","power-p5v-stby-good",
"power-p1v0-dvdd-good","power-p1v0-avdd-good",
"","","","",
"","","","",
"","","","";
};
};
&i2c12 {
status = "okay";
adm1278@11 {
compatible = "adi,adm1278";
reg = <0x11>;
};
tmp421@4c {
compatible = "ti,tmp421";
reg = <0x4c>;
};
tmp421@4d {
compatible = "ti,tmp421";
reg = <0x4d>;
};
fan_ioexp: pca9552@67 {
compatible = "nxp,pca9552";
reg = <0x67>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"presence-fan0","presence-fan1",
"presence-fan2","presence-fan3",
"power-fan0-good","power-fan1-good",
"power-fan2-good","power-fan3-good",
"","","","",
"","","","";
};
};
&i2c13 {
multi-master;
aspeed,hw-timeout-ms = <1000>;
status = "okay";
};
&gpio0 {
gpio-line-names =
/*A0-A7*/ "","","","","","","","",
/*B0-B7*/ "","","SEL_SPI2_MUX","SPI2_MUX1",
"SPI2_MUX2","SPI2_MUX3","","",
/*C0-C7*/ "","","","","","","","",
/*D0-D7*/ "","","","","","","","",
/*E0-E7*/ "","","","","","","","",
/*F0-F7*/ "","","","","","","","",
/*G0-G7*/ "","SWITCH_FRU_MUX","","","","","","",
/*H0-H7*/ "presence-riser1","presence-riser2",
"presence-sled0","presence-sled1",
"presence-sled2","presence-sled3",
"presence-sled4","presence-sled5",
/*I0-I7*/ "REV_ID0","","REV_ID1","REV_ID2",
"","","","",
/*J0-J7*/ "","","","","","","","",
/*K0-K7*/ "","","","","","","","",
/*L0-L7*/ "","","","","","","","",
/*M0-M7*/ "ALERT_SLED0","ALERT_SLED1",
"ALERT_SLED2","ALERT_SLED3",
"ALERT_SLED4","ALERT_SLED5",
"P12V_AUX_ALERT1","",
/*N0-N7*/ "","","","","","","","",
/*O0-O7*/ "","","","",
"","BOARD_ID0","BOARD_ID1","BOARD_ID2",
/*P0-P7*/ "","","","","","","","",
/*Q0-Q7*/ "","","","","","","","",
/*R0-R7*/ "","","","","","","","",
/*S0-S7*/ "","","","BAT_DETECT",
"BMC_BT_WP0","BMC_BT_WP1","","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "","RST_BMC_MVL","","",
"USB2_SEL0_A","USB2_SEL1_A",
"USB2_SEL0_B","USB2_SEL1_B",
/*W0-W7*/ "RST_FRONT_IOEXP","","","","","","","",
/*X0-X7*/ "","","","","","","","",
/*Y0-Y7*/ "","","BSM_FLASH_LATCH","","","","","",
/*Z0-Z7*/ "","","","","","","","";
};
&adc0 {
vref = <1800>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
&pinctrl_adc2_default &pinctrl_adc3_default
&pinctrl_adc4_default &pinctrl_adc5_default
&pinctrl_adc6_default &pinctrl_adc7_default>;
};
&adc1 {
vref = <2500>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default
&pinctrl_adc10_default &pinctrl_adc11_default
&pinctrl_adc12_default &pinctrl_adc13_default
&pinctrl_adc14_default &pinctrl_adc15_default>;
};

892
arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts
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File diff suppressed because it is too large Load Diff

1238
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
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File diff suppressed because it is too large Load Diff

9
arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts
View File

@ -3,6 +3,7 @@
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
#include <dt-bindings/leds/leds-pca955x.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "FP5280G2 BMC";
@ -245,7 +246,7 @@ flash@0 {
label = "bmc";
m25p,fast-read;
spi-max-frequency = <50000000>;
#include "openbmc-flash-layout.dtsi"
#include "openbmc-flash-layout-64.dtsi"
};
};
@ -902,4 +903,10 @@ fan@7 {
};
&kcs3 {
status = "okay";
aspeed,lpc-io-reg = <0xca2>;
aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
};
#include "ibm-power9-dual.dtsi"

328
arch/arm/boot/dts/aspeed-bmc-inventec-transformers.dts Normal file
View File

@ -0,0 +1,328 @@
// SPDX-License-Identifier: GPL-2.0-or-later
// Copyright 2021 Inventec Corp.
/dts-v1/;
#include "aspeed-g6.dtsi"
#include "aspeed-g6-pinctrl.dtsi"
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "TRANSFORMERS BMC";
compatible = "inventec,transformer-bmc", "aspeed,ast2600";
aliases {
serial4 = &uart5;
};
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200n8";
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
leds {
compatible = "gpio-leds";
// UID led
uid {
label = "UID_LED";
gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>;
};
// Heart beat led
heartbeat {
label = "HB_LED";
gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>;
};
};
};
&mdio0 {
status = "okay";
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mac3 {
status = "okay";
phy-mode = "rgmii";
phy-handle = <&ethphy0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii4_default>;
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
spi-max-frequency = <33000000>;
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
#include "openbmc-flash-layout.dtsi"
};
flash@1 {
status = "okay";
m25p,fast-read;
label = "bmc2";
spi-max-frequency = <33000000>;
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
};
};
&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
flash@0 {
status = "okay";
m25p,fast-read;
label = "bios";
spi-max-frequency = <33000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};
&wdt1 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart5 {
status = "okay";
};
&i2c0 {
status = "okay";
//Set bmc' slave address;
bmc_slave@10 {
compatible = "ipmb-dev";
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
i2c-protocol;
};
};
&i2c2 {
status = "okay";
};
&i2c3 {
// FRU AT24C512C-SSHM-T
status = "okay";
eeprom@50 {
compatible = "atmel,24c512";
reg = <0x50>;
pagesize = <128>;
};
};
&i2c5 {
status = "okay";
};
&i2c6 {
status = "okay";
tmp75@49 {
compatible = "ti,tmp75";
reg = <0x49>;
};
tmp75@4f {
compatible = "ti,tmp75";
reg = <0x4f>;
};
tmp468@48 {
compatible = "ti,tmp468";
reg = <0x48>;
};
};
&i2c7 {
status = "okay";
adm1278@40 {
compatible = "adi,adm1278";
reg = <0x40>;
};
};
&i2c8 {
// FRU AT24C512C-SSHM-T
status = "okay";
eeprom@51 {
compatible = "atmel,24c512";
reg = <0x51>;
pagesize = <128>;
};
eeprom@53 {
compatible = "atmel,24c512";
reg = <0x53>;
pagesize = <128>;
};
};
&i2c9 {
// M.2
status = "okay";
};
&i2c10 {
// I2C EXPANDER
status = "okay";
i2c-switch@71 {
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x71>;
};
i2c-switch@73 {
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x73>;
};
};
&i2c11 {
// I2C EXPANDER
status = "okay";
i2c-switch@70 {
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
pcie_eeprom_riser1: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
eeprom@55 {
compatible = "atmel,24c512";
reg = <0x55>;
pagesize = <128>;
};
};
pcie_eeprom_riser2: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
eeprom@55 {
compatible = "atmel,24c512";
reg = <0x55>;
pagesize = <128>;
};
};
pcie_eeprom_riser3: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
eeprom@55 {
compatible = "atmel,24c512";
reg = <0x55>;
pagesize = <128>;
};
};
};
};
&i2c12 {
status = "okay";
psu0:psu0@58 {
compatible = "pmbus";
reg = <0x58>;
};
};
&gpio0 {
status = "okay";
gpio-line-names =
/*A0-A7*/ "","","","","","","","",
/*B0-B7*/ "presence-ps0","power-chassis-good","","","","","presence-ps1","",
/*C0-C7*/ "","","","","","","","",
/*D0-D7*/ "","","","","","","","",
/*E0-E7*/ "","","","","","","","",
/*F0-F7*/ "","","","","power-chassis-control","","","",
/*G0-G7*/ "","","jtag-mux","","","","","",
/*H0-H7*/ "","","","","reset-button","power-button","","",
/*I0-I7*/ "","","","","","","","",
/*J0-J7*/ "","","","","","","","",
/*K0-K7*/ "","","","","","","","",
/*L0-L7*/ "","","","","","","","",
/*M0-M7*/ "","","","","","","","",
/*N0-N7*/ "","","","","","","","",
/*O0-O7*/ "","","","","","","","",
/*P0-P7*/ "","","","tck-mux","","","","",
/*Q0-Q7*/ "","","","","","","","",
/*R0-R7*/ "","","","","","","","",
/*S0-S7*/ "","","","","","","","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","nmi-button","","","","","","",
/*V0-V7*/ "","","","","power-config-full-load","","","",
/*W0-W7*/ "","","","","","","","",
/*X0-X7*/ "","","","","","","","",
/*Y0-Y7*/ "","","","","","","","",
/*Z0-Z7*/ "","","","","","","","",
/*AA0-AA7*/ "","","","","","","","",
/*AB0-AB7*/ "","","","","","","","",
/*AC0-AC7*/ "","","","","","","","";
};
&lpc_snoop {
status = "okay";
snoop-ports = <0x80>;
};
&emmc_controller {
status = "okay";
};
&emmc {
status = "okay";
non-removable;
max-frequency = <52000000>;
bus-width = <8>;
};
&vhub {
status = "okay";
aspeed,vhub-downstream-ports = <7>;
aspeed,vhub-generic-endpoints = <21>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2ad_default>;
};
&rtc {
status = "okay";
};

528
arch/arm/boot/dts/aspeed-bmc-tyan-s7106.dts Normal file
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// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "Tyan S7106 BMC";
compatible = "tyan,s7106-bmc", "aspeed,ast2500";
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
p2a_memory: region@987f0000 {
no-map;
reg = <0x987f0000 0x00010000>; /* 64KB */
};
vga_memory: framebuffer@9f000000 {
no-map;
reg = <0x9f000000 0x01000000>; /* 16M */
};
gfx_memory: framebuffer {
size = <0x01000000>; /* 16M */
alignment = <0x01000000>;
compatible = "shared-dma-pool";
reusable;
};
};
leds {
compatible = "gpio-leds";
identify {
gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>;
};
heartbeat {
gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>;
};
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
<&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
<&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>,
<&adc 12>, <&adc 13>, <&adc 14>;
};
iio-hwmon-battery {
compatible = "iio-hwmon";
io-channels = <&adc 15>;
};
};
&fmc {
status = "okay";
flash@0 {
label = "bmc";
status = "okay";
m25p,fast-read;
#include "openbmc-flash-layout.dtsi"
};
};
&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
flash@0 {
status = "okay";
label = "pnor";
m25p,fast-read;
};
};
&uart1 {
/* Rear RS-232 connector */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default>;
};
&uart2 {
/* RS-232 connector on header */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd2_default
&pinctrl_rxd2_default>;
};
&uart3 {
/* Alternative to vuart to internally connect (route) to uart1
* when vuart cannot be used due to BIOS limitations.
*/
status = "okay";
};
&uart4 {
/* Alternative to vuart to internally connect (route) to the
* external port usually used by uart1 when vuart cannot be
* used due to BIOS limitations.
*/
status = "okay";
};
&uart5 {
/* BMC "debug" (console) UART; connected to RS-232 connector
* on header; selectable via jumpers as alternative to uart2
*/
status = "okay";
};
&uart_routing {
status = "okay";
};
&vuart {
status = "okay";
/* We enable the VUART here, but leave it in a state that does
* not interfere with the SuperIO. The goal is to have both the
* VUART and the SuperIO available and decide at runtime whether
* the VUART should actually be used. For that reason, configure
* an "invalid" IO address and an IRQ that is not used by the
* BMC.
*/
aspeed,lpc-io-reg = <0xffff>;
aspeed,lpc-interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
};
&lpc_ctrl {
status = "okay";
};
&p2a {
status = "okay";
memory-region = <&p2a_memory>;
};
&lpc_snoop {
status = "okay";
snoop-ports = <0x80>;
};
&adc {
status = "okay";
};
&vhub {
status = "okay";
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_default
&pinctrl_pwm1_default
&pinctrl_pwm3_default
&pinctrl_pwm4_default>;
/* CPU fan #0 */
fan@0 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x00>;
};
/* CPU fan #1 */
fan@1 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x01>;
};
/* PWM group for chassis fans #1, #2, #3 and #4 */
fan@2 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x02>;
};
fan@3 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x03>;
};
fan@4 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x04>;
};
fan@5 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x05>;
};
/* PWM group for chassis fans #5 and #6 */
fan@6 {
reg = <0x04>;
aspeed,fan-tach-ch = /bits/ 8 <0x06>;
};
fan@7 {
reg = <0x04>;
aspeed,fan-tach-ch = /bits/ 8 <0x07>;
};
};
&i2c0 {
status = "okay";
/* Hardware monitor with temperature sensors */
nct7802@28 {
compatible = "nuvoton,nct7802";
reg = <0x28>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 { /* LTD */
reg = <0>;
};
channel@1 { /* RTD1 */
reg = <1>;
sensor-type = "temperature";
temperature-mode = "thermistor";
};
channel@2 { /* RTD2 */
reg = <2>;
sensor-type = "temperature";
temperature-mode = "thermistor";
};
channel@3 { /* RTD3 */
reg = <3>;
sensor-type = "temperature";
};
};
/* Also connected to:
* - IPMB pin header
* - CPU #0 memory error LED @ 0x3A
* - CPU #1 memory error LED @ 0x3C
*/
};
&i2c1 {
/* Directly connected to PCH SMBUS #0 */
status = "okay";
};
&i2c2 {
status = "okay";
/* BMC EEPROM, incl. mainboard FRU */
eeprom@50 {
compatible = "atmel,24c256";
reg = <0x50>;
};
/* Also connected to:
* - fan header
* - mini-SAS HD connector
* - SSATA SGPIO
* - via switch (BMC_SMB3_PCH_IE_SML3_EN, active low)
* to PCH SMBUS #3
*/
};
&i2c3 {
status = "okay";
/* PSU1 FRU @ 0xA0 */
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
};
/* PSU2 FRU @ 0xA2 */
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
};
/* PSU1 @ 0xB0 */
power-supply@58 {
compatible = "pmbus";
reg = <0x58>;
};
/* PSU2 @ 0xB2 */
power-supply@59 {
compatible = "pmbus";
reg = <0x59>;
};
/* Also connected to:
* - PCH SMBUS #1
*/
};
&i2c4 {
status = "okay";
/* Connected to:
* - PCH SMBUS #2
*/
/* Connected via switch to:
* - CPU #0 channels ABC VDDQ @ 0x80
* - CPU #0 channels DEF VDDQ @ 0x81
* - CPU #1 channels ABC VDDQ @ 0x82
* - CPU #1 channels DEF VDDQ @ 0x83
* - CPU #0 VCCIO & VMCP @ 0x52
* - CPU #1 VCCIO & VMCP @ 0x53
* - CPU #0 VCCIN @ 0xC0
* - CPU #0 VSA @ 0xC2
* - CPU #1 VCCIN @ 0xC4
* - CPU #1 VSA @ 0xC6
* - J110
*/
};
&i2c5 {
status = "okay";
/* Connected via switch (PCH_BMC_SMB_SW_P) to:
* - mainboard FRU @ 0xAE
* - XDP connector
* - ME debug header
* - clock buffer @ 0xD8
* - i2c4 via switch (PCH_VR_SMBUS_SW_P; controlled by PCH)
* - PCH SMBUS
*/
};
&i2c6 {
status = "okay";
/* Connected via switch (BMC_PE_SMB_EN_1_N) to
* bus mux (selector BMC_PE_SMB_SW_BIT[1..0]) to:
* - 0,0: PCIE slot 1, SMB #1
* - 0,1: PCIE slot 1, SMB #2
* - 1,0: PCIE slot 2, SMB #1
* - 1,1: PCIE slot 2, SMB #2
*/
/* Connected via switch (BMC_PE_SMB_EN_2_N) to
* bus mux (selector BMC_PE_SMB_SW_BIT[1..0]) to:
* - 0,0: OCP0 (A) SMB
* - 0,1: OCP0 (C) SMB
* - 1,0: OCP1 (A) SMB
* - 1,1: NC
*/
};
&i2c7 {
status = "okay";
/* Connected to:
* - PCH SMBUS #4
*/
};
&i2c8 {
status = "okay";
/* Not connected */
};
&mac0 {
status = "okay";
use-ncsi;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
};
&mac1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
&ibt {
status = "okay";
};
&kcs1 {
status = "okay";
aspeed,lpc-io-reg = <0xca8>;
};
&kcs3 {
status = "okay";
aspeed,lpc-io-reg = <0xca2>;
};
/* Enable BMC VGA output to show an early (pre-BIOS) boot screen */
&gfx {
status = "okay";
memory-region = <&gfx_memory>;
};
/* We're following the GPIO naming as defined at
* https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md.
*
* Notes on led-identify and id-button:
* - A physical button is connected to id-button which
* triggers the clock on a D flip-flop. The /Q output of the
* flip-flop drives its D input.
* - The flip-flop's Q output drives led-identify which is
* connected to LEDs.
* - With that, every button press toggles the LED between on and off.
*
* Notes on power-, reset- and nmi- button and control:
* - The -button signals can be used to monitor physical buttons.
* - The -control signals can be used to actuate the specific
* operation.
* - In hardware, the -button signals are connected to the -control
* signals through drivers with the -control signals being
* protected through diodes.
*/
&gpio {
status = "okay";
gpio-line-names =
/*A0*/ "",
/*A1*/ "",
/*A2*/ "led-identify", /* in/out: BMC_IDLED_ON_N */
/*A3*/ "",
/*A4*/ "",
/*A5*/ "",
/*A6*/ "",
/*A7*/ "",
/*B0-B7*/ "","","","","","","","",
/*C0*/ "",
/*C1*/ "",
/*C2*/ "",
/*C3*/ "",
/*C4*/ "id-button", /* in/out: BMC_IDBTN_IN_OUT_N */
/*C5*/ "post-complete", /* in: FM_BIOS_POST_CMPLT_N */
/*C6*/ "",
/*C7*/ "",
/*D0*/ "",
/*D1*/ "",
/*D2*/ "power-chassis-good", /* in: SYS_PWROK_BUF */
/*D3*/ "platform-reset", /* in: SYS_PLTRST_N */
/*D4*/ "",
/*D5*/ "",
/*D6*/ "",
/*D7*/ "",
/*E0*/ "power-button", /* in: BMC_PWBTN_IN_N */
/*E1*/ "power-chassis-control", /* out: BMC_PWRBTN_OUT_N */
/*E2*/ "reset-button", /* in: BMC_RSTBTN_IN_N */
/*E3*/ "reset-control", /* out: BMC_RSTBTN_OUT_N */
/*E4*/ "nmi-button", /* in: BMC_NMIBTN_IN_N */
/*E5*/ "nmi-control", /* out: BMC_NMIBTN_OUT_N */
/*E6*/ "",
/*E7*/ "led-heartbeat", /* out: BMC_HEARTBRAT_LED_N */
/*F0*/ "",
/*F1*/ "clear-cmos-control", /* out: BMC_CLR_CMOS_N */
/*F2*/ "",
/*F3*/ "",
/*F4*/ "led-fault", /* out: AST_HW_FAULT_N */
/*F5*/ "",
/*F6*/ "",
/*F7*/ "",
/*G0*/ "BMC_PE_SMB_EN_1_N", /* out */
/*G1*/ "BMC_PE_SMB_EN_2_N", /* out */
/*G2*/ "",
/*G3*/ "",
/*G4*/ "",
/*G5*/ "",
/*G6*/ "",
/*G7*/ "",
/*H0-H7*/ "","","","","","","","",
/*I0-I7*/ "","","","","","","","",
/*J0-J7*/ "","","","","","","","",
/*K0-K7*/ "","","","","","","","",
/*L0-L7*/ "","","","","","","","",
/*M0-M7*/ "","","","","","","","",
/*N0-N7*/ "","","","","","","","",
/*O0-O7*/ "","","","","","","","",
/*P0-P7*/ "","","","","","","","",
/*Q0*/ "",
/*Q1*/ "",
/*Q2*/ "",
/*Q3*/ "",
/*Q4*/ "BMC_PE_SMB_SW_BIT0", /* out */
/*Q5*/ "BMC_PE_SMB_SW_BIT1", /* out */
/*Q6*/ "",
/*Q7*/ "",
/*R0-R7*/ "","","","","","","","",
/*S0-S7*/ "","","","","","","","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "","","","","","","","",
/*W0-W7*/ "","","","","","","","",
/*X0-X7*/ "","","","","","","","",
/*Y0-Y7*/ "","","","","","","","",
/*Z0-Z7*/ "","","","","","","","",
/*AA0*/ "",
/*AA1*/ "",
/*AA2*/ "",
/*AA3*/ "BMC_SMB3_PCH_IE_SML3_EN", /* out */
/*AA4*/ "",
/*AA5*/ "",
/*AA6*/ "",
/*AA7*/ "",
/*AB0-AB7*/ "","","","","","","","";
};

470
arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts Normal file
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// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "Tyan S8036 BMC";
compatible = "tyan,s8036-bmc", "aspeed,ast2500";
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
p2a_memory: region@987f0000 {
no-map;
reg = <0x987f0000 0x00010000>; /* 64KB */
};
vga_memory: framebuffer@9f000000 {
no-map;
reg = <0x9f000000 0x01000000>; /* 16M */
};
gfx_memory: framebuffer {
size = <0x01000000>; /* 16M */
alignment = <0x01000000>;
compatible = "shared-dma-pool";
reusable;
};
};
leds {
compatible = "gpio-leds";
identify {
gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>;
};
heartbeat {
gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>;
};
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
<&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
<&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>,
<&adc 12>, <&adc 13>, <&adc 14>;
};
iio-hwmon-battery {
compatible = "iio-hwmon";
io-channels = <&adc 15>;
};
};
&fmc {
status = "okay";
flash@0 {
label = "bmc";
status = "okay";
m25p,fast-read;
#include "openbmc-flash-layout.dtsi"
};
};
&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
flash@0 {
status = "okay";
label = "pnor";
m25p,fast-read;
};
};
&uart1 {
/* Rear RS-232 connector */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default>;
};
&uart2 {
/* RS-232 connector on header */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd2_default
&pinctrl_rxd2_default>;
};
&uart3 {
/* Alternative to vuart to internally connect (route) to uart1
* when vuart cannot be used due to BIOS limitations.
*/
status = "okay";
};
&uart4 {
/* Alternative to vuart to internally connect (route) to the
* external port usually used by uart1 when vuart cannot be
* used due to BIOS limitations.
*/
status = "okay";
};
&uart5 {
/* BMC "debug" (console) UART; connected to RS-232 connector
* on header; selectable via jumpers as alternative to uart2
*/
status = "okay";
};
&uart_routing {
status = "okay";
};
&vuart {
status = "okay";
/* We enable the VUART here, but leave it in a state that does
* not interfere with the SuperIO. The goal is to have both the
* VUART and the SuperIO available and decide at runtime whether
* the VUART should actually be used. For that reason, configure
* an "invalid" IO address and an IRQ that is not used by the
* BMC.
*/
aspeed,lpc-io-reg = <0xffff>;
aspeed,lpc-interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
};
&lpc_ctrl {
status = "okay";
};
&p2a {
status = "okay";
memory-region = <&p2a_memory>;
};
&lpc_snoop {
status = "okay";
snoop-ports = <0x80>;
};
&adc {
status = "okay";
};
&vhub {
status = "okay";
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_default
&pinctrl_pwm1_default
&pinctrl_pwm3_default
&pinctrl_pwm4_default>;
/* CPU fan */
fan@0 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x00>;
};
/* PWM group for chassis fans #1, #2, #3 and #4 */
fan@2 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x02>;
};
fan@3 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x03>;
};
fan@4 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x04>;
};
fan@5 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x05>;
};
/* PWM group for chassis fans #5 and #6 */
fan@6 {
reg = <0x04>;
aspeed,fan-tach-ch = /bits/ 8 <0x06>;
};
fan@7 {
reg = <0x04>;
aspeed,fan-tach-ch = /bits/ 8 <0x07>;
};
};
&i2c0 {
/* Directly connected to Sideband-Temperature Sensor Interface (APML) */
status = "okay";
};
&i2c1 {
/* Directly connected to IPMB HDR. */
status = "okay";
};
&i2c2 {
status = "okay";
/* BMC EEPROM, incl. mainboard FRU */
eeprom@50 {
compatible = "atmel,24c256";
reg = <0x50>;
};
/* Also connected to:
* - BCM5720
* - FPGA
* - FAN HDR
* - FPIO HDR
*/
};
&i2c3 {
status = "okay";
/* PSU1 FRU @ 0xA0 */
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
};
/* PSU2 FRU @ 0xA2 */
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
};
/* PSU1 @ 0xB0 */
power-supply@58 {
compatible = "pmbus";
reg = <0x58>;
};
/* PSU2 @ 0xB2 */
power-supply@59 {
compatible = "pmbus";
reg = <0x59>;
};
};
&i2c4 {
status = "okay";
};
&i2c5 {
status = "okay";
/* Hardware monitor with temperature sensors */
nct7802@28 {
compatible = "nuvoton,nct7802";
reg = <0x28>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 { /* LTD */
reg = <0>;
status = "okay";
};
channel@1 { /* RTD1 */
reg = <1>;
status = "okay";
sensor-type = "temperature";
temperature-mode = "thermistor";
};
channel@2 { /* RTD2 */
reg = <2>;
status = "okay";
sensor-type = "temperature";
temperature-mode = "thermistor";
};
channel@3 { /* RTD3 */
reg = <3>;
status = "okay";
sensor-type = "temperature";
};
};
/* Also connected to:
* - PCA9544
* - CLK BUFF
* - OCP FRU
*/
};
&i2c6 {
status = "okay";
/* Connected to:
* - PCA9548 @0xE0
* - PCA9548 @0xE2
* - PCA9544 @0xE4
*/
};
&i2c7 {
status = "okay";
/* Connected to:
* - PCH SMBUS #4
*/
};
&i2c8 {
status = "okay";
/* Not connected */
};
&mac0 {
status = "okay";
use-ncsi;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
};
&mac1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
&ibt {
status = "okay";
};
&kcs1 {
status = "okay";
aspeed,lpc-io-reg = <0xca8>;
};
&kcs3 {
status = "okay";
aspeed,lpc-io-reg = <0xca2>;
};
/* Enable BMC VGA output to show an early (pre-BIOS) boot screen */
&gfx {
status = "okay";
memory-region = <&gfx_memory>;
};
/* We're following the GPIO naming as defined at
* https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md.
*
* Notes on led-identify and id-button:
* - A physical button is connected to id-button which
* triggers the clock on a D flip-flop. The /Q output of the
* flip-flop drives its D input.
* - The flip-flop's Q output drives led-identify which is
* connected to LEDs.
* - With that, every button press toggles the LED between on and off.
*
* Notes on power-, reset- and nmi- button and control:
* - The -button signals can be used to monitor physical buttons.
* - The -control signals can be used to actuate the specific
* operation.
* - In hardware, the -button signals are connected to the -control
* signals through drivers with the -control signals being
* protected through diodes.
*/
&gpio {
status = "okay";
gpio-line-names =
/*A0*/ "",
/*A1*/ "",
/*A2*/ "led-identify", /* in/out: BMC_CHASSIS_ID_LED_L */
/*A3*/ "",
/*A4*/ "",
/*A5*/ "",
/*A6*/ "",
/*A7*/ "",
/*B0-B7*/ "","","","","","","","",
/*C0-C7*/ "","","","","","","","",
/*D0*/ "",
/*D1*/ "",
/*D2*/ "power-chassis-good", /* in: PWR_GOOD_LED -- Check if this is Z3?*/
/*D3*/ "platform-reset", /* in: RESET_LED_L */
/*D4*/ "",
/*D5*/ "",
/*D6*/ "",
/*D7*/ "",
/*E0*/ "power-button", /* in: BMC_SYS_MON_PWR_BTN_L */
/*E1*/ "power-chassis-control", /* out: BMC_ASSERT_PWR_BTN */
/*E2*/ "reset-button", /* in: BMC_SYS_MOS_RST_BTN_L*/
/*E3*/ "reset-control", /* out: BMC_ASSERT_RST_BTN */
/*E4*/ "nmi-button", /* in: BMC_SYS_MON_NMI_BTN_L */
/*E5*/ "nmi-control", /* out: BMC_ASSERT_NMI_BTN */
/*E6*/ "TSI_RESERT",
/*E7*/ "led-heartbeat", /* out: BMC_GPIOE7 */
/*F0*/ "",
/*F1*/ "clear-cmos-control", /* out: BMC_ASSERT_CLR_CMOS_L */
/*F2*/ "",
/*F3*/ "",
/*F4*/ "led-fault", /* out: BMC_HWM_FAULT_LED_L */
/*F5*/ "BMC_SYS_FAULT_LED_L",
/*F6*/ "BMC_ASSERT_BIOS_WP_L",
/*F7*/ "",
/*G0-G7*/ "","","","","","","","",
/*H0-H7*/ "","","","","","","","",
/*I0-I7*/ "","","","","","","","",
/*J0-J7*/ "","","","","","","","",
/*K0-K7*/ "","","","","","","","",
/*L0-L7*/ "","","","","","","","",
/*M0-M7*/ "","","","","","","","",
/*N0-N7*/ "","","","","","","","",
/*O0-O7*/ "","","","","","","","",
/*P0-P7*/ "","","","","","","","",
/*Q0*/ "",
/*Q1*/ "",
/*Q2*/ "",
/*Q3*/ "",
/*Q4*/ "",
/*Q5*/ "",
/*Q6*/ "id-button", /* in: BMC_CHASSIS_ID_BTN_L */
/*Q7*/ "",
/*R0-R7*/ "","","","","","","","",
/*S0-S7*/ "","","","","","","","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "","","","","","","","",
/*W0-W7*/ "","","","","","","","",
/*X0-X7*/ "","","","","","","","",
/*Y0-Y7*/ "","","","","","","","",
/*Z0-Z2*/ "","","",
/*Z3*/ "post-complete", /* BMC_SYS_MON_PWROK */
/*Z4-Z7*/ "","","","",
/*AA0*/ "",
/*AA1*/ "",
/*AA2*/ "",
/*AA3*/ "",
/*AA4*/ "",
/*AA5*/ "",
/*AA6*/ "",
/*AA7*/ "BMC_ASSERT_BMC_READY",
/*AB0*/ "BMC_SPD_SEL",
/*AB1-AB7*/ "","","","","","","";
};

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arch/arm/boot/dts/aspeed-bmc-vegman-n110.dts Normal file
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// SPDX-License-Identifier: GPL-2.0+
// Copyright (C) 2021 YADRO
/dts-v1/;
#include "aspeed-bmc-vegman.dtsi"
/ {
model = "YADRO VEGMAN N110 BMC";
compatible = "yadro,vegman-n110-bmc", "aspeed,ast2500";
};
&gpio {
status = "okay";
gpio-line-names =
/*A0-A7*/ "CHASSIS_INTRUSION","CASE_OPEN_FAULT_RST","","","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","",
/*B0-B7*/ "","","","","","","","",
/*C0-C7*/ "","","","","","","","",
/*D0-D7*/ "","","","","","","","",
/*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","","","","",
/*F0-F7*/ "NMI_OUT","PCIE_NIC_ALERT","","","SKT0_FAULT_LED","","RST_RGMII_PHYRST_DNP","",
/*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","","IRQ_NMI_EVENT","","","",
/*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS",
/*I0-I7*/ "","","","","","","","",
/*J0-J7*/ "","","","","","","","",
/*K0-K7*/ "","","","","","","","",
/*L0-L7*/ "","","","","","","","",
/*M0-M7*/ "","","","","","","","",
/*N0-N7*/ "","","","","","","","",
/*O0-O7*/ "","","","","","","","_SPI2_BMC_CS_SEL",
/*P0-P7*/ "","","","","","","","",
/*Q0-Q7*/ "","","","","","","","",
/*R0-R7*/ "_SPI_RMM4_LITE_CS","","","","","","","",
/*S0-S7*/ "_SPI2_BMC_CS1","","","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "","","","","","","","",
/*W0-W7*/ "","","","","","","","",
/*X0-X7*/ "","","","","","","","",
/*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","",
/*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","",
/*AA0-AA7*/ "","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE",
/*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","ID_BUTTON","PS_PWROK","","","","",
/*AC0-AC7*/ "","","","","","","","";
};
&sgpio {
ngpios = <80>;
bus-frequency = <2000000>;
status = "okay";
/* SGPIO lines. even: input, odd: output */
gpio-line-names =
/*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","",
/*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","",
/*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","",
/*D0-D7*/ "","","","","","","","","","","","","","","","",
/*E0-E7*/ "","","","","","","","","","","","","","","","",
/*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","",
/*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","",
/*H0-H7*/ "","","","","","","","","","","","","","","","",
/*I0-I7*/ "","","","","","","","","","","","","","","","",
/*J0-J7*/ "","","","","","","","","","","","","","","","";
};
&i2c11 {
/* SMB_BMC_MGMT_LVC3 */
gpio@21 {
compatible = "nxp,pcal9535";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
/*IO0.0-0.7*/ "", "", "", "", "", "", "PE_PCH_SCR_CLKREQ", "",
/*IO1.0-1.7*/ "", "PE_PCH_MEZ_PRSNT", "PE_PCH_MEZ_PRSNT_", "NIC_4_PE_PRSNT", "NIC_3_PE_PRSNT", "NIC_2_PE_PRSNT", "NIC_1_PE_PRSNT", "";
};
gpio@27 {
compatible = "nxp,pca9698";
reg = <0x27>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
/*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX",
/*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0",
/*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "", "", "",
/*IO3.0-3.7*/ "", "", "", "", "", "", "", "",
/*IO4.0-4.7*/ "", "", "", "", "", "", "", "";
};
};
&i2c13 {
/* SMB_PCIE2_STBY_LVC3 */
mux-expa@73 {
compatible = "nxp,pca9545";
reg = <0x73>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect;
};
mux-sata@71 {
compatible = "nxp,pca9543";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect;
};
};
&i2c2 {
/* SMB_PCIE_STBY_LVC3 */
mux-expb@71 {
compatible = "nxp,pca9545";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect;
};
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
&pinctrl_pwm2_default &pinctrl_pwm3_default
&pinctrl_pwm4_default &pinctrl_pwm5_default>;
fan@0 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x00 0x06>;
};
fan@1 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x01 0x08>;
};
fan@2 {
reg = <0x02>;
aspeed,fan-tach-ch = /bits/ 8 <0x02 0x09>;
};
fan@3 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0A>;
};
fan@4 {
reg = <0x04>;
aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0B>;
};
fan@5 {
reg = <0x05>;
aspeed,fan-tach-ch = /bits/ 8 <0x05>;
};
};

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// SPDX-License-Identifier: GPL-2.0+
// Copyright (C) 2021 YADRO
/dts-v1/;
#include "aspeed-bmc-vegman.dtsi"
/ {
model = "YADRO VEGMAN Rx20 BMC";
compatible = "yadro,vegman-rx20-bmc", "aspeed,ast2500";
leds {
compatible = "gpio-leds";
temp_alarm {
label = "temp:red:status";
default-state = "off";
gpios = <&gpio ASPEED_GPIO(E, 4) GPIO_ACTIVE_LOW>;
};
temp_ok {
label = "temp:green:status";
default-state = "off";
gpios = <&gpio ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>;
};
psu_fault {
label = "psu:red:status";
default-state = "off";
gpios = <&gpio ASPEED_GPIO(E, 6) GPIO_ACTIVE_LOW>;
};
psu_ok {
label = "psu:green:status";
default-state = "off";
gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>;
};
};
};
&gpio {
status = "okay";
gpio-line-names =
/*A0-A7*/ "CASE_OPEN_DNP","CASE_OPEN_FAULT_RST_DNP","BEZEL_ON_PWR_P3V3","PWM_PWRGD_EXP_EN","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","",
/*B0-B7*/ "","","","","","","","",
/*C0-C7*/ "","","","","","","","",
/*D0-D7*/ "","","","","","","","",
/*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","LED_TEMP_STATUS_R","LED_TEMP_STATUS_G","LED_PWR_STATUS_R","LED_PWR_STATUS_G",
/*F0-F7*/ "NMI_OUT","CPU1_DISABLE_COD","","","SKT0_FAULT_LED_DNP","SKT1_FAULT_LED_DNP","RST_RGMII_PHYRST_DNP","",
/*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","SPI_BMC_BOOT_HD","IRQ_NMI_EVENT","SPI_BMC_BOOT_WP","SPI_BMC_BOOT_WP1","",
/*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS",
/*I0-I7*/ "","","","","","","","",
/*J0-J7*/ "","","","","","","","",
/*K0-K7*/ "","","","","","","","",
/*L0-L7*/ "","","","","","","","",
/*M0-M7*/ "SEL_FLASH_SOFT","STATUS_SEL_BMC","","","BMC_WDT_P","ID_BUTTON","PS_PWROK","",
/*N0-N7*/ "","","","","","","","",
/*O0-O7*/ "","","","","","","","",
/*P0-P7*/ "","","","","","","SPI_BIOS_ACTIVE_FLASH_SEL","STATUS_SEL_BIOS",
/*Q0-Q7*/ "","","","","","","","",
/*R0-R7*/ "_SPI_BMC_BOOT_CS1","","","","","","","",
/*S0-S7*/ "_SPI2_BMC_CS1","RSR_A_SMBEXP_RST_INT","RSR_B_SMBEXP_RST_INT","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "","","","","","","","",
/*W0-W7*/ "","","","","","","","",
/*X0-X7*/ "","","","","","","","",
/*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","",
/*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","",
/*AA0-AA7*/ "CPU_CLK_MUX_SEL","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE",
/*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","BMC_WDT_RST1","BMC_WDT_RST2","","","","",
/*AC0-AC7*/ "","","","","","","","";
};
&sgpio {
ngpios = <80>;
bus-frequency = <2000000>;
status = "okay";
/* SGPIO lines. even: input, odd: output */
gpio-line-names =
/*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","",
/*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","",
/*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","",
/*D0-D7*/ "","","","","","","","","","","","","","","","",
/*E0-E7*/ "","","","","","","","","","","","","","","","",
/*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","",
/*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","",
/*H0-H7*/ "","","","","","","","","","","","","","","","",
/*I0-I7*/ "","","","","","","","","","","","","","","","",
/*J0-J7*/ "","","","","","","","","","","","","","","","";
};
&i2c11 {
/* SMB_BMC_MGMT_LVC3 */
gpio@21 {
compatible = "nxp,pcal9535";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
/*IO0.0-0.7*/ "ETH3_CLK_REQ", "ETH2_CLK_REQ", "RSR_A_PCIE_X16_2_PRSNT", "RSR_B_PCIE_X16_2_PRSNT", "", "RSR_B_PCIE_X8_3_PRSNT", "RSR_B_PCIE_X8_4_PRSNT", "RSR_B_PCIE_X16_PRSNT_N",
/*IO1.0-1.7*/ "RSR_B_PCIE_X8_2_PRSNT", "RSR_B_PCIE_X8_1_PRSNT", "NIC_1_PE_BUF_PRSNT", "RSR_A_PCIE_X16_PRSNT", "RSR_A_PCIE_X8_3_PRSNT", "RSR_A_PCIE_X8_2_PRSNT", "RSR_A_PCIE_X8_1_PRSNT_N", "";
};
gpio@23 {
compatible = "nxp,pcal9535";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
/*IO0.0-0.7*/ "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "FM_LINK_WIDTH_ID0", "", "", "",
/*IO1.0-1.7*/ "", "", "", "", "", "", "", "";
};
gpio@27 {
compatible = "nxp,pca9698";
reg = <0x27>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
/*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX",
/*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0",
/*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "PWRGD_PVCCIN_CPU1", "PWRGD_PVCCSA_CPU1", "PWRGD_PVCCIO_CPU1",
/*IO3.0-3.7*/ "PWRGD_PVMCP_CPU1", "PWRGD_P1V0_CPU1", "PWRGD_PVDDQ_GHJ_CPU1", "PWRGD_PVPP_GHJ_CPU1", "PWRGD_PVTT_GHJ_CPU1", "PWRGD_PVDDQ_KLM_CPU1", "PWRGD_PVPP_KLM_CPU1", "PWRGD_PVTT_KLM_CPU1",
/*IO4.0-4.7*/ "PCH_PWR_RESET_N", "FM_BOARD_SKU_ID0", "FM_BOARD_SKU_ID1", "FM_BOARD_SKU_ID2", "FM_BOARD_SKU_ID3", "FM_BOARD_SKU_ID4", "FM_BOARD_REV_ID0", "FM_BOARD_REV_ID1";
};
gpio@39 {
compatible = "nxp,pca9554";
reg = <0x39>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
/*IO0.0-0.7*/ "FAN_FAULT_0", "FAN_FAULT_1", "FAN_FAULT_2", "FAN_FAULT_3", "FAN_FAULT_4", "FAN_FAULT_5", "FAN_FAULT_6", "";
};
};
&i2c13 {
/* SMB_PCIE2_STBY_LVC3 */
mux-expa@70 {
compatible = "nxp,pca9548";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect;
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
rsra-mux@72 {
compatible = "nxp,pca9548";
reg = <0x72>;
#address-cells = <1>;
#size-cells = <0>;
i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
at24@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
size = <8192>;
address-width = <16>;
};
};
};
};
};
mux-sata@71 {
compatible = "nxp,pca9543";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect;
};
};
&i2c2 {
/* SMB_PCIE_STBY_LVC3 */
mux-expb@71 {
compatible = "nxp,pca9548";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
rsrb-mux@72 {
compatible = "nxp,pca9548";
reg = <0x72>;
#address-cells = <1>;
#size-cells = <0>;
i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
at24@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
size = <8192>;
address-width = <16>;
};
};
};
at24@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
size = <8192>;
address-width = <16>;
};
};
};
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
&pinctrl_pwm2_default &pinctrl_pwm3_default
&pinctrl_pwm4_default &pinctrl_pwm5_default
&pinctrl_pwm6_default>;
fan@0 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x00 0x07>;
};
fan@1 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x01 0x08>;
};
fan@2 {
reg = <0x02>;
aspeed,fan-tach-ch = /bits/ 8 <0x02 0x09>;
};
fan@3 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0A>;
};
fan@4 {
reg = <0x04>;
aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0B>;
};
fan@5 {
reg = <0x05>;
aspeed,fan-tach-ch = /bits/ 8 <0x05 0x0C>;
};
fan@6 {
reg = <0x06>;
aspeed,fan-tach-ch = /bits/ 8 <0x06 0x0D>;
};
};

154
arch/arm/boot/dts/aspeed-bmc-vegman-sx20.dts Normal file
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@ -0,0 +1,154 @@
// SPDX-License-Identifier: GPL-2.0+
// Copyright (C) 2021 YADRO
/dts-v1/;
#include "aspeed-bmc-vegman.dtsi"
/ {
model = "YADRO VEGMAN Sx20 BMC";
compatible = "yadro,vegman-sx20-bmc", "aspeed,ast2500";
};
&gpio {
status = "okay";
gpio-line-names =
/*A0-A7*/ "CHASSIS_INTRUSION","CASE_OPEN_FAULT_RST","","","SPEAKER_BMC","FM_FORCE_BMC_UPDATE","","",
/*B0-B7*/ "","","","","","","","",
/*C0-C7*/ "","","","","","","","",
/*D0-D7*/ "","","","","","","","",
/*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","","","","",
/*F0-F7*/ "NMI_OUT","CPU1_DISABLE_COD","","","SKT0_FAULT_LED","SKT1_FAULT_LED","RST_RGMII_PHYRST_DNP","",
/*G0-G7*/ "CPU_ERR2","CPU_CATERR","PCH_BMC_THERMTRIP","","IRQ_NMI_EVENT","","","",
/*H0-H7*/ "PWRGD_P3V3_RISER1","PWRGD_P3V3_RISER2","PWRGD_P3V3_RISER3","","MIO_BIOS_SEL","_SPI_FLASH_HOLD","_SPI_FLASH_WP","FM_240VA_STATUS",
/*I0-I7*/ "","","","","","","","",
/*J0-J7*/ "","","","","","","","",
/*K0-K7*/ "","","","","","","","",
/*L0-L7*/ "","","","","","","","",
/*M0-M7*/ "","","","","BMC_GPU_RISER_ID1","BMC_GPU_RISER_ID0","","",
/*N0-N7*/ "","","","","","","","",
/*O0-O7*/ "","","","","","","","_SPI2_BMC_CS_SEL",
/*P0-P7*/ "","P12V_HDDS_A_EN","P12V_HDDS_B_EN","P5V_HDDS_A_EN","PWRGD_P5V_HDDS_A","P5V_HDDS_B_EN","PWRGD_P5V_HDDS_B","",
/*Q0-Q7*/ "","","","","","","","",
/*R0-R7*/ "_SPI_RMM4_LITE_CS","","","","","","","",
/*S0-S7*/ "_SPI2_BMC_CS1","","","IRQ_SML0_ALERT_MUX","FP_LED_STATUS_GREEN","FP_LED_STATUS_AMBER","FP_ID_LED","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "","","","","","","","",
/*W0-W7*/ "","","","","","","","",
/*X0-X7*/ "","","","","","","","",
/*Y0-Y7*/ "SIO_S3","SIO_S5","","SIO_ONCONTROL","","","","",
/*Z0-Z7*/ "FM_BMC_PWR_BTN","SIO_POWER_GOOD","FM_BMC_PWRBTN_OUT","FM_BMC_PCH_SCI_LPC","","","","",
/*AA0-AA7*/ "CPU_CLK_MUX_SEL","IRQ_SML1_PMBUS_ALERT","FM_PVCCIN_CPU0_PWR_IN_ALERT","FM_PVCCIN_CPU1_PWR_IN_ALERT","BMC_SYS_PWR_FAULT","BMC_SYS_PWR_OK","SMI","POST_COMPLETE",
/*AB0-AB7*/ "FM_CPU_BMCINIT","NMI_BUTTON","ID_BUTTON","PS_PWROK","","","","",
/*AC0-AC7*/ "","","","","","","","";
};
&sgpio {
ngpios = <80>;
bus-frequency = <2000000>;
status = "okay";
/* SGPIO lines. even: input, odd: output */
gpio-line-names =
/*A0-A7*/ "CPU1_PRESENCE","","CPU1_THERMTRIP","","CPU1_VRHOT","","CPU1_FIVR_FAULT","","CPU1_MEM_ABCD_VRHOT","","CPU1_MEM_EFGH_VRHOT","","","","","",
/*B0-B7*/ "CPU1_MISMATCH","","CPU1_MEM_THERM_EVENT","","CPU2_PRESENCE","","CPU2_THERMTRIP","","CPU2_VRHOT","","CPU2_FIVR_FAULT","","CPU2_MEM_ABCD_VRHOT","","CPU2_MEM_EFGH_VRHOT","",
/*C0-C7*/ "","","","","CPU2_MISMATCH","","CPU2_MEM_THERM_EVENT","","","","","","","","","",
/*D0-D7*/ "","","","","","","","","","","","","","","","",
/*E0-E7*/ "","","","","","","","","","","","","","","","",
/*F0-F7*/ "SGPIO_PLD_MINOR_REV_BIT0","","SGPIO_PLD_MINOR_REV_BIT1","","SGPIO_PLD_MINOR_REV_BIT2","","SGPIO_PLD_MINOR_REV_BIT3","","SGPIO_PLD_MAJOR_REV_BIT0","","SGPIO_PLD_MAJOR_REV_BIT1","","SGPIO_PLD_MAJOR_REV_BIT2","","SGPIO_PLD_MAJOR_REV_BIT3","",
/*G0-G7*/ "MAIN_PLD_MINOR_REV_BIT0","","MAIN_PLD_MINOR_REV_BIT1","","MAIN_PLD_MINOR_REV_BIT2","","MAIN_PLD_MINOR_REV_BIT3","","MAIN_PLD_MAJOR_REV_BIT0","","MAIN_PLD_MAJOR_REV_BIT1","","MAIN_PLD_MAJOR_REV_BIT2","","MAIN_PLD_MAJOR_REV_BIT3","",
/*H0-H7*/ "","","","","","","","","","","","","","","","",
/*I0-I7*/ "","","","","","","","","","","","","","","","",
/*J0-J7*/ "","","","","","","","","","","","","","","","";
};
&i2c11 {
/* SMB_BMC_MGMT_LVC3 */
gpio@21 {
compatible = "nxp,pcal9535";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
/*IO0.0-0.7*/ "", "", "CPU1_PE3_0_SLOT_PRSNT", "", "CPU1_PE1_GPU_PRSNT", "CPU1_PE3_1_SLOT_PRSNT", "PE_PCH_MEZ_PRSNT", "CPU0_PE3_1_SLOT_PRSNT",
/*IO1.0-1.7*/ "CPU0_PE1_GPU_PRSNT", "CPU0_PE2_NVME2_PRSNT", "CPU1_PE2_NVME3_PRSNT", "CPU1_PE2_SLOT_PRSNT", "CPU1_PE2_NVME4_PRSNT", "", "CPU0_PE2_NVME1_PRSNT", "CPU0_PE3_0_RAID_PRSNT";
};
gpio@27 {
compatible = "nxp,pca9698";
reg = <0x27>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
/*IO0.0-0.7*/ "PWRGD_PS_PWROK", "PWRGD_DSW_PWROK", "PWRGD_P5V_AUX", "PWRGD_P3V3_AUX", "PWRGD_P5V", "PWRGD_P3V3", "PWRGD_P1V8_PCH_AUX", "PWRGD_PCH_PVNN_AUX",
/*IO1.0-1.7*/ "PWRGD_P1V05_PCH_AUX", "PWRGD_PCH_AUX_VRS", "PWRGD_PVCCIN_CPU0", "PWRGD_PVCCSA_CPU0", "PWRGD_PVCCIO_CPU0", "PWRGD_PVMCP_CPU0", "PWRGD_P1V0_CPU0", "PWRGD_PVDDQ_ABC_CPU0",
/*IO2.0-2.7*/ "PWRGD_PVPP_ABC_CPU0", "PWRGD_PVTT_ABC_CPU0", "PWRGD_PVDDQ_DEF_CPU0", "PWRGD_PVPP_DEF_CPU0", "PWRGD_PVTT_DEF_CPU0", "PWRGD_PVCCIN_CPU1", "PWRGD_PVCCSA_CPU1", "PWRGD_PVCCIO_CPU1",
/*IO3.0-3.7*/ "PWRGD_PVMCP_CPU1", "PWRGD_P1V0_CPU1", "PWRGD_PVDDQ_GHJ_CPU1", "PWRGD_PVPP_GHJ_CPU1", "PWRGD_PVTT_GHJ_CPU1", "PWRGD_PVDDQ_KLM_CPU1", "PWRGD_PVPP_KLM_CPU1", "PWRGD_PVTT_KLM_CPU1",
/*IO4.0-4.7*/ "PWRGD_P5V_HDDS_A_R", "PWRGD_P5V_HDDS_B_R", "", "", "", "", "", "";
};
};
&i2c13 {
/* SMB_PCIE2_STBY_LVC3 */
mux-expa@73 {
compatible = "nxp,pca9545";
reg = <0x73>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect;
};
mux-sata@71 {
compatible = "nxp,pca9543";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect;
};
};
&i2c2 {
/* SMB_PCIE_STBY_LVC3 */
mux-expb@71 {
compatible = "nxp,pca9545";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect;
};
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
&pinctrl_pwm2_default &pinctrl_pwm3_default
&pinctrl_pwm4_default &pinctrl_pwm5_default
&pinctrl_pwm6_default>;
fan@0 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x00>;
};
fan@1 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x01>;
};
fan@2 {
reg = <0x02>;
aspeed,fan-tach-ch = /bits/ 8 <0x02>;
};
fan@3 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x03>;
};
fan@4 {
reg = <0x04>;
aspeed,fan-tach-ch = /bits/ 8 <0x04>;
};
fan@5 {
reg = <0x05>;
aspeed,fan-tach-ch = /bits/ 8 <0x05>;
};
fan@6 {
reg = <0x06>;
aspeed,fan-tach-ch = /bits/ 8 <0x06>;
};
};

311
arch/arm/boot/dts/aspeed-bmc-vegman.dtsi Normal file
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@ -0,0 +1,311 @@
// SPDX-License-Identifier: GPL-2.0+
// Copyright (C) 2021 YADRO
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
aliases {
serial4 = &uart5;
};
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory@80000000 {
reg = <0x80000000 0x20000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
video_engine_memory: jpegbuffer {
size = <0x02000000>; /* 32M */
alignment = <0x01000000>;
compatible = "shared-dma-pool";
reusable;
};
ramoops@9eff0000{
compatible = "ramoops";
reg = <0x9eff0000 0x10000>;
record-size = <0x2000>;
console-size = <0x2000>;
};
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
<&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
<&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>,
<&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>;
};
leds {
compatible = "gpio-leds";
identify {
label = "platform:blue:indicator";
linux,default-trigger = "heartbeat";
gpios = <&gpio ASPEED_GPIO(S, 6) GPIO_ACTIVE_LOW>;
};
status_amber {
label = "platform:red:status";
default-state = "off";
gpios = <&gpio ASPEED_GPIO(S, 5) GPIO_ACTIVE_LOW>;
};
status_green {
label = "platform:green:status";
default-state = "off";
gpios = <&gpio ASPEED_GPIO(S, 4) GPIO_ACTIVE_LOW>;
};
power_fault {
label = "platform:red:power";
default-state = "off";
gpios = <&gpio ASPEED_GPIO(AA, 4) GPIO_ACTIVE_LOW>;
};
power_ok {
label = "platform:green:power";
default-state = "off";
gpios = <&gpio ASPEED_GPIO(AA, 5) GPIO_ACTIVE_LOW>;
};
};
beeper {
compatible = "pwm-beeper";
pwms = <&timer 5 1000000 0>;
};
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
label = "bmc";
m25p,fast-read;
#include "openbmc-flash-layout-64.dtsi"
};
};
&spi2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2ck_default
&pinctrl_spi2miso_default
&pinctrl_spi2mosi_default
&pinctrl_spi2cs0_default>;
flash@0 {
status = "okay";
label = "bios";
m25p,fast-read;
};
};
&mac0 {
status = "okay";
use-ncsi;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
};
&mac1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
phy-mode = "rgmii";
phy-handle = <&phy>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy: ethernet-phy@1 {
/* KSZ9131 */
compatible = "ethernet-phy-id0022.1640";
reg = <1>;
micrel,led-mode = <0>;
};
};
};
&vhub {
status = "okay";
};
&adc {
status = "okay";
};
&video {
status = "okay";
memory-region = <&video_engine_memory>;
};
&sdmmc {
status = "okay";
};
&sdhci1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd2_default>;
disable-wp;
};
&timer {
fttmr010,pwm-outputs = <5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_timer5_default>;
#pwm-cells = <3>;
status = "okay";
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default
&pinctrl_nrts1_default
&pinctrl_ndtr1_default
&pinctrl_ndsr1_default
&pinctrl_ncts1_default
&pinctrl_ndcd1_default
&pinctrl_nri1_default>;
};
&uart5 {
status = "okay";
};
&vuart {
status = "okay";
};
&kcs3 {
aspeed,lpc-io-reg = <0xCA2>;
status = "okay";
};
&kcs4 {
aspeed,lpc-io-reg = <0xCA4>;
status = "okay";
};
&lpc_snoop {
snoop-ports = <0x80>;
status = "okay";
};
&uart_routing {
status = "okay";
};
&uart2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <>;
};
&uart3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <>;
};
&uart4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <>;
};
&i2c0 {
/* SMB_IPMB_STBY_LVC3 */
multi-master;
status = "okay";
};
&i2c1 {
/* SMB_CHASSENSOR_STBY_LVC3 */
status = "okay";
};
&i2c2 {
/* SMB_PCIE_STBY_LVC3 */
status = "okay";
};
&i2c3 {
/* SMB_HOST_STBY_LVC3 */
multi-master;
status = "okay";
};
&i2c4 {
/* BMC_PMBUS2_STBY */
status = "okay";
};
&i2c5 {
/* SMB_SMLINK0_STBY_LVC3 */
bus-frequency = <1000000>;
multi-master;
status = "okay";
};
&i2c6 {
/* SMB_TEMPSENSOR_STBY_LVC3 */
multi-master;
status = "okay";
};
&i2c7 {
/* SMB_SM_PMB1_SML1_STBY_LVC3 */
multi-master;
status = "okay";
};
&i2c9 {
/* SMB_BMC_ETH3_LVC3 */
status = "okay";
};
&i2c10 {
/* SMB_BMC_ETH2_LVC3 */
status = "okay";
};
&i2c11 {
/* SMB_BMC_MGMT_LVC3 */
status = "okay";
at24@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
size = <8192>;
address-width = <16>;
};
};
&i2c12 {
/* SMB_BMC_FAULT_EXP_LVC3 */
status = "okay";
};
&i2c13 {
/* SMB_PCIE2_STBY_LVC3 */
status = "okay";
};

7
arch/arm/boot/dts/aspeed-g4.dtsi
View File

@ -381,6 +381,13 @@ ibt: ibt@140 {
compatible = "aspeed,ast2400-ibt-bmc";
reg = <0x140 0x18>;
interrupts = <8>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
uart_routing: uart-routing@9c {
compatible = "aspeed,ast2400-uart-routing";
reg = <0x9c 0x4>;
status = "disabled";
};
};

11
arch/arm/boot/dts/aspeed-g5.dtsi
View File

@ -446,6 +446,7 @@ kcs1: kcs@24 {
compatible = "aspeed,ast2500-kcs-bmc-v2";
reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
interrupts = <8>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
@ -453,6 +454,7 @@ kcs2: kcs@28 {
compatible = "aspeed,ast2500-kcs-bmc-v2";
reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
interrupts = <8>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
@ -460,6 +462,7 @@ kcs3: kcs@2c {
compatible = "aspeed,ast2500-kcs-bmc-v2";
reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
interrupts = <8>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
@ -467,6 +470,7 @@ kcs4: kcs@114 {
compatible = "aspeed,ast2500-kcs-bmc-v2";
reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>;
interrupts = <8>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
@ -491,6 +495,12 @@ lpc_reset: reset-controller@98 {
#reset-cells = <1>;
};
uart_routing: uart-routing@9c {
compatible = "aspeed,ast2500-uart-routing";
reg = <0x9c 0x4>;
status = "disabled";
};
lhc: lhc@a0 {
compatible = "aspeed,ast2500-lhc";
reg = <0xa0 0x24 0xc8 0x8>;
@ -501,6 +511,7 @@ ibt: ibt@140 {
compatible = "aspeed,ast2500-ibt-bmc";
reg = <0x140 0x18>;
interrupts = <8>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
};

36
arch/arm/boot/dts/aspeed-g6.dtsi
View File

@ -364,6 +364,31 @@ xdma: xdma@1e6e7000 {
status = "disabled";
};
adc0: adc@1e6e9000 {
compatible = "aspeed,ast2600-adc0";
reg = <0x1e6e9000 0x100>;
clocks = <&syscon ASPEED_CLK_APB2>;
resets = <&syscon ASPEED_RESET_ADC>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
status = "disabled";
};
adc1: adc@1e6e9100 {
compatible = "aspeed,ast2600-adc1";
reg = <0x1e6e9100 0x100>;
clocks = <&syscon ASPEED_CLK_APB2>;
resets = <&syscon ASPEED_RESET_ADC>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
status = "disabled";
};
sbc: secure-boot-controller@1e6f2000 {
compatible = "aspeed,ast2600-sbc";
reg = <0x1e6f2000 0x1000>;
};
gpio0: gpio@1e780000 {
#gpio-cells = <2>;
gpio-controller;
@ -500,6 +525,7 @@ kcs1: kcs@24 {
compatible = "aspeed,ast2500-kcs-bmc-v2";
reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
kcs_chan = <1>;
status = "disabled";
};
@ -508,6 +534,7 @@ kcs2: kcs@28 {
compatible = "aspeed,ast2500-kcs-bmc-v2";
reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
@ -515,6 +542,7 @@ kcs3: kcs@2c {
compatible = "aspeed,ast2500-kcs-bmc-v2";
reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
@ -522,6 +550,7 @@ kcs4: kcs@114 {
compatible = "aspeed,ast2500-kcs-bmc-v2";
reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
@ -551,10 +580,17 @@ lpc_reset: reset-controller@98 {
#reset-cells = <1>;
};
uart_routing: uart-routing@98 {
compatible = "aspeed,ast2600-uart-routing";
reg = <0x98 0x8>;
status = "disabled";
};
ibt: ibt@140 {
compatible = "aspeed,ast2600-ibt-bmc";
reg = <0x140 0x18>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
};

147
arch/arm/boot/dts/at91-lmu5000.dts Normal file
View File

@ -0,0 +1,147 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree file for CalAmp LMU5000 board
*
* Copyright (C) 2013 Adam Porter <porter.adam@gmail.com>
*/
/dts-v1/;
#include "at91sam9g20.dtsi"
/ {
model = "CalAmp LMU5000";
compatible = "calamp,lmu5000", "atmel,at91sam9g20", "atmel,at91sam9";
chosen {
bootargs = "mem=64M console=ttyS0,115200 rootfstype=jffs2";
};
memory {
reg = <0x20000000 0x4000000>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
main_clock: clock@0 {
compatible = "atmel,osc", "fixed-clock";
clock-frequency = <18432000>;
};
};
};
&dbgu {
status = "okay";
};
&ebi {
status = "okay";
nand_controller: nand-controller {
pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
pinctrl-names = "default";
status = "okay";
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "soft";
nand-on-flash-bbt;
label = "atmel_nand";
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
kernel@0 {
label = "kernel";
reg = <0x0 0x400000>;
};
rootfs@400000 {
label = "rootfs";
reg = <0x400000 0x3C00000>;
};
user1@4000000 {
label = "user1";
reg = <0x4000000 0x2000000>;
};
user2@6000000 {
label = "user2";
reg = <0x6000000 0x2000000>;
};
};
};
};
};
&macb0 {
phy-mode = "mii";
status = "okay";
};
&pinctrl {
board {
pinctrl_pck0_as_mck: pck0_as_mck {
atmel,pins = <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
usb0 {
pinctrl_usb1_vbus_gpio: usb0_vbus_gpio {
atmel,pins = <AT91_PIOC 5 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
};
&ssc0 {
status = "okay";
pinctrl-0 = <&pinctrl_ssc0_tx>;
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&usart0 {
pinctrl-0 =
<&pinctrl_usart0
&pinctrl_usart0_rts
&pinctrl_usart0_cts
&pinctrl_usart0_dtr_dsr
&pinctrl_usart0_dcd
&pinctrl_usart0_ri>;
status = "okay";
};
&usart2 {
status = "okay";
};
&usb0 {
num-ports = <2>;
status = "okay";
};
&usb1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_vbus_gpio>;
atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&watchdog {
status = "okay";
};

181
arch/arm/boot/dts/at91-q5xr5.dts Normal file
View File

@ -0,0 +1,181 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree file for Exegin Q5xR5 board
*
* Copyright (C) 2014 Owen Kirby <osk@exegin.com>
*/
/dts-v1/;
#include "at91sam9g20.dtsi"
/ {
model = "Exegin Q5x (rev5)";
compatible = "exegin,q5xr5", "atmel,at91sam9g20", "atmel,at91sam9";
chosen {
bootargs = "console=ttyS0,115200 rootfstype=squashfs,jffs2";
};
memory {
reg = <0x20000000 0x0>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
main_clock: clock@0 {
compatible = "atmel,osc", "fixed-clock";
clock-frequency = <18432000>;
};
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <18432000>;
};
};
};
&dbgu {
status = "okay";
};
&ebi {
status = "okay";
flash: flash@0 {
compatible = "cfi-flash";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0 0x1000000 0x800000>;
bank-width = <2>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
kernel@0 {
label = "kernel";
reg = <0x0 0x200000>;
};
rootfs@200000 {
label = "rootfs";
reg = <0x200000 0x600000>;
};
};
};
};
&macb0 {
phy-mode = "mii";
status = "okay";
};
&pinctrl {
board {
pinctrl_pck0_as_mck: pck0_as_mck {
atmel,pins = <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
spi0 {
pinctrl_spi0: spi0-0 {
atmel,pins =
<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_spi0_npcs0: spi0_npcs0 {
atmel,pins = <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_spi0_npcs1: spi0_npcs1 {
atmel,pins = <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
spi1 {
pinctrl_spi1: spi1-0 {
atmel,pins =
<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_spi1_npcs0: spi1_npcs0 {
atmel,pins = <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_spi1_npcs1: spi1_npcs1 {
atmel,pins = <AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0 &pinctrl_spi0_npcs0 &pinctrl_spi0_npcs1>;
cs-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>, <&pioC 11 GPIO_ACTIVE_LOW>, <0>, <0>;
status = "okay";
m25p80@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
at91boot@0 {
label = "at91boot";
reg = <0x0 0x4000>;
};
uenv@4000 {
label = "uboot-env";
reg = <0x4000 0x4000>;
};
uboot@8000 {
label = "uboot";
reg = <0x8000 0x3E000>;
};
};
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1 &pinctrl_spi1_npcs0 &pinctrl_spi1_npcs1>;
cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>, <&pioC 5 GPIO_ACTIVE_LOW>, <0>, <0>;
status = "okay";
};
&usart0 {
pinctrl-0 =
<&pinctrl_usart0
&pinctrl_usart0_rts
&pinctrl_usart0_cts
&pinctrl_usart0_dtr_dsr
&pinctrl_usart0_dcd
&pinctrl_usart0_ri>;
status = "okay";
};
&usb0 {
num-ports = <2>;
status = "okay";
};
&usb1 {
status = "okay";
};
&watchdog {
status = "okay";
};

12
arch/arm/boot/dts/at91-sama5d27_som1.dtsi
View File

@ -8,6 +8,7 @@
*/
#include "sama5d2.dtsi"
#include "sama5d2-pinfunc.h"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Atmel SAMA5D27 SoM1";
@ -95,8 +96,11 @@ ethernet-phy@7 {
i2c0: i2c@f8028000 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
at24@50 {
@ -113,6 +117,12 @@ pinctrl_i2c0_default: i2c0_default {
bias-disable;
};
pinctrl_i2c0_gpio: i2c0_gpio {
pinmux = <PIN_PD21__GPIO>,
<PIN_PD22__GPIO>;
bias-disable;
};
pinctrl_qspi1_default: qspi1_default {
sck_cs {
pinmux = <PIN_PB5__QSPI1_SCK>,

23
arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
View File

@ -130,8 +130,11 @@ i2c3: i2c@600 {
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_mikrobus_i2c>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
sda-gpios = <&pioA PIN_PA24 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA PIN_PA23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
};
@ -215,8 +218,11 @@ i2c1: i2c@fc028000 {
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
sda-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA PIN_PD5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
@ -252,6 +258,13 @@ pinctrl_i2c1_default: i2c1_default {
bias-disable;
};
pinctrl_i2c1_gpio: i2c1_gpio {
pinmux = <PIN_PD4__GPIO>,
<PIN_PD5__GPIO>;
bias-disable;
};
pinctrl_isc_base: isc_base {
pinmux = <PIN_PC21__ISC_PCK>,
<PIN_PC22__ISC_VSYNC>,
@ -441,6 +454,12 @@ pinctrl_mikrobus_i2c: mikrobus1_i2c {
bias-disable;
};
pinctrl_i2c3_gpio: i2c3_gpio {
pinmux = <PIN_PA24__GPIO>,
<PIN_PA23__GPIO>;
bias-disable;
};
pinctrl_flx4_default: flx4_uart_default {
pinmux = <PIN_PC28__FLEXCOM4_IO0>,
<PIN_PC29__FLEXCOM4_IO1>,

70
arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
View File

@ -30,6 +30,14 @@ main_xtal {
clock-frequency = <24000000>;
};
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-wilc1000";
reset-gpios = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>;
powerdown-gpios = <&pioA PIN_PA29 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pinctrl_wilc_pwrseq>;
pinctrl-names = "default";
};
};
&flx1 {
@ -310,5 +318,67 @@ pinctrl_qspi1_default: qspi1_default {
<PIN_PB10__QSPI1_IO3>;
bias-pull-up;
};
pinctrl_sdmmc1_default: sdmmc1_default {
cmd-data {
pinmux = <PIN_PA28__SDMMC1_CMD>,
<PIN_PA18__SDMMC1_DAT0>,
<PIN_PA19__SDMMC1_DAT1>,
<PIN_PA20__SDMMC1_DAT2>,
<PIN_PA21__SDMMC1_DAT3>;
bias-disable;
};
conf-ck {
pinmux = <PIN_PA22__SDMMC1_CK>;
bias-disable;
};
};
pinctrl_wilc_default: wilc_default {
conf-irq {
pinmux = <PIN_PB25__GPIO>;
bias-disable;
};
};
pinctrl_wilc_pwrseq: wilc_pwrseq {
conf-ce-nrst {
pinmux = <PIN_PA27__GPIO>,
<PIN_PA29__GPIO>;
bias-disable;
};
conf-rtcclk {
pinmux = <PIN_PB13__PCK1>;
bias-disable;
};
};
};
&sdmmc1 {
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc1_default>;
mmc-pwrseq = <&wifi_pwrseq>;
no-1-8-v;
non-removable;
bus-width = <4>;
status = "okay";
wilc: wifi@0 {
reg = <0>;
compatible = "microchip,wilc1000";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wilc_default>;
clocks = <&pmc PMC_TYPE_SYSTEM 9>;
clock-names = "rtc";
interrupts = <PIN_PB25 IRQ_TYPE_NONE>;
interrupt-parent = <&pioA>;
assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>;
assigned-clock-rates = <32768>;
};
};

22
arch/arm/boot/dts/at91-sama5d2_icp.dts
View File

@ -307,8 +307,11 @@ regulator-state-mem {
};
&i2c0 { /* mikrobus i2c */
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_mikrobus_i2c>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
status = "okay";
@ -316,8 +319,11 @@ &i2c0 { /* mikrobus i2c */
&i2c1 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
sda-gpios = <&pioA PIN_PD19 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA PIN_PD20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
status = "okay";
@ -402,6 +408,12 @@ pinctrl_i2c1_default: i2c1_default {
bias-disable;
};
pinctrl_i2c1_gpio: i2c1_gpio {
pinmux = <PIN_PD19__GPIO>,
<PIN_PD20__GPIO>;
bias-disable;
};
pinctrl_key_gpio_default: key_gpio_default {
pinmux = <PIN_PD0__GPIO>;
bias-pull-up;
@ -463,6 +475,12 @@ pinctrl_mikrobus_i2c: mikrobus_i2c {
bias-disable;
};
pinctrl_i2c0_gpio: i2c0_gpio {
pinmux = <PIN_PD21__GPIO>,
<PIN_PD22__GPIO>;
bias-disable;
};
pinctrl_mikrobus1_an: mikrobus1_an {
pinmux = <PIN_PD26__GPIO>;
bias-disable;

5
arch/arm/boot/dts/at91-sama5d2_xplained.dts
View File

@ -66,7 +66,7 @@ sdmmc0: sdio-host@a0000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_default>;
non-removable;
mmc-ddr-1_8v;
mmc-ddr-3_3v;
status = "okay";
};
@ -619,10 +619,9 @@ cmd_data {
bias-disable;
};
ck_cd_rstn_vddsel {
ck_cd_rstn {
pinmux = <PIN_PA0__SDMMC0_CK>,
<PIN_PA10__SDMMC0_RSTN>,
<PIN_PA11__SDMMC0_VDDSEL>,
<PIN_PA13__SDMMC0_CD>;
bias-disable;
};

209
arch/arm/boot/dts/at91-sama5d3_ksz9477_evb.dts Normal file
View File

@ -0,0 +1,209 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2021 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
*/
/dts-v1/;
#include "sama5d36.dtsi"
/ {
model = "EVB-KSZ9477";
compatible = "microchip,sama5d3-ksz9477-evb", "atmel,sama5d36",
"atmel,sama5d3", "atmel,sama5";
chosen {
stdout-path = &dbgu;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_vcc_mmc0: regulator-mmc0 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mcc0_vcc>;
regulator-name = "mmc0-vcc";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
gpio = <&pioE 2 GPIO_ACTIVE_LOW>;
};
};
&dbgu {
status = "okay";
};
&ebi {
pinctrl-0 = <&pinctrl_ebi_nand_addr>;
pinctrl-names = "default";
status = "okay";
};
&i2c0 {
pinctrl-0 = <&pinctrl_i2c0_pu>;
status = "okay";
};
&macb0 {
phy-mode = "rgmii";
status = "okay";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&main_xtal {
clock-frequency = <12000000>;
};
&mmc0 {
pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3
&pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <8>;
cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>;
disable-wp;
vmmc-supply = <&reg_vcc_mmc0>;
vqmmc-supply = <&reg_3v3>;
};
};
&nand_controller {
status = "okay";
nand@3 {
reg = <0x3 0x0 0x2>;
atmel,rb = <0>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-on-flash-bbt;
label = "atmel_nand";
};
};
&slow_xtal {
clock-frequency = <32768>;
};
&spi0 {
cs-gpios = <&pioD 13 GPIO_ACTIVE_LOW>, <0>, <0>,
<&pioD 16 GPIO_ACTIVE_LOW>;
status = "okay";
};
&spi1 {
pinctrl-0 = <&pinctrl_spi_ksz>;
cs-gpios = <&pioC 25 GPIO_ACTIVE_LOW>;
status = "okay";
switch@0 {
compatible = "microchip,ksz9477";
reg = <0>;
spi-max-frequency = <1000000>;
spi-cpha;
spi-cpol;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@4 {
reg = <4>;
label = "lan5";
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&macb0>;
phy-mode = "rgmii-txid";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};
&usb0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usba_vbus>;
atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&pinctrl {
board {
pinctrl_i2c0_pu: i2c0-pu {
atmel,pins =
<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
<AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_mmc0_cd: mmc0-cd {
atmel,pins = <AT91_PIOE 0 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
pinctrl_mcc0_vcc: mmc0-vcc {
atmel,pins = <AT91_PIOE 2 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
pinctrl_spi_ksz: spi-ksz {
atmel,pins =
<
/* SPI1_MISO */
AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
/* SPI1_MOSI */
AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE
/* SPI1_SPCK */
AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE
/* SPI CS */
AT91_PIOC 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
/* switch IRQ */
AT91_PIOB 28 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH
/* switch PME_N, SoC IN */
AT91_PIOC 30 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP
/* switch RST */
AT91_PIOC 31 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH
>;
};
pinctrl_usba_vbus: usba-vbus {
atmel,pins =
<AT91_PIOE 9 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
};
};
};

93
arch/arm/boot/dts/at91-sama7g5ek.dts
View File

@ -13,6 +13,7 @@
#include "sama7g5.dtsi"
#include <dt-bindings/mfd/atmel-flexcom.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/at91.h>
/ {
model = "Microchip SAMA7G5-EK";
@ -122,10 +123,71 @@ spdif_out: spdif-out {
};
};
&adc {
vddana-supply = <&vddout25>;
vref-supply = <&vddout25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mikrobus1_an_default &pinctrl_mikrobus2_an_default>;
status = "okay";
};
&cpu0 {
cpu-supply = <&vddcpu>;
};
&qspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <133000000>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
m25p,fast-read;
at91bootstrap@0 {
label = "ospi: at91bootstrap";
reg = <0x0 0x40000>;
};
bootloader@40000 {
label = "ospi: bootloader";
reg = <0x40000 0xc0000>;
};
bootloaderenvred@100000 {
label = "ospi: bootloader env redundant";
reg = <0x100000 0x40000>;
};
bootloaderenv@140000 {
label = "ospi: bootloader env";
reg = <0x140000 0x40000>;
};
dtb@180000 {
label = "ospi: device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
label = "ospi: kernel";
reg = <0x200000 0x600000>;
};
rootfs@800000 {
label = "ospi: rootfs";
reg = <0x800000 0x7800000>;
};
};
};
&dma0 {
status = "okay";
};
@ -547,6 +609,25 @@ pinctrl_mikrobus1_spi: mikrobus1_spi {
bias-disable;
};
pinctrl_qspi: qspi {
pinmux = <PIN_PB12__QSPI0_IO0>,
<PIN_PB11__QSPI0_IO1>,
<PIN_PB10__QSPI0_IO2>,
<PIN_PB9__QSPI0_IO3>,
<PIN_PB16__QSPI0_IO4>,
<PIN_PB17__QSPI0_IO5>,
<PIN_PB18__QSPI0_IO6>,
<PIN_PB19__QSPI0_IO7>,
<PIN_PB13__QSPI0_CS>,
<PIN_PB14__QSPI0_SCK>,
<PIN_PB15__QSPI0_SCKN>,
<PIN_PB20__QSPI0_DQS>,
<PIN_PB21__QSPI0_INT>;
bias-disable;
slew-rate = <0>;
atmel,drive-strength = <ATMEL_PIO_DRVSTR_HI>;
};
pinctrl_sdmmc0_default: sdmmc0_default {
cmd_data {
pinmux = <PIN_PA1__SDMMC0_CMD>,
@ -679,6 +760,18 @@ &spdiftx {
status = "okay";
};
&tcb0 {
timer0: timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer1: timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
&trng {
status = "okay";
};

6
arch/arm/boot/dts/at91-wb50n.dts
View File

@ -90,12 +90,6 @@ &i2c0 {
&spi1 {
status = "okay";
spidev@0 {
compatible = "spidev";
reg = <0>;
spi-max-frequency = <8000000>;
};
};
&usb0 {

2
arch/arm/boot/dts/at91sam9260.dtsi
View File

@ -166,7 +166,7 @@ tcb1: timer@fffdc000 {
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
pinctrl@fffff400 {
pinctrl: pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";

6
arch/arm/boot/dts/axp209.dtsi
View File

@ -53,7 +53,7 @@ &axp209 {
interrupt-controller;
#interrupt-cells = <1>;
ac_power_supply: ac-power-supply {
ac_power_supply: ac-power {
compatible = "x-powers,axp202-ac-power-supply";
status = "disabled";
};
@ -69,7 +69,7 @@ axp_gpio: gpio {
#gpio-cells = <2>;
};
battery_power_supply: battery-power-supply {
battery_power_supply: battery-power {
compatible = "x-powers,axp209-battery-power-supply";
status = "disabled";
};
@ -112,7 +112,7 @@ reg_ldo5: ldo5 {
};
};
usb_power_supply: usb-power-supply {
usb_power_supply: usb-power {
compatible = "x-powers,axp202-usb-power-supply";
status = "disabled";
};

6
arch/arm/boot/dts/axp22x.dtsi
View File

@ -52,7 +52,7 @@ &axp22x {
interrupt-controller;
#interrupt-cells = <1>;
ac_power_supply: ac-power-supply {
ac_power_supply: ac-power {
compatible = "x-powers,axp221-ac-power-supply";
status = "disabled";
};
@ -62,7 +62,7 @@ axp_adc: adc {
#io-channel-cells = <1>;
};
battery_power_supply: battery-power-supply {
battery_power_supply: battery-power {
compatible = "x-powers,axp221-battery-power-supply";
status = "disabled";
};
@ -163,7 +163,7 @@ reg_drivevbus: drivevbus {
};
};
usb_power_supply: usb_power_supply {
usb_power_supply: usb-power {
compatible = "x-powers,axp221-usb-power-supply";
status = "disabled";
};

10
arch/arm/boot/dts/axp81x.dtsi
View File

@ -48,7 +48,7 @@ &axp81x {
interrupt-controller;
#interrupt-cells = <1>;
ac_power_supply: ac-power-supply {
ac_power_supply: ac-power {
compatible = "x-powers,axp813-ac-power-supply";
status = "disabled";
};
@ -63,18 +63,18 @@ axp_gpio: gpio {
gpio-controller;
#gpio-cells = <2>;
gpio0_ldo: gpio0-ldo {
gpio0_ldo: gpio0-ldo-pin {
pins = "GPIO0";
function = "ldo";
};
gpio1_ldo: gpio1-ldo {
gpio1_ldo: gpio1-ldo-pin {
pins = "GPIO1";
function = "ldo";
};
};
battery_power_supply: battery-power-supply {
battery_power_supply: battery-power {
compatible = "x-powers,axp813-battery-power-supply";
status = "disabled";
};
@ -172,7 +172,7 @@ reg_drivevbus: drivevbus {
};
};
usb_power_supply: usb-power-supply {
usb_power_supply: usb-power {
compatible = "x-powers,axp813-usb-power-supply";
};
};

18
arch/arm/boot/dts/bcm-cygnus.dtsi
View File

@ -112,18 +112,18 @@ otp: otp@301c800 {
status = "disabled";
};
pcie_phy: phy@301d0a0 {
pcie_phy: pcie_phy@301d0a0 {
compatible = "brcm,cygnus-pcie-phy";
reg = <0x0301d0a0 0x14>;
#address-cells = <1>;
#size-cells = <0>;
pcie0_phy: phy@0 {
pcie0_phy: pcie-phy@0 {
reg = <0>;
#phy-cells = <0>;
};
pcie1_phy: phy@1 {
pcie1_phy: pcie-phy@1 {
reg = <1>;
#phy-cells = <0>;
};
@ -274,8 +274,8 @@ pcie0: pcie@18012000 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0 0x28000000 0 0x00010000
0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
ranges = <0x81000000 0 0 0x28000000 0 0x00010000>,
<0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
phys = <&pcie0_phy>;
phy-names = "pcie-phy";
@ -283,7 +283,7 @@ pcie0: pcie@18012000 {
status = "disabled";
msi-parent = <&msi0>;
msi0: msi-controller {
msi0: msi {
compatible = "brcm,iproc-msi";
msi-controller;
interrupt-parent = <&gic>;
@ -309,8 +309,8 @@ pcie1: pcie@18013000 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0 0x48000000 0 0x00010000
0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
ranges = <0x81000000 0 0 0x48000000 0 0x00010000>,
<0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
phys = <&pcie1_phy>;
phy-names = "pcie-phy";
@ -318,7 +318,7 @@ pcie1: pcie@18013000 {
status = "disabled";
msi-parent = <&msi1>;
msi1: msi-controller {
msi1: msi {
compatible = "brcm,iproc-msi";
msi-controller;
interrupt-parent = <&gic>;

4
arch/arm/boot/dts/bcm-hr2.dtsi
View File

@ -318,7 +318,7 @@ pcie0: pcie@18012000 {
status = "disabled";
msi-parent = <&msi0>;
msi0: msi-controller {
msi0: msi {
compatible = "brcm,iproc-msi";
msi-controller;
interrupt-parent = <&gic>;
@ -354,7 +354,7 @@ pcie1: pcie@18013000 {
status = "disabled";
msi-parent = <&msi1>;
msi1: msi-controller {
msi1: msi {
compatible = "brcm,iproc-msi";
msi-controller;
interrupt-parent = <&gic>;

70
arch/arm/boot/dts/bcm-nsp-ax.dtsi Normal file
View File

@ -0,0 +1,70 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Broadcom Northstar Plus Ax stepping-specific bindings.
* Notable differences from B0+ are the secondary-boot-reg and
* lack of DMA coherency.
*/
&cpu1 {
secondary-boot-reg = <0xffff042c>;
};
&dma {
/delete-property/ dma-coherent;
};
&sdio {
/delete-property/ dma-coherent;
};
&amac0 {
/delete-property/ dma-coherent;
};
&amac1 {
/delete-property/ dma-coherent;
};
&amac2 {
/delete-property/ dma-coherent;
};
&ehci0 {
/delete-property/ dma-coherent;
};
&mailbox {
/delete-property/ dma-coherent;
};
&xhci {
/delete-property/ dma-coherent;
};
&ehci0 {
/delete-property/ dma-coherent;
};
&ohci0 {
/delete-property/ dma-coherent;
};
&i2c0 {
/delete-property/ dma-coherent;
};
&sata {
/delete-property/ dma-coherent;
};
&pcie0 {
/delete-property/ dma-coherent;
};
&pcie1 {
/delete-property/ dma-coherent;
};
&pcie2 {
/delete-property/ dma-coherent;
};

56
arch/arm/boot/dts/bcm-nsp.dtsi
View File

@ -166,7 +166,7 @@ periph_clk: periph_clk {
};
};
axi@18000000 {
axi: axi@18000000 {
compatible = "simple-bus";
ranges = <0x00000000 0x18000000 0x0011c40c>;
#address-cells = <1>;
@ -310,6 +310,7 @@ qspi: spi@27200 {
num-cs = <2>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
xhci: usb@29000 {
@ -362,6 +363,42 @@ pwm: pwm@31000 {
status = "disabled";
};
mdio: mdio@32000 {
compatible = "brcm,iproc-mdio";
reg = <0x32000 0x8>;
#size-cells = <0>;
#address-cells = <1>;
};
mdio-mux@32000 {
compatible = "mdio-mux-mmioreg", "mdio-mux";
reg = <0x32000 0x4>;
mux-mask = <0x200>;
#address-cells = <1>;
#size-cells = <0>;
mdio-parent-bus = <&mdio>;
mdio_int: mdio@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
usb3_phy: usb3-phy@10 {
compatible = "brcm,ns-bx-usb3-phy";
reg = <0x10>;
usb3-dmp-syscon = <&usb3_dmp>;
#phy-cells = <0>;
status = "disabled";
};
};
mdio_ext: mdio@200 {
reg = <0x200>;
#address-cells = <1>;
#size-cells = <0>;
};
};
rng: rng@33000 {
compatible = "brcm,bcm-nsp-rng";
reg = <0x33000 0x14>;
@ -497,7 +534,7 @@ sata_phy1: sata-phy@1 {
};
};
sata: ahci@41000 {
sata: sata@41000 {
compatible = "brcm,bcm-nsp-ahci";
reg-names = "ahci", "top-ctrl";
reg = <0x41000 0x1000>, <0x40020 0x1c>;
@ -520,13 +557,8 @@ sata1: sata-port@1 {
};
};
usb3_phy: usb3-phy@104000 {
compatible = "brcm,ns-bx-usb3-phy";
reg = <0x104000 0x1000>,
<0x032000 0x1000>;
reg-names = "dmp", "ccb-mii";
#phy-cells = <0>;
status = "disabled";
usb3_dmp: syscon@104000 {
reg = <0x104000 0x1000>;
};
};
@ -555,7 +587,7 @@ pcie0: pcie@18012000 {
status = "disabled";
msi-parent = <&msi0>;
msi0: msi-controller {
msi0: msi {
compatible = "brcm,iproc-msi";
msi-controller;
interrupt-parent = <&gic>;
@ -592,7 +624,7 @@ pcie1: pcie@18013000 {
status = "disabled";
msi-parent = <&msi1>;
msi1: msi-controller {
msi1: msi {
compatible = "brcm,iproc-msi";
msi-controller;
interrupt-parent = <&gic>;
@ -629,7 +661,7 @@ pcie2: pcie@18014000 {
status = "disabled";
msi-parent = <&msi2>;
msi2: msi-controller {
msi2: msi {
compatible = "brcm,iproc-msi";
msi-controller;
interrupt-parent = <&gic>;

66
arch/arm/boot/dts/bcm2711-rpi-4-b.dts
View File

@ -3,6 +3,7 @@
#include "bcm2711.dtsi"
#include "bcm2711-rpi.dtsi"
//#include "bcm283x-rpi-usb-peripheral.dtsi"
#include "bcm283x-rpi-wifi-bt.dtsi"
/ {
compatible = "raspberrypi,4-model-b", "brcm,bcm2711";
@ -26,11 +27,6 @@ led-pwr {
};
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
};
sd_io_1v8_reg: sd_io_1v8_reg {
compatible = "regulator-gpio";
regulator-name = "vdd-sd-io";
@ -56,6 +52,10 @@ sd_vcc_reg: sd_vcc_reg {
};
};
&bt {
shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
};
&ddc0 {
status = "okay";
};
@ -65,12 +65,12 @@ &ddc1 {
};
&expgpio {
gpio-line-names = "BT_ON",
gpio-line-names = "BT_ON", /* 0 */
"WL_ON",
"PWR_LED_OFF",
"GLOBAL_RESET",
"VDD_SD_IO_SEL",
"CAM_GPIO",
"CAM_GPIO", /* 5 */
"SD_PWR_ON",
"SD_OC_N";
};
@ -84,66 +84,66 @@ &gpio {
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "ID_SDA",
gpio-line-names = "ID_SDA", /* 0 */
"ID_SCL",
"SDA1",
"SCL1",
"GPIO_GCLK",
"GPIO5",
"GPIO5", /* 5 */
"GPIO6",
"SPI_CE1_N",
"SPI_CE0_N",
"SPI_MISO",
"SPI_MOSI",
"SPI_MOSI", /* 10 */
"SPI_SCLK",
"GPIO12",
"GPIO13",
/* Serial port */
"TXD1",
"RXD1",
"RXD1", /* 15 */
"GPIO16",
"GPIO17",
"GPIO18",
"GPIO19",
"GPIO20",
"GPIO20", /* 20 */
"GPIO21",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
"GPIO25", /* 25 */
"GPIO26",
"GPIO27",
"RGMII_MDIO",
"RGMIO_MDC",
/* Used by BT module */
"CTS0",
"CTS0", /* 30 */
"RTS0",
"TXD0",
"RXD0",
/* Used by Wifi */
"SD1_CLK",
"SD1_CMD",
"SD1_CMD", /* 35 */
"SD1_DATA0",
"SD1_DATA1",
"SD1_DATA2",
"SD1_DATA3",
/* Shared with SPI flash */
"PWM0_MISO",
"PWM0_MISO", /* 40 */
"PWM1_MOSI",
"STATUS_LED_G_CLK",
"SPIFLASH_CE_N",
"SDA0",
"SCL0",
"SCL0", /* 45 */
"RGMII_RXCLK",
"RGMII_RXCTL",
"RGMII_RXD0",
"RGMII_RXD1",
"RGMII_RXD2",
"RGMII_RXD2", /* 50 */
"RGMII_RXD3",
"RGMII_TXCLK",
"RGMII_TXCTL",
"RGMII_TXD0",
"RGMII_TXD1",
"RGMII_TXD1", /* 55 */
"RGMII_TXD2",
"RGMII_TXD3";
};
@ -178,23 +178,6 @@ &pwm1 {
status = "okay";
};
/* SDHCI is used to control the SDIO for wireless */
&sdhci {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio34>;
bus-width = <4>;
non-removable;
mmc-pwrseq = <&wifi_pwrseq>;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* EMMC2 is used to drive the SD card */
&emmc2 {
vqmmc-supply = <&sd_io_1v8_reg>;
@ -237,13 +220,6 @@ &uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <2000000>;
shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
};
};
/* uart1 is mapped to the pin header */
@ -261,6 +237,10 @@ &vec {
status = "disabled";
};
&wifi_pwrseq {
reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
};
// =============================================
// Downstream rpi- changes

38
arch/arm/boot/dts/bcm2711-rpi-400.dts
View File

@ -3,6 +3,7 @@
#include "bcm2711.dtsi"
#include "bcm2711-rpi.dtsi"
//#include "bcm283x-rpi-usb-peripheral.dtsi"
#include "bcm283x-rpi-wifi-bt.dtsi"
/ {
compatible = "raspberrypi,400", "brcm,bcm2711";
@ -26,11 +27,6 @@ led-pwr {
};
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
};
sd_io_1v8_reg: sd_io_1v8_reg {
compatible = "regulator-gpio";
regulator-name = "vdd-sd-io";
@ -56,6 +52,10 @@ sd_vcc_reg: sd_vcc_reg {
};
};
&bt {
shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
};
&ddc0 {
status = "okay";
};
@ -178,23 +178,6 @@ &pwm1 {
status = "okay";
};
/* SDHCI is used to control the SDIO for wireless */
&sdhci {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio34>;
bus-width = <4>;
non-removable;
mmc-pwrseq = <&wifi_pwrseq>;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* EMMC2 is used to drive the SD card */
&emmc2 {
vqmmc-supply = <&sd_io_1v8_reg>;
@ -237,13 +220,6 @@ &uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <2000000>;
shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
};
};
/* uart1 is mapped to the pin header */
@ -261,6 +237,10 @@ &vec {
status = "disabled";
};
&wifi_pwrseq {
reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
};
// =============================================
// Downstream rpi- changes

138
arch/arm/boot/dts/bcm2711-rpi-cm4-io.dts Normal file
View File

@ -0,0 +1,138 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2711-rpi-cm4.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
/ {
model = "Raspberry Pi Compute Module 4 IO Board";
leds {
led-act {
gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
};
led-pwr {
label = "PWR";
gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
default-state = "keep";
linux,default-trigger = "default-on";
};
};
};
&ddc0 {
status = "okay";
};
&ddc1 {
status = "okay";
};
&gpio {
/*
* Parts taken from rpi_SCH_4b_4p0_reduced.pdf and
* the official GPU firmware DT blob.
*
* Legend:
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "ID_SDA",
"ID_SCL",
"SDA1",
"SCL1",
"GPIO_GCLK",
"GPIO5",
"GPIO6",
"SPI_CE1_N",
"SPI_CE0_N",
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
"GPIO12",
"GPIO13",
/* Serial port */
"TXD1",
"RXD1",
"GPIO16",
"GPIO17",
"GPIO18",
"GPIO19",
"GPIO20",
"GPIO21",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
"GPIO26",
"GPIO27",
"RGMII_MDIO",
"RGMIO_MDC",
/* Used by BT module */
"CTS0",
"RTS0",
"TXD0",
"RXD0",
/* Used by Wifi */
"SD1_CLK",
"SD1_CMD",
"SD1_DATA0",
"SD1_DATA1",
"SD1_DATA2",
"SD1_DATA3",
/* Shared with SPI flash */
"PWM0_MISO",
"PWM1_MOSI",
"STATUS_LED_G_CLK",
"SPIFLASH_CE_N",
"SDA0",
"SCL0",
"RGMII_RXCLK",
"RGMII_RXCTL",
"RGMII_RXD0",
"RGMII_RXD1",
"RGMII_RXD2",
"RGMII_RXD3",
"RGMII_TXCLK",
"RGMII_TXCTL",
"RGMII_TXD0",
"RGMII_TXD1",
"RGMII_TXD2",
"RGMII_TXD3";
};
&hdmi0 {
status = "okay";
};
&hdmi1 {
status = "okay";
};
&genet {
status = "okay";
};
&pixelvalve0 {
status = "okay";
};
&pixelvalve1 {
status = "okay";
};
&pixelvalve2 {
status = "okay";
};
&pixelvalve4 {
status = "okay";
};
&vc4 {
status = "okay";
};
&vec {
status = "disabled";
};

44
arch/arm/boot/dts/bcm2711-rpi-cm4.dts
View File

@ -3,6 +3,7 @@
#include "bcm2711.dtsi"
#include "bcm2711-rpi.dtsi"
//#include "bcm283x-rpi-usb-peripheral.dtsi"
#include "bcm283x-rpi-wifi-bt.dtsi"
/ {
compatible = "raspberrypi,4-compute-module", "brcm,bcm2711";
@ -26,11 +27,6 @@ led-pwr {
};
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
};
sd_io_1v8_reg: sd_io_1v8_reg {
compatible = "regulator-gpio";
regulator-name = "vdd-sd-io";
@ -56,6 +52,10 @@ sd_vcc_reg: sd_vcc_reg {
};
};
&bt {
shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
};
&ddc0 {
status = "okay";
};
@ -190,23 +190,6 @@ &pwm1 {
status = "okay";
};
/* SDHCI is used to control the SDIO for wireless */
&sdhci {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio34>;
bus-width = <4>;
non-removable;
mmc-pwrseq = <&wifi_pwrseq>;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* EMMC2 is used to drive the EMMC card */
&emmc2 {
bus-width = <8>;
@ -231,7 +214,7 @@ phy1: ethernet-phy@0 {
&pcie0 {
pci@0,0 {
device-type = "pci";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
@ -245,13 +228,6 @@ &uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <2000000>;
shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
};
};
/* uart1 is mapped to the pin header */
@ -261,10 +237,6 @@ &uart1 {
status = "okay";
};
&vchiq {
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
};
&vc4 {
status = "okay";
};
@ -273,6 +245,10 @@ &vec {
status = "disabled";
};
&wifi_pwrseq {
reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
};
// =============================================
// Downstream rpi- changes

113
arch/arm/boot/dts/bcm2711-rpi-cm4.dtsi Normal file
View File

@ -0,0 +1,113 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2711.dtsi"
#include "bcm2711-rpi.dtsi"
#include "bcm283x-rpi-wifi-bt.dtsi"
/ {
compatible = "raspberrypi,4-compute-module", "brcm,bcm2711";
chosen {
/* 8250 auxiliary UART instead of pl011 */
stdout-path = "serial1:115200n8";
};
sd_io_1v8_reg: sd_io_1v8_reg {
compatible = "regulator-gpio";
regulator-name = "vdd-sd-io";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
regulator-settling-time-us = <5000>;
gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>;
states = <1800000 0x1>,
<3300000 0x0>;
status = "okay";
};
sd_vcc_reg: sd_vcc_reg {
compatible = "regulator-fixed";
regulator-name = "vcc-sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
gpio = <&expgpio 6 GPIO_ACTIVE_HIGH>;
};
};
&bt {
shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
};
/* EMMC2 is used to drive the eMMC */
&emmc2 {
bus-width = <8>;
vqmmc-supply = <&sd_io_1v8_reg>;
vmmc-supply = <&sd_vcc_reg>;
broken-cd;
/* Even the IP block is limited to 100 MHz
* this provides a throughput gain
*/
mmc-hs200-1_8v;
status = "okay";
};
&expgpio {
gpio-line-names = "BT_ON",
"WL_ON",
"PWR_LED_OFF",
"ANT1",
"VDD_SD_IO_SEL",
"CAM_GPIO",
"SD_PWR_ON",
"ANT2";
ant1: ant1-hog {
gpio-hog;
gpios = <3 GPIO_ACTIVE_HIGH>;
/* internal antenna enabled */
output-high;
line-name = "ant1";
};
ant2: ant2-hog {
gpio-hog;
gpios = <7 GPIO_ACTIVE_HIGH>;
/* external antenna disabled */
output-low;
line-name = "ant2";
};
};
&genet {
phy-handle = <&phy1>;
phy-mode = "rgmii-rxid";
status = "okay";
};
&genet_mdio {
phy1: ethernet-phy@0 {
/* No PHY interrupt */
reg = <0x0>;
};
};
/* uart0 communicates with the BT module */
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>;
uart-has-rtscts;
};
/* uart1 is mapped to the pin header */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_gpio14>;
status = "okay";
};
&wifi_pwrseq {
reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
};

31
arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
View File

@ -7,6 +7,7 @@
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
#include "bcm283x-rpi-usb-otg.dtsi"
#include "bcm283x-rpi-wifi-bt.dtsi"
/ {
compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
@ -27,11 +28,10 @@ led-act {
gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
};
};
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
};
&bt {
shutdown-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>;
};
&gpio {
@ -110,19 +110,7 @@ &hdmi {
};
&sdhci {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>;
bus-width = <4>;
mmc-pwrseq = <&wifi_pwrseq>;
non-removable;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
&sdhost {
@ -135,13 +123,6 @@ &sdhost {
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <2000000>;
shutdown-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>;
};
};
&uart1 {
@ -150,6 +131,10 @@ &uart1 {
status = "okay";
};
&wifi_pwrseq {
reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
};
/* i2c on camera/display connector is gpio 28&29 */
&i2c0mux {
pinctrl-1 = <&i2c0_gpio28>;

36
arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts
View File

@ -3,6 +3,7 @@
#include "bcm2837.dtsi"
#include "bcm2836-rpi.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
#include "bcm283x-rpi-wifi-bt.dtsi"
/ {
compatible = "raspberrypi,3-model-a-plus", "brcm,bcm2837";
@ -130,28 +131,6 @@ &pwm {
status = "okay";
};
/*
* SDHCI is used to control the SDIO for wireless
*
* WL_REG_ON and BT_REG_ON of the CYW43455 Wifi/BT module are driven
* by a single GPIO. We can't give GPIO control to one of the drivers,
* otherwise the other part would get unexpectedly disturbed.
*/
&sdhci {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio34>;
status = "okay";
bus-width = <4>;
non-removable;
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* SDHOST is used to drive the SD card */
&sdhost {
pinctrl-names = "default";
@ -160,16 +139,15 @@ &sdhost {
bus-width = <4>;
};
/* uart0 communicates with the BT module */
/* uart0 communicates with the BT module
*
* WL_REG_ON and BT_REG_ON of the CYW43455 Wifi/BT module are driven
* by a single GPIO. We can't give GPIO control to one of the drivers,
* otherwise the other part would get unexpectedly disturbed.
*/
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <2000000>;
};
};
/* uart1 is mapped to the pin header */

36
arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts
View File

@ -4,6 +4,7 @@
#include "bcm2836-rpi.dtsi"
#include "bcm283x-rpi-lan7515.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
#include "bcm283x-rpi-wifi-bt.dtsi"
/ {
compatible = "raspberrypi,3-model-b-plus", "brcm,bcm2837";
@ -31,11 +32,10 @@ led-pwr {
linux,default-trigger = "default-on";
};
};
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
};
&bt {
shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
};
&firmware {
@ -137,23 +137,6 @@ &pwm {
status = "okay";
};
/* SDHCI is used to control the SDIO for wireless */
&sdhci {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio34>;
status = "okay";
bus-width = <4>;
non-removable;
mmc-pwrseq = <&wifi_pwrseq>;
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* SDHOST is used to drive the SD card */
&sdhost {
pinctrl-names = "default";
@ -166,13 +149,6 @@ &sdhost {
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <2000000>;
shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
};
};
/* uart1 is mapped to the pin header */
@ -182,6 +158,10 @@ &uart1 {
status = "okay";
};
&wifi_pwrseq {
reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
};
/* i2c on camera/display connector is gpio 44&45 */
&i2c0mux {
pinctrl-1 = <&i2c0_gpio44>;

36
arch/arm/boot/dts/bcm2837-rpi-3-b.dts
View File

@ -4,6 +4,7 @@
#include "bcm2836-rpi.dtsi"
#include "bcm283x-rpi-smsc9514.dtsi"
#include "bcm283x-rpi-usb-host.dtsi"
#include "bcm283x-rpi-wifi-bt.dtsi"
/ {
compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
@ -24,11 +25,10 @@ led-act {
gpios = <&expgpio 2 GPIO_ACTIVE_HIGH>;
};
};
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
};
&bt {
shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
};
&firmware {
@ -134,13 +134,6 @@ &hdmi {
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_gpio32 &gpclk2_gpio43>;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <2000000>;
shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
};
};
/* uart1 is mapped to the pin header */
@ -150,23 +143,6 @@ &uart1 {
status = "okay";
};
/* SDHCI is used to control the SDIO for wireless */
&sdhci {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio34>;
status = "okay";
bus-width = <4>;
non-removable;
mmc-pwrseq = <&wifi_pwrseq>;
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* SDHOST is used to drive the SD card */
&sdhost {
pinctrl-names = "default";
@ -175,6 +151,10 @@ &sdhost {
bus-width = <4>;
};
&wifi_pwrseq {
reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
};
/* i2c on camera/display connector is gpio 44&45 */
&i2c0mux {
pinctrl-1 = <&i2c0_gpio44>;

34
arch/arm/boot/dts/bcm283x-rpi-wifi-bt.dtsi Normal file
View File

@ -0,0 +1,34 @@
// SPDX-License-Identifier: GPL-2.0
/ {
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
};
};
/* SDHCI is used to control the SDIO for wireless */
&sdhci {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio34>;
bus-width = <4>;
non-removable;
mmc-pwrseq = <&wifi_pwrseq>;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
/* uart0 communicates with the BT module */
&uart0 {
status = "okay";
bt: bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <2000000>;
};
};

37
arch/arm/boot/dts/bcm4708-netgear-r6250.dts
View File

@ -94,3 +94,40 @@ &spi_nor {
&usb3_phy {
status = "okay";
};
&srab {
status = "okay";
ports {
port@0 {
reg = <0>;
label = "lan4";
};
port@1 {
reg = <1>;
label = "lan3";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan1";
};
port@4 {
reg = <4>;
label = "wan";
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&gmac0>;
};
};
};

37
arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
View File

@ -117,3 +117,40 @@ eject {
};
};
};
&srab {
status = "okay";
ports {
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@4 {
reg = <4>;
label = "wan";
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&gmac0>;
};
};
};

42
arch/arm/boot/dts/bcm4709-netgear-r8000.dts
View File

@ -187,3 +187,45 @@ &usb3 {
&usb3_phy {
status = "okay";
};
&srab {
status = "okay";
ports {
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@4 {
reg = <4>;
label = "wan";
};
port@8 {
reg = <8>;
label = "cpu";
ethernet = <&gmac2>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};

199
arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts Normal file
View File

@ -0,0 +1,199 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (C) 2021 Arınç ÜNAL <arinc.unal@arinc9.com>
*/
/dts-v1/;
#include "bcm47094.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"
/ {
compatible = "asus,rt-ac88u", "brcm,bcm47094", "brcm,bcm4708";
model = "Asus RT-AC88U";
chosen {
bootargs = "earlycon";
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x18000000>;
};
nvram@1c080000 {
compatible = "brcm,nvram";
reg = <0x1c080000 0x00180000>;
};
leds {
compatible = "gpio-leds";
power {
label = "white:power";
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
wan-red {
label = "red:wan";
gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
};
lan {
label = "white:lan";
gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>;
};
usb2 {
label = "white:usb2";
gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>;
trigger-sources = <&ehci_port2>;
linux,default-trigger = "usbport";
};
usb3 {
label = "white:usb3";
gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
trigger-sources = <&ehci_port1>, <&xhci_port1>;
linux,default-trigger = "usbport";
};
wps {
label = "white:wps";
gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>;
};
};
gpio-keys {
compatible = "gpio-keys";
wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>;
};
reset {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
};
wifi {
label = "Wi-Fi";
linux,code = <KEY_RFKILL>;
gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;
};
led {
label = "Backlight";
linux,code = <KEY_BRIGHTNESS_ZERO>;
gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
};
};
};
&srab {
compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab";
status = "okay";
dsa,member = <0 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan4";
};
port@1 {
reg = <1>;
label = "lan3";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan1";
};
port@4 {
reg = <4>;
label = "wan";
};
sw0_p5: port@5 {
reg = <5>;
label = "extsw";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
port@7 {
reg = <7>;
ethernet = <&gmac1>;
label = "cpu";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@8 {
reg = <8>;
ethernet = <&gmac2>;
label = "cpu";
status = "disabled";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
&usb2 {
vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>;
};
&usb3_phy {
status = "okay";
};
&nandcs {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "boot";
reg = <0x00000000 0x00080000>;
read-only;
};
partition@80000 {
label = "nvram";
reg = <0x00080000 0x00180000>;
};
partition@200000 {
label = "firmware";
reg = <0x00200000 0x07e00000>;
compatible = "brcm,trx";
};
};
};

42
arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
View File

@ -118,3 +118,45 @@ &spi_nor {
&usb3_phy {
status = "okay";
};
&srab {
status = "okay";
ports {
port@0 {
reg = <0>;
label = "lan4";
};
port@1 {
reg = <1>;
label = "lan3";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan1";
};
port@4 {
reg = <4>;
label = "wan";
};
port@8 {
reg = <8>;
label = "cpu";
ethernet = <&gmac2>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};

37
arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts
View File

@ -68,3 +68,40 @@ &spi_nor {
&usb3_phy {
status = "okay";
};
&srab {
status = "okay";
ports {
port@0 {
reg = <0>;
label = "wan";
};
port@1 {
reg = <1>;
label = "lan4";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan2";
};
port@4 {
reg = <4>;
label = "lan1";
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&gmac0>;
};
};
};

37
arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts
View File

@ -68,3 +68,40 @@ &spi_nor {
&usb3_phy {
status = "okay";
};
&srab {
status = "okay";
ports {
port@0 {
reg = <0>;
label = "wan";
};
port@1 {
reg = <1>;
label = "lan4";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan2";
};
port@4 {
reg = <4>;
label = "lan1";
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&gmac0>;
};
};
};

37
arch/arm/boot/dts/bcm47189-tenda-ac9.dts
View File

@ -105,3 +105,40 @@ pcie0_chipcommon: chipcommon@0 {
};
};
};
&switch {
status = "okay";
ports {
port@0 {
reg = <0>;
label = "wan";
};
port@1 {
reg = <1>;
label = "lan1";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan3";
};
port@4 {
reg = <4>;
label = "lan4";
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&gmac0>;
};
};
};

61
arch/arm/boot/dts/bcm53016-meraki-mr32.dts
View File

@ -84,34 +84,6 @@ blue {
max-brightness = <255>;
};
};
i2c {
/*
* The platform provided I2C does not budge.
* This is a replacement until I can figure
* out what are the missing bits...
*/
compatible = "i2c-gpio";
sda-gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;
scl-gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>;
i2c-gpio,delay-us = <10>; /* close to 100 kHz */
#address-cells = <1>;
#size-cells = <0>;
current_sense: ina219@45 {
compatible = "ti,ina219";
reg = <0x45>;
shunt-resistor = <60000>; /* = 60 mOhms */
};
eeprom: eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
read-only;
};
};
};
&uart0 {
@ -133,6 +105,11 @@ &uart2 {
*/
};
&gmac0 {
nvmem-cell-names = "mac-address";
nvmem-cells = <&mac_address>;
};
&gmac1 {
status = "disabled";
};
@ -217,3 +194,31 @@ fixed-link {
};
};
};
&i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinmux_i2c>;
clock-frequency = <100000>;
current_sense: ina219@45 {
compatible = "ti,ina219";
reg = <0x45>;
shunt-resistor = <60000>; /* = 60 mOhms */
};
eeprom: eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
read-only;
#address-cells = <1>;
#size-cells = <1>;
mac_address: mac-address@66 {
reg = <0x66 0x6>;
};
};
};

31
arch/arm/boot/dts/bcm5301x.dtsi
View File

@ -148,15 +148,6 @@ periph_clk: periph_clk {
};
};
usb2_phy: usb2-phy@1800c000 {
compatible = "brcm,ns-usb2-phy";
reg = <0x1800c000 0x1000>;
reg-names = "dmu";
#phy-cells = <0>;
clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
clock-names = "phy-ref-clk";
};
axi@18000000 {
compatible = "brcm,bus-axi";
reg = <0x18000000 0x1000>;
@ -423,14 +414,14 @@ dmu-bus@1800c000 {
#address-cells = <1>;
#size-cells = <1>;
cru@100 {
compatible = "simple-bus";
cru-bus@100 {
compatible = "brcm,ns-cru", "simple-mfd";
reg = <0x100 0x1a4>;
ranges;
#address-cells = <1>;
#size-cells = <1>;
lcpll0: lcpll0@100 {
lcpll0: clock-controller@100 {
#clock-cells = <1>;
compatible = "brcm,nsp-lcpll0";
reg = <0x100 0x14>;
@ -439,7 +430,7 @@ lcpll0: lcpll0@100 {
"sdio", "ddr_phy";
};
genpll: genpll@140 {
genpll: clock-controller@140 {
#clock-cells = <1>;
compatible = "brcm,nsp-genpll";
reg = <0x140 0x24>;
@ -450,6 +441,20 @@ genpll: genpll@140 {
"sata1", "sata2";
};
usb2_phy: phy@164 {
compatible = "brcm,ns-usb2-phy";
reg = <0x164 0x4>;
brcm,syscon-clkset = <&cru_clkset>;
clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
clock-names = "phy-ref-clk";
#phy-cells = <0>;
};
cru_clkset: syscon@180 {
compatible = "brcm,cru-clkset", "syscon";
reg = <0x180 0x4>;
};
pinctrl: pin-controller@1c0 {
compatible = "brcm,bcm4708-pinmux";
reg = <0x1c0 0x24>;

18
arch/arm/boot/dts/bcm53573.dtsi
View File

@ -180,6 +180,24 @@ ohci_port2: port@2 {
gmac0: ethernet@5000 {
reg = <0x5000 0x1000>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch: switch@1e {
compatible = "brcm,bcm53125";
reg = <0x1e>;
status = "disabled";
/* ports are defined in board DTS */
ports {
#address-cells = <1>;
#size-cells = <0>;
};
};
};
};
gmac1: ethernet@b000 {

3
arch/arm/boot/dts/bcm958522er.dts
View File

@ -37,7 +37,7 @@
/ {
model = "NorthStar Plus SVK (BCM958522ER)";
compatible = "brcm,bcm58522", "brcm,nsp";
compatible = "brcm,bcm958522er", "brcm,bcm58522", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
@ -134,6 +134,7 @@ nand_sel: nand_sel {
};
&qspi {
status = "okay";
bspi-sel = <0>;
flash: m25p80@0 {
#address-cells = <1>;

3
arch/arm/boot/dts/bcm958525er.dts
View File

@ -37,7 +37,7 @@
/ {
model = "NorthStar Plus SVK (BCM958525ER)";
compatible = "brcm,bcm58525", "brcm,nsp";
compatible = "brcm,bcm958525er", "brcm,bcm58525", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
@ -134,6 +134,7 @@ nand_sel: nand_sel {
};
&qspi {
status = "okay";
bspi-sel = <0>;
flash: m25p80@0 {
#address-cells = <1>;

3
arch/arm/boot/dts/bcm958525xmc.dts
View File

@ -37,7 +37,7 @@
/ {
model = "NorthStar Plus XMC (BCM958525xmc)";
compatible = "brcm,bcm58525", "brcm,nsp";
compatible = "brcm,bcm958525xmc", "brcm,bcm58525", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
@ -150,6 +150,7 @@ nand_sel: nand_sel {
};
&qspi {
status = "okay";
bspi-sel = <0>;
flash: m25p80@0 {
#address-cells = <1>;

3
arch/arm/boot/dts/bcm958622hr.dts
View File

@ -37,7 +37,7 @@
/ {
model = "NorthStar Plus SVK (BCM958622HR)";
compatible = "brcm,bcm58622", "brcm,nsp";
compatible = "brcm,bcm958622hr", "brcm,bcm58622", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
@ -138,6 +138,7 @@ nand_sel: nand_sel {
};
&qspi {
status = "okay";
bspi-sel = <0>;
flash: m25p80@0 {
#address-cells = <1>;

3
arch/arm/boot/dts/bcm958623hr.dts
View File

@ -37,7 +37,7 @@
/ {
model = "NorthStar Plus SVK (BCM958623HR)";
compatible = "brcm,bcm58623", "brcm,nsp";
compatible = "brcm,bcm958623hr", "brcm,bcm58623", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
@ -142,6 +142,7 @@ &sata_phy0 {
};
&qspi {
status = "okay";
bspi-sel = <0>;
flash: m25p80@0 {
#address-cells = <1>;

285
arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi Normal file
View File

@ -0,0 +1,285 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Device Tree Bindings for Cisco Meraki MX65 series (Alamo).
*
* Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
*/
#include "bcm958625-meraki-mx6x-common.dtsi"
/ {
keys {
compatible = "gpio-keys-polled";
autorepeat;
poll-interval = <20>;
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpioa 8 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
led-0 {
/* green:wan1-left */
function = LED_FUNCTION_ACTIVITY;
function-enumerator = <0>;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpioa 25 GPIO_ACTIVE_LOW>;
};
led-1 {
/* green:wan1-right */
function = LED_FUNCTION_ACTIVITY;
function-enumerator = <1>;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpioa 24 GPIO_ACTIVE_LOW>;
};
led-2 {
/* green:wan2-left */
function = LED_FUNCTION_ACTIVITY;
function-enumerator = <2>;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpioa 27 GPIO_ACTIVE_LOW>;
};
led-3 {
/* green:wan2-right */
function = LED_FUNCTION_ACTIVITY;
function-enumerator = <3>;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpioa 26 GPIO_ACTIVE_LOW>;
};
led-4 {
/* amber:power */
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_AMBER>;
gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
led-5 {
/* white:status */
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_WHITE>;
gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>;
};
};
};
&axi {
mdio-mux@3f1c0 {
compatible = "mdio-mux-mmioreg", "mdio-mux";
reg = <0x3f1c0 0x4>;
mux-mask = <0x2000>;
mdio-parent-bus = <&mdio_ext>;
#address-cells = <1>;
#size-cells = <0>;
mdio@0 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
phy_port6: phy@0 {
reg = <0>;
};
phy_port7: phy@1 {
reg = <1>;
};
phy_port8: phy@2 {
reg = <2>;
};
phy_port9: phy@3 {
reg = <3>;
};
phy_port10: phy@4 {
reg = <4>;
};
switch@10 {
compatible = "qca,qca8337";
reg = <0x10>;
dsa,member = <1 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ethernet = <&sgmii1>;
phy-mode = "sgmii";
qca,sgmii-enable-pll;
qca,sgmii-txclk-falling-edge;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "lan8";
phy-handle = <&phy_port6>;
};
port@2 {
reg = <2>;
label = "lan9";
phy-handle = <&phy_port7>;
};
port@3 {
reg = <3>;
label = "lan10";
phy-handle = <&phy_port8>;
};
port@4 {
reg = <4>;
label = "lan11";
phy-handle = <&phy_port9>;
};
port@5 {
reg = <5>;
label = "lan12";
phy-handle = <&phy_port10>;
};
};
};
};
mdio-mii@2000 {
reg = <0x2000>;
#address-cells = <1>;
#size-cells = <0>;
phy_port1: phy@0 {
reg = <0>;
};
phy_port2: phy@1 {
reg = <1>;
};
phy_port3: phy@2 {
reg = <2>;
};
phy_port4: phy@3 {
reg = <3>;
};
phy_port5: phy@4 {
reg = <4>;
};
switch@10 {
compatible = "qca,qca8337";
reg = <0x10>;
dsa,member = <2 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ethernet = <&sgmii0>;
phy-mode = "sgmii";
qca,sgmii-enable-pll;
qca,sgmii-txclk-falling-edge;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "lan3";
phy-handle = <&phy_port1>;
};
port@2 {
reg = <2>;
label = "lan4";
phy-handle = <&phy_port2>;
};
port@3 {
reg = <3>;
label = "lan5";
phy-handle = <&phy_port3>;
};
port@4 {
reg = <4>;
label = "lan6";
phy-handle = <&phy_port4>;
};
port@5 {
reg = <5>;
label = "lan7";
phy-handle = <&phy_port5>;
};
};
};
};
};
};
&srab {
compatible = "brcm,bcm58625-srab", "brcm,nsp-srab";
status = "okay";
dsa,member = <0 0>;
ports {
port@0 {
label = "wan1";
reg = <0>;
};
port@1 {
label = "wan2";
reg = <1>;
};
sgmii0: port@4 {
label = "sw0";
reg = <4>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
sgmii1: port@5 {
label = "sw1";
reg = <5>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@8 {
ethernet = <&amac2>;
reg = <8>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};

163
arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi Normal file
View File

@ -0,0 +1,163 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Device Tree Bindings for Cisco Meraki MX64 series (Kingpin).
*
* Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
*/
#include "bcm958625-meraki-mx6x-common.dtsi"
/ {
keys {
compatible = "gpio-keys-polled";
autorepeat;
poll-interval = <20>;
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpioa 6 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
led-0 {
/* green:lan1-left */
function = LED_FUNCTION_ACTIVITY;
function-enumerator = <0>;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpioa 19 GPIO_ACTIVE_LOW>;
};
led-1 {
/* green:lan1-right */
function = LED_FUNCTION_ACTIVITY;
function-enumerator = <1>;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpioa 18 GPIO_ACTIVE_LOW>;
};
led-2 {
/* green:lan2-left */
function = LED_FUNCTION_ACTIVITY;
function-enumerator = <2>;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpioa 24 GPIO_ACTIVE_LOW>;
};
led-3 {
/* green:lan2-right */
function = LED_FUNCTION_ACTIVITY;
function-enumerator = <3>;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpioa 20 GPIO_ACTIVE_LOW>;
};
led-4 {
/* green:lan3-left */
function = LED_FUNCTION_ACTIVITY;
function-enumerator = <4>;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpioa 26 GPIO_ACTIVE_LOW>;
};
led-5 {
/* green:lan3-right */
function = LED_FUNCTION_ACTIVITY;
function-enumerator = <5>;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpioa 25 GPIO_ACTIVE_LOW>;
};
led-6 {
/* green:lan4-left */
function = LED_FUNCTION_ACTIVITY;
function-enumerator = <6>;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpioa 28 GPIO_ACTIVE_LOW>;
};
led-7 {
/* green:lan4-right */
function = LED_FUNCTION_ACTIVITY;
function-enumerator = <7>;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpioa 27 GPIO_ACTIVE_LOW>;
};
led-8 {
/* green:wan-left */
function = LED_FUNCTION_ACTIVITY;
function-enumerator = <8>;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpioa 30 GPIO_ACTIVE_LOW>;
};
led-9 {
/* green:wan-right */
function = LED_FUNCTION_ACTIVITY;
function-enumerator = <9>;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpioa 29 GPIO_ACTIVE_LOW>;
};
led-a {
/* amber:power */
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_AMBER>;
gpios = <&gpioa 0 GPIO_ACTIVE_LOW>;
default-state = "on";
};
led-b {
/* white:status */
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_WHITE>;
gpios = <&gpioa 31 GPIO_ACTIVE_HIGH>;
};
};
};
&srab {
compatible = "brcm,bcm58625-srab", "brcm,nsp-srab";
status = "okay";
ports {
port@0 {
label = "lan1";
reg = <0>;
};
port@1 {
label = "lan2";
reg = <1>;
};
port@2 {
label = "lan3";
reg = <2>;
};
port@3 {
label = "lan4";
reg = <3>;
};
port@4 {
label = "wan";
reg = <4>;
};
port@8 {
ethernet = <&amac2>;
reg = <8>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};

25
arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts Normal file
View File

@ -0,0 +1,25 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Device Tree Bindings for Cisco Meraki MX64 with A0 SoC.
*
* Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
*/
/dts-v1/;
#include "bcm958625-meraki-kingpin.dtsi"
#include "bcm-nsp-ax.dtsi"
/ {
model = "Cisco Meraki MX64(A0)";
compatible = "meraki,mx64-a0", "brcm,bcm58625", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
};
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x80000000>;
};
};

24
arch/arm/boot/dts/bcm958625-meraki-mx64.dts Normal file
View File

@ -0,0 +1,24 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Device Tree Bindings for Cisco Meraki MX64 with B0+ SoC.
*
* Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
*/
/dts-v1/;
#include "bcm958625-meraki-kingpin.dtsi"
/ {
model = "Cisco Meraki MX64";
compatible = "meraki,mx64", "brcm,bcm58625", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
};
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x80000000>;
};
};

33
arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts Normal file
View File

@ -0,0 +1,33 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Device Tree Bindings for Cisco Meraki MX64W with A0 SoC.
*
* Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
*/
/dts-v1/;
#include "bcm958625-meraki-kingpin.dtsi"
#include "bcm-nsp-ax.dtsi"
/ {
model = "Cisco Meraki MX64W(A0)";
compatible = "meraki,mx64w-a0", "brcm,bcm58625", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
};
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x80000000>;
};
};
&pcie0 {
status = "okay";
};
&pcie1 {
status = "okay";
};

32
arch/arm/boot/dts/bcm958625-meraki-mx64w.dts Normal file
View File

@ -0,0 +1,32 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Device Tree Bindings for Cisco Meraki MX64W with B0+ SoC.
*
* Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
*/
/dts-v1/;
#include "bcm958625-meraki-kingpin.dtsi"
/ {
model = "Cisco Meraki MX64W";
compatible = "meraki,mx64w", "brcm,bcm58625", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
};
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x80000000>;
};
};
&pcie0 {
status = "okay";
};
&pcie1 {
status = "okay";
};

24
arch/arm/boot/dts/bcm958625-meraki-mx65.dts Normal file
View File

@ -0,0 +1,24 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Device Tree Bindings for Cisco Meraki MX65.
*
* Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
*/
/dts-v1/;
#include "bcm958625-meraki-alamo.dtsi"
/ {
model = "Cisco Meraki MX65";
compatible = "meraki,mx65", "brcm,bcm58625", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
};
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x80000000>;
};
};

32
arch/arm/boot/dts/bcm958625-meraki-mx65w.dts Normal file
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@ -0,0 +1,32 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Device Tree Bindings for Cisco Meraki MX65W.
*
* Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
*/
/dts-v1/;
#include "bcm958625-meraki-alamo.dtsi"
/ {
model = "Cisco Meraki MX65W";
compatible = "meraki,mx65w", "brcm,bcm58625", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
};
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x80000000>;
};
};
&pcie0 {
status = "okay";
};
&pcie1 {
status = "okay";
};

129
arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi Normal file
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@ -0,0 +1,129 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Common Bindings for Cisco Meraki MX64 (Kingpin) and MX65 (Alamo) devices.
*
* Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
*/
#include "bcm-nsp.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
pwm-leds {
compatible = "pwm-leds";
led-1 {
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_RED>;
pwms = <&pwm 1 50000>;
max-brightness = <255>;
};
led-2 {
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_GREEN>;
pwms = <&pwm 2 50000>;
max-brightness = <255>;
};
led-3 {
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_BLUE>;
pwms = <&pwm 3 50000>;
max-brightness = <255>;
};
};
};
&amac2 {
status = "okay";
};
&ehci0 {
status = "okay";
};
&i2c0 {
status = "okay";
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
read-only;
};
};
&nand_controller {
nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
#address-cells = <1>;
#size-cells = <1>;
nand-ecc-strength = <24>;
nand-ecc-step-size = <1024>;
brcm,nand-oob-sector-size = <27>;
partition@0 {
label = "u-boot";
reg = <0x0 0x80000>;
read-only;
};
partition@80000 {
label = "shmoo";
reg = <0x80000 0x80000>;
read-only;
};
partition@100000 {
label = "bootkernel1";
reg = <0x100000 0x300000>;
};
partition@400000 {
label = "nvram";
reg = <0x400000 0x100000>;
};
partition@500000 {
label = "bootkernel2";
reg = <0x500000 0x300000>;
};
partition@800000 {
label = "ubi";
reg = <0x800000 0x3f700000>;
};
};
};
&ohci0 {
status = "okay";
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&pwm_leds>;
pwm_leds: pwm_leds {
function = "pwm";
groups = "pwm1_grp", "pwm2_grp", "pwm3_grp";
};
};
&pwm {
status = "okay";
#pwm-cells = <2>;
};
&uart0 {
clock-frequency = <62500000>;
status = "okay";
};

3
arch/arm/boot/dts/bcm958625hr.dts
View File

@ -37,7 +37,7 @@
/ {
model = "NorthStar Plus SVK (BCM958625HR)";
compatible = "brcm,bcm58625", "brcm,nsp";
compatible = "brcm,bcm958625hr", "brcm,bcm58625", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
@ -149,6 +149,7 @@ nand_sel: nand_sel {
};
&qspi {
status = "okay";
bspi-sel = <0>;
flash: m25p80@0 {
#address-cells = <1>;

3
arch/arm/boot/dts/bcm958625k.dts
View File

@ -36,7 +36,7 @@
/ {
model = "NorthStar Plus SVK (BCM958625K)";
compatible = "brcm,bcm58625", "brcm,nsp";
compatible = "brcm,bcm958625k", "brcm,bcm58625", "brcm,nsp";
chosen {
stdout-path = "serial0:115200n8";
@ -153,6 +153,7 @@ &pwm {
};
&qspi {
status = "okay";
bspi-sel = <0>;
flash: m25p80@0 {
#address-cells = <1>;

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