mirror of
https://github.com/Qortal/Brooklyn.git
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Torchie The Cat Source
This commit is contained in:
parent
95a1728f76
commit
e9f98f07aa
11
Makefile
11
Makefile
@ -1,16 +1,13 @@
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# SPDX-License-Identifier: GPL-2.0
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#
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# Fuck you T3Q.. I hope you drown in your own shit.
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# This build is optimized for the core version 3.3.x and onwards. Welcome abroad Digibyte and Raven
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# You two projects will feel comfortable now on Sinclair Titan Plus
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#
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# -Scare Crowe
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#
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VERSION = 5
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PATCHLEVEL = 60
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SUBLEVEL = 18
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EXTRAVERSION = -TP
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NAME = Sinclair Titan Plus
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PATCHLEVEL = 80
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SUBLEVEL = 11
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EXTRAVERSION = Titan
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NAME = Torchie The Cat
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# *DOCUMENTATION*
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# To see a list of typical targets execute "make help"
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22
README
22
README
@ -1,9 +1,10 @@
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Brooklyn, The Blockchain Linux 5.80.11 64bit RPI4 by Scare Crow
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================================================================
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Brooklyn Torchie The Cat, The Blockchain Linux 5.80.11 64bit RPI4 by Scare Crow
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===============================================================================
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* This build is optimized for the core version 3.3.x and onwards. Welcome abroad Digibyte and Raven
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* You two projects will feel comfortable now on Torchie
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* Brooklyn Torchie The Cat 5.80.11 is here. meh! (First ever release on the planet to use ARM Turbo Clocks & full ARM NEON Crypto Engine)
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This release brings more optimizations to QortalOS. Too many to name in a single README. From now on, Crowetic is the sole custodian of all releases and code.
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This release brings more optimizations to QortalOS. Too many to name in a single README.
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-Scare Crowe
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@ -34,17 +35,10 @@ Use logout from MATE Desktop to prevent locked screen sessions in the first plac
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* V1.1 XFCE is based on Brooklyn Jackwagon 5.12.10 LTS
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* V1.1 MATE-LXDE is based on Brookltn Plumbus 5.12.10 LTS
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==========================================================
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If this has helped you in any way then throw me some
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LTC for R&D or a few Sneaker / Bounty chocolates
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Personal LTC: nothing needed from you fucks
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Personal QORT: ditto asshats. shove it up your asses
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-/ Scare Crowe was awaken by the asshat crowetic again. Fuck you jack for fucking things up again.
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-/ Scare Crowe was awaken by the asshat crowetic again.
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Forever greets to my moosey Sean , Russell & Gisele who have been around unconditionally unlike the rest of fucking conditional dicks.
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Before I forget, fuck you T3Q. I hope you gargle with your own shit and die you inbred piece of shit.
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GNUK Token Implementation
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Source: http://www.gniibe.org
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@ -69,8 +63,8 @@ You can get a release and flash it directly on your USB 3 hard drive with Balena
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Pro Tip: Do not add another Desktop overlay or replace the current with something else. It will make the system unstable and unreliable. What comes pre-shipped with the packaged image is built around the kernel and whatever else was done with it. Be smart, don't be a crowetic. LMAO!
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QortalOS Linux Kernel 5.60.14
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=============================
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Legacy QortalOS Linux Kernel 5.60.14
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====================================
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This thing is way ahead of kernel.org releases for a reason. Go figure...
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9
arch/arc/include/uapi/asm/bpf_perf_event.h
Normal file
9
arch/arc/include/uapi/asm/bpf_perf_event.h
Normal file
@ -0,0 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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#ifndef _UAPI__ASM_BPF_PERF_EVENT_H__
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#define _UAPI__ASM_BPF_PERF_EVENT_H__
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#include <asm/ptrace.h>
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typedef struct user_regs_struct bpf_user_pt_regs_t;
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#endif /* _UAPI__ASM_BPF_PERF_EVENT_H__ */
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86
arch/arm/boot/compressed/misc-ep93xx.h
Normal file
86
arch/arm/boot/compressed/misc-ep93xx.h
Normal file
@ -0,0 +1,86 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
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*/
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#include <asm/mach-types.h>
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static inline unsigned int __raw_readl(unsigned int ptr)
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{
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return *((volatile unsigned int *)ptr);
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}
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static inline void __raw_writeb(unsigned char value, unsigned int ptr)
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{
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*((volatile unsigned char *)ptr) = value;
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}
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static inline void __raw_writel(unsigned int value, unsigned int ptr)
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{
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*((volatile unsigned int *)ptr) = value;
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}
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/*
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* Some bootloaders don't turn off DMA from the ethernet MAC before
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* jumping to linux, which means that we might end up with bits of RX
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* status and packet data scribbled over the uncompressed kernel image.
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* Work around this by resetting the ethernet MAC before we uncompress.
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*/
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#define PHYS_ETH_SELF_CTL 0x80010020
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#define ETH_SELF_CTL_RESET 0x00000001
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static inline void ep93xx_ethernet_reset(void)
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{
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unsigned int v;
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/* Reset the ethernet MAC. */
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v = __raw_readl(PHYS_ETH_SELF_CTL);
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__raw_writel(v | ETH_SELF_CTL_RESET, PHYS_ETH_SELF_CTL);
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/* Wait for reset to finish. */
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while (__raw_readl(PHYS_ETH_SELF_CTL) & ETH_SELF_CTL_RESET)
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;
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}
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#define TS72XX_WDT_CONTROL_PHYS_BASE 0x23800000
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#define TS72XX_WDT_FEED_PHYS_BASE 0x23c00000
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#define TS72XX_WDT_FEED_VAL 0x05
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static inline void __maybe_unused ts72xx_watchdog_disable(void)
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{
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__raw_writeb(TS72XX_WDT_FEED_VAL, TS72XX_WDT_FEED_PHYS_BASE);
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__raw_writeb(0, TS72XX_WDT_CONTROL_PHYS_BASE);
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}
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static inline void ep93xx_decomp_setup(void)
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{
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if (machine_is_ts72xx())
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ts72xx_watchdog_disable();
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if (machine_is_adssphere() ||
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machine_is_edb9301() ||
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machine_is_edb9302() ||
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machine_is_edb9302a() ||
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machine_is_edb9302a() ||
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machine_is_edb9307() ||
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machine_is_edb9307a() ||
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machine_is_edb9307a() ||
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machine_is_edb9312() ||
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machine_is_edb9315() ||
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machine_is_edb9315a() ||
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machine_is_edb9315a() ||
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machine_is_gesbc9312() ||
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machine_is_micro9() ||
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machine_is_micro9l() ||
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machine_is_micro9m() ||
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machine_is_micro9s() ||
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machine_is_micro9m() ||
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machine_is_micro9l() ||
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machine_is_micro9s() ||
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machine_is_sim_one() ||
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machine_is_snapper_cl15() ||
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machine_is_ts72xx() ||
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machine_is_bk3() ||
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machine_is_vision_ep9307())
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ep93xx_ethernet_reset();
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}
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190
arch/arm/boot/dts/aspeed-bmc-qcom-dc-scm-v1.dts
Normal file
190
arch/arm/boot/dts/aspeed-bmc-qcom-dc-scm-v1.dts
Normal file
@ -0,0 +1,190 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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// Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
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/dts-v1/;
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#include "aspeed-g6.dtsi"
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/ {
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model = "Qualcomm DC-SCM V1 BMC";
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compatible = "qcom,dc-scm-v1-bmc", "aspeed,ast2600";
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aliases {
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serial4 = &uart5;
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};
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chosen {
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stdout-path = &uart5;
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bootargs = "console=ttyS4,115200n8";
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x40000000>;
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};
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};
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&mdio3 {
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status = "okay";
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ethphy3: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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&mac2 {
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status = "okay";
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/* Bootloader sets up the MAC to insert delay */
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phy-mode = "rgmii";
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phy-handle = <ðphy3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_rgmii3_default>;
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};
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&mac3 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_rmii4_default>;
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use-ncsi;
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};
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&rtc {
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status = "okay";
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};
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&fmc {
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status = "okay";
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flash@0 {
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status = "okay";
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m25p,fast-read;
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label = "bmc";
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spi-max-frequency = <133000000>;
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#include "openbmc-flash-layout-64.dtsi"
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};
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flash@1 {
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status = "okay";
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m25p,fast-read;
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label = "alt-bmc";
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spi-max-frequency = <133000000>;
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#include "openbmc-flash-layout-64-alt.dtsi"
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};
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};
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&spi1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi1_default>;
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flash@0 {
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status = "okay";
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m25p,fast-read;
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label = "bios";
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spi-max-frequency = <133000000>;
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};
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};
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&gpio0 {
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gpio-line-names =
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/*A0-A7*/ "","","","","","","","",
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/*B0-B7*/ "BMC_FLASH_MUX_SEL","","","","","","","",
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/*C0-C7*/ "","","","","","","","",
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/*D0-D7*/ "","","","","","","","",
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/*E0-E7*/ "","","","","","","","",
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/*F0-F7*/ "","","","","","","","",
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/*G0-G7*/ "","","","","","","","",
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/*H0-H7*/ "","","","","","","","",
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/*I0-I7*/ "","","","","","","","",
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/*J0-J7*/ "","","","","","","","",
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/*K0-K7*/ "","","","","","","","",
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/*L0-L7*/ "","","","","","","","",
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/*M0-M7*/ "","","","","","","","",
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/*N0-N7*/ "BMC_FWSPI_RST_N","","GPIO_1_BMC_3V3","","","","","",
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/*O0-O7*/ "JTAG_MUX_A","JTAG_MUX_B","","","","","","",
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/*P0-P7*/ "","","","","","","","",
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/*Q0-Q7*/ "","","","","","","","",
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/*R0-R7*/ "","","","","","","","",
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/*S0-S7*/ "","","","","","","","",
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/*T0-T7*/ "","","","","","","","",
|
||||
/*U0-U7*/ "","","","","","","","",
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||||
/*V0-V7*/ "","","","SCMFPGA_SPARE_GPIO1_3V3",
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"SCMFPGA_SPARE_GPIO2_3V3","SCMFPGA_SPARE_GPIO3_3V3",
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"SCMFPGA_SPARE_GPIO4_3V3","SCMFPGA_SPARE_GPIO5_3V3",
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/*W0-W7*/ "","","","","","","","",
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/*X0-X7*/ "","","","","","","","",
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||||
/*Y0-Y7*/ "","","","","","","","",
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/*Z0-Z7*/ "","","","","","","","",
|
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/*AA0-AA7*/ "","","","","","","","",
|
||||
/*AB0-AB7*/ "","","","","","","","",
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||||
/*AC0-AC7*/ "","","","","","","","";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
gpio-line-names =
|
||||
/*A0-A7*/ "GPI_1_BMC_1V8","","","","","",
|
||||
"SCMFPGA_SPARE_GPIO1_1V8","SCMFPGA_SPARE_GPIO2_1V8",
|
||||
/*B0-B7*/ "SCMFPGA_SPARE_GPIO3_1V8","SCMFPGA_SPARE_GPIO4_1V8",
|
||||
"SCMFPGA_SPARE_GPIO5_1V8","","","","","",
|
||||
/*C0-C7*/ "","","","","","","","",
|
||||
/*D0-D7*/ "","BMC_SPI1_RST_N","BIOS_FLASH_MUX_SEL","",
|
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"","TPM2_PIRQ_N","TPM2_RST_N","",
|
||||
/*E0-E7*/ "","","","","","","","";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c8 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c9 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c10 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c12 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c13 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c14 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c15 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vhub {
|
||||
status = "okay";
|
||||
};
|
221
arch/arm/boot/dts/bcm2709-rpi-cm2.dts
Normal file
221
arch/arm/boot/dts/bcm2709-rpi-cm2.dts
Normal file
@ -0,0 +1,221 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm2709.dtsi"
|
||||
#include "bcm2709-rpi.dtsi"
|
||||
#include "bcm283x-rpi-csi0-2lane.dtsi"
|
||||
#include "bcm283x-rpi-csi1-4lane.dtsi"
|
||||
#include "bcm283x-rpi-i2c0mux_0_28.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "raspberrypi,2-compute-module", "brcm,bcm2836";
|
||||
model = "Raspberry Pi Compute Module 2";
|
||||
};
|
||||
|
||||
&cam1_reg {
|
||||
gpio = <&gpio 2 GPIO_ACTIVE_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cam0_reg: &cam0_regulator {
|
||||
gpio = <&gpio 30 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio {
|
||||
/*
|
||||
* This is based on the official GPU firmware DT blob.
|
||||
*
|
||||
* Legend:
|
||||
* "NC" = not connected (no rail from the SoC)
|
||||
* "FOO" = GPIO line named "FOO" on the schematic
|
||||
* "FOO_N" = GPIO line named "FOO" on schematic, active low
|
||||
*/
|
||||
gpio-line-names = "GPIO0",
|
||||
"GPIO1",
|
||||
"GPIO2",
|
||||
"GPIO3",
|
||||
"GPIO4",
|
||||
"GPIO5",
|
||||
"GPIO6",
|
||||
"GPIO7",
|
||||
"GPIO8",
|
||||
"GPIO9",
|
||||
"GPIO10",
|
||||
"GPIO11",
|
||||
"GPIO12",
|
||||
"GPIO13",
|
||||
"GPIO14",
|
||||
"GPIO15",
|
||||
"GPIO16",
|
||||
"GPIO17",
|
||||
"GPIO18",
|
||||
"GPIO19",
|
||||
"GPIO20",
|
||||
"GPIO21",
|
||||
"GPIO22",
|
||||
"GPIO23",
|
||||
"GPIO24",
|
||||
"GPIO25",
|
||||
"GPIO26",
|
||||
"GPIO27",
|
||||
"GPIO28",
|
||||
"GPIO29",
|
||||
"GPIO30",
|
||||
"GPIO31",
|
||||
"GPIO32",
|
||||
"GPIO33",
|
||||
"GPIO34",
|
||||
"GPIO35",
|
||||
"GPIO36",
|
||||
"GPIO37",
|
||||
"GPIO38",
|
||||
"GPIO39",
|
||||
"GPIO40",
|
||||
"GPIO41",
|
||||
"GPIO42",
|
||||
"GPIO43",
|
||||
"GPIO44",
|
||||
"GPIO45",
|
||||
"SMPS_SCL",
|
||||
"SMPS_SDA",
|
||||
/* Used by eMMC */
|
||||
"SD_CLK_R",
|
||||
"SD_CMD_R",
|
||||
"SD_DATA0_R",
|
||||
"SD_DATA1_R",
|
||||
"SD_DATA2_R",
|
||||
"SD_DATA3_R";
|
||||
|
||||
spi0_pins: spi0_pins {
|
||||
brcm,pins = <9 10 11>;
|
||||
brcm,function = <4>; /* alt0 */
|
||||
};
|
||||
|
||||
spi0_cs_pins: spi0_cs_pins {
|
||||
brcm,pins = <8 7>;
|
||||
brcm,function = <1>; /* output */
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0 {
|
||||
brcm,pins = <0 1>;
|
||||
brcm,function = <4>;
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1 {
|
||||
brcm,pins = <2 3>;
|
||||
brcm,function = <4>;
|
||||
};
|
||||
|
||||
i2s_pins: i2s {
|
||||
brcm,pins = <18 19 20 21>;
|
||||
brcm,function = <4>; /* alt0 */
|
||||
};
|
||||
|
||||
audio_pins: audio_pins {
|
||||
brcm,pins;
|
||||
brcm,function;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
virtgpio: virtgpio {
|
||||
compatible = "brcm,bcm2835-virtgpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
firmware = <&firmware>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&firmware {
|
||||
expgpio: expgpio {
|
||||
compatible = "raspberrypi,firmware-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names = "HDMI_HPD_N",
|
||||
"EMMC_EN_N",
|
||||
"NC",
|
||||
"NC",
|
||||
"NC",
|
||||
"NC",
|
||||
"NC",
|
||||
"NC";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_pins &spi0_cs_pins>;
|
||||
cs-gpios = <&gpio 8 1>, <&gpio 7 1>;
|
||||
|
||||
spidev0: spidev@0{
|
||||
compatible = "spidev";
|
||||
reg = <0>; /* CE0 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
spi-max-frequency = <125000000>;
|
||||
};
|
||||
|
||||
spidev1: spidev@1{
|
||||
compatible = "spidev";
|
||||
reg = <1>; /* CE1 */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
spi-max-frequency = <125000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0if {
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
&i2s {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s_pins>;
|
||||
};
|
||||
|
||||
&leds {
|
||||
act_led: led-act {
|
||||
label = "led0";
|
||||
linux,default-trigger = "mmc0";
|
||||
gpios = <&virtgpio 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
hpd-gpios = <&expgpio 0 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&vchiq {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&audio_pins>;
|
||||
};
|
||||
|
||||
/ {
|
||||
__overrides__ {
|
||||
audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_hdmi=0'}";
|
||||
|
||||
act_led_gpio = <&act_led>,"gpios:4";
|
||||
act_led_activelow = <&act_led>,"gpios:8";
|
||||
act_led_trigger = <&act_led>,"linux,default-trigger";
|
||||
cam0_reg = <&cam0_reg>,"status";
|
||||
cam0_reg_gpio = <&cam0_reg>,"gpio:4";
|
||||
cam1_reg = <&cam1_reg>,"status";
|
||||
cam1_reg_gpio = <&cam1_reg>,"gpio:4";
|
||||
};
|
||||
};
|
192
arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi
Normal file
192
arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi
Normal file
@ -0,0 +1,192 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Broadcom BCM470X / BCM5301X ARM platform code.
|
||||
* DTS for Buffalo WZR-1166DHP and WZR-1166DHP2
|
||||
*
|
||||
* Copyright (C) 2014 Rafał Miłecki <zajec5@gmail.com>
|
||||
* Copyright (C) 2022 SHIMAMOTO Takayoshi <takayoshi.shimamoto.360@gmail.com>
|
||||
*/
|
||||
|
||||
|
||||
#include "bcm4708.dtsi"
|
||||
#include "bcm5301x-nand-cs0-bch8.dtsi"
|
||||
#include <dt-bindings/leds/common.h>
|
||||
|
||||
/ {
|
||||
spi {
|
||||
compatible = "spi-gpio";
|
||||
num-chipselects = <1>;
|
||||
gpio-sck = <&chipcommon 7 0>;
|
||||
gpio-mosi = <&chipcommon 4 0>;
|
||||
cs-gpios = <&chipcommon 6 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
hc595: gpio_spi@0 {
|
||||
compatible = "fairchild,74hc595";
|
||||
reg = <0>;
|
||||
registers-number = <1>;
|
||||
spi-max-frequency = <100000>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
usb {
|
||||
/* label = "bcm53xx:blue:usb"; */
|
||||
function = LED_FUNCTION_USB;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
gpios = <&hc595 0 GPIO_ACTIVE_HIGH>;
|
||||
trigger-sources = <&ohci_port1>, <&ehci_port1>,
|
||||
<&xhci_port1>, <&ohci_port2>,
|
||||
<&ehci_port2>;
|
||||
linux,default-trigger = "usbport";
|
||||
};
|
||||
|
||||
power0 {
|
||||
/* label = "bcm53xx:red:power"; */
|
||||
function = LED_FUNCTION_FAULT;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
gpios = <&hc595 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
power1 {
|
||||
/* label = "bcm53xx:white:power"; */
|
||||
function = LED_FUNCTION_POWER;
|
||||
color = <LED_COLOR_ID_WHITE>;
|
||||
gpios = <&hc595 2 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
|
||||
router0 {
|
||||
/* label = "bcm53xx:blue:router"; */
|
||||
function = LED_FUNCTION_STATUS;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
gpios = <&hc595 3 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
|
||||
router1 {
|
||||
/* label = "bcm53xx:amber:router"; */
|
||||
function = LED_FUNCTION_STATUS;
|
||||
color = <LED_COLOR_ID_AMBER>;
|
||||
gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wan {
|
||||
/* label = "bcm53xx:blue:wan"; */
|
||||
function = LED_FUNCTION_WAN;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
|
||||
wireless0 {
|
||||
/* label = "bcm53xx:blue:wireless"; */
|
||||
function = LED_FUNCTION_WLAN;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
gpios = <&hc595 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wireless1 {
|
||||
/* label = "bcm53xx:amber:wireless"; */
|
||||
function = LED_FUNCTION_WLAN;
|
||||
color = <LED_COLOR_ID_AMBER>;
|
||||
gpios = <&hc595 7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
button-restart {
|
||||
label = "Reset";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
button-aoss {
|
||||
label = "AOSS";
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
/* Commit mode set by switch? */
|
||||
button-mode {
|
||||
label = "Mode";
|
||||
linux,code = <KEY_SETUP>;
|
||||
gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
/* Switch: AP mode */
|
||||
button-sw-ap {
|
||||
label = "AP";
|
||||
linux,code = <BTN_0>;
|
||||
gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
button-eject {
|
||||
label = "USB eject";
|
||||
linux,code = <KEY_EJECTCD>;
|
||||
gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb2 {
|
||||
vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&usb3 {
|
||||
vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&spi_nor {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&srab {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "wan";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
label = "cpu";
|
||||
ethernet = <&gmac0>;
|
||||
};
|
||||
};
|
||||
};
|
26
arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp.dts
Normal file
26
arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp.dts
Normal file
@ -0,0 +1,26 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Device Tree Bindigs for Buffalo WZR-1166DHP
|
||||
*
|
||||
* Copyright (C) 2022 SHIMAMOTO Takayoshi <takayoshi.shimamoto.360@gmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm4708-buffalo-wzr-1166dhp-common.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "buffalo,wzr-1166dhp", "brcm,bcm4708";
|
||||
model = "Buffalo WZR-1166DHP";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x08000000>,
|
||||
<0x88000000 0x18000000>;
|
||||
};
|
||||
|
||||
};
|
26
arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts
Normal file
26
arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp2.dts
Normal file
@ -0,0 +1,26 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Device Tree Bindigs for Buffalo WZR-1166DHP2
|
||||
*
|
||||
* Copyright (C) 2022 SHIMAMOTO Takayoshi <takayoshi.shimamoto.360@gmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm4708-buffalo-wzr-1166dhp-common.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "buffalo,wzr-1166dhp2", "brcm,bcm4708";
|
||||
model = "Buffalo WZR-1166DHP2";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x08000000>,
|
||||
<0x88000000 0x08000000>;
|
||||
};
|
||||
|
||||
};
|
130
arch/arm/boot/dts/bcm47622.dtsi
Normal file
130
arch/arm/boot/dts/bcm47622.dtsi
Normal file
@ -0,0 +1,130 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm47622", "brcm,bcmbca";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CA7_0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
CA7_1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
CA7_2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x2>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
CA7_3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x3>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
arm,cpu-registers-not-fw-configured;
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a7-pmu";
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&CA7_0>, <&CA7_1>,
|
||||
<&CA7_2>, <&CA7_3>;
|
||||
};
|
||||
|
||||
clocks: clocks {
|
||||
periph_clk: periph-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
|
||||
uart_clk: uart-clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&periph_clk>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
axi@81000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x81000000 0x8000>;
|
||||
|
||||
gic: interrupt-controller@1000 {
|
||||
compatible = "arm,cortex-a7-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
reg = <0x1000 0x1000>,
|
||||
<0x2000 0x2000>,
|
||||
<0x4000 0x2000>,
|
||||
<0x6000 0x2000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus@ff800000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0xff800000 0x800000>;
|
||||
|
||||
uart0: serial@12000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x12000 0x1000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uart_clk>, <&uart_clk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
166
arch/arm/boot/dts/bcm53015-meraki-mr26.dts
Normal file
166
arch/arm/boot/dts/bcm53015-meraki-mr26.dts
Normal file
@ -0,0 +1,166 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Broadcom BCM470X / BCM5301X ARM platform code.
|
||||
* DTS for Meraki MR26 / Codename: Venom
|
||||
*
|
||||
* Copyright (C) 2022 Christian Lamparter <chunkeey@gmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm4708.dtsi"
|
||||
#include "bcm5301x-nand-cs0-bch8.dtsi"
|
||||
#include <dt-bindings/leds/common.h>
|
||||
|
||||
/ {
|
||||
compatible = "meraki,mr26", "brcm,bcm53015", "brcm,bcm4708";
|
||||
model = "Meraki MR26";
|
||||
|
||||
memory@0 {
|
||||
reg = <0x00000000 0x08000000>;
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led-0 {
|
||||
function = LED_FUNCTION_FAULT;
|
||||
color = <LED_COLOR_ID_AMBER>;
|
||||
gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>;
|
||||
panic-indicator;
|
||||
};
|
||||
led-1 {
|
||||
function = LED_FUNCTION_INDICATOR;
|
||||
color = <LED_COLOR_ID_WHITE>;
|
||||
gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
key-restart {
|
||||
label = "Reset";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
clock-frequency = <50000000>;
|
||||
/delete-property/ clocks;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
status = "disabled";
|
||||
};
|
||||
&gmac2 {
|
||||
status = "disabled";
|
||||
};
|
||||
&gmac3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&nandcs {
|
||||
nand-ecc-algo = "hw";
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
|
||||
partition@0 {
|
||||
label = "u-boot";
|
||||
reg = <0x0 0x200000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@200000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x200000 0x200000>;
|
||||
/* empty */
|
||||
};
|
||||
|
||||
partition@400000 {
|
||||
label = "u-boot-backup";
|
||||
reg = <0x400000 0x200000>;
|
||||
/* empty */
|
||||
};
|
||||
|
||||
partition@600000 {
|
||||
label = "u-boot-env-backup";
|
||||
reg = <0x600000 0x200000>;
|
||||
/* empty */
|
||||
};
|
||||
|
||||
partition@800000 {
|
||||
label = "ubi";
|
||||
reg = <0x800000 0x7780000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&srab {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "poe";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
label = "cpu";
|
||||
ethernet = <&gmac0>;
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
duplex-full;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinmux_i2c>;
|
||||
|
||||
clock-frequency = <100000>;
|
||||
|
||||
ina219@40 {
|
||||
compatible = "ti,ina219"; /* PoE power */
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <60000>; /* = 60 mOhms */
|
||||
};
|
||||
|
||||
eeprom@56 {
|
||||
compatible = "atmel,24c64";
|
||||
reg = <0x56>;
|
||||
pagesize = <32>;
|
||||
read-only;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* it's empty */
|
||||
};
|
||||
};
|
||||
|
||||
&thermal {
|
||||
status = "disabled";
|
||||
/* does not work, reads 418 degree Celsius */
|
||||
};
|
103
arch/arm/boot/dts/bcm63148.dtsi
Normal file
103
arch/arm/boot/dts/bcm63148.dtsi
Normal file
@ -0,0 +1,103 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm63148", "brcm,bcmbca";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
B15_0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "brcm,brahma-b15";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
B15_1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "brcm,brahma-b15";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a15-pmu";
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&B15_0>, <&B15_1>;
|
||||
};
|
||||
|
||||
clocks: clocks {
|
||||
periph_clk: periph-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
axi@80030000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x80030000 0x8000>;
|
||||
|
||||
gic: interrupt-controller@1000 {
|
||||
compatible = "arm,cortex-a15-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x1000 0x1000>,
|
||||
<0x2000 0x2000>,
|
||||
<0x4000 0x2000>,
|
||||
<0x6000 0x2000>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
};
|
||||
|
||||
bus@ff800000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0xfffe8000 0x8000>;
|
||||
|
||||
uart0: serial@600 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x600 0x20>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&periph_clk>;
|
||||
clock-names = "refclk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
118
arch/arm/boot/dts/bcm63178.dtsi
Normal file
118
arch/arm/boot/dts/bcm63178.dtsi
Normal file
@ -0,0 +1,118 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm63178", "brcm,bcmbca";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CA7_0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
CA7_1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
CA7_2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x2>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
arm,cpu-registers-not-fw-configured;
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a7-pmu";
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&CA7_0>, <&CA7_1>,
|
||||
<&CA7_2>;
|
||||
};
|
||||
|
||||
clocks: clocks {
|
||||
periph_clk: periph-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
uart_clk: uart-clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&periph_clk>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
cpu_off = <1>;
|
||||
cpu_on = <2>;
|
||||
};
|
||||
|
||||
axi@81000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x81000000 0x4000>;
|
||||
|
||||
gic: interrupt-controller@1000 {
|
||||
compatible = "arm,cortex-a7-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x1000 0x1000>,
|
||||
<0x2000 0x2000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus@ff800000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0xff800000 0x800000>;
|
||||
|
||||
uart0: serial@12000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x12000 0x1000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uart_clk>, <&uart_clk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
130
arch/arm/boot/dts/bcm6756.dtsi
Normal file
130
arch/arm/boot/dts/bcm6756.dtsi
Normal file
@ -0,0 +1,130 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm6756", "brcm,bcmbca";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CA7_0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
CA7_1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
CA7_2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x2>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
CA7_3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x3>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
arm,cpu-registers-not-fw-configured;
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a7-pmu";
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&CA7_0>, <&CA7_1>,
|
||||
<&CA7_2>, <&CA7_3>;
|
||||
};
|
||||
|
||||
clocks: clocks {
|
||||
periph_clk: periph-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
|
||||
uart_clk: uart-clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&periph_clk>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
axi@81000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x81000000 0x8000>;
|
||||
|
||||
gic: interrupt-controller@1000 {
|
||||
compatible = "arm,cortex-a7-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
reg = <0x1000 0x1000>,
|
||||
<0x2000 0x2000>,
|
||||
<0x4000 0x2000>,
|
||||
<0x6000 0x2000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus@ff800000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0xff800000 0x800000>;
|
||||
|
||||
uart0: serial@12000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x12000 0x1000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uart_clk>, <&uart_clk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
103
arch/arm/boot/dts/bcm6846.dtsi
Normal file
103
arch/arm/boot/dts/bcm6846.dtsi
Normal file
@ -0,0 +1,103 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm6846", "brcm,bcmbca";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CA7_0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
CA7_1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
arm,cpu-registers-not-fw-configured;
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a7-pmu";
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&CA7_0>, <&CA7_1>;
|
||||
};
|
||||
|
||||
clocks: clocks {
|
||||
periph_clk: periph-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
cpu_off = <1>;
|
||||
cpu_on = <2>;
|
||||
};
|
||||
|
||||
axi@81000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x81000000 0x4000>;
|
||||
|
||||
gic: interrupt-controller@1000 {
|
||||
compatible = "arm,cortex-a7-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x1000 0x1000>,
|
||||
<0x2000 0x2000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus@ff800000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0xff800000 0x800000>;
|
||||
|
||||
uart0: serial@640 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x640 0x1b>;
|
||||
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&periph_clk>;
|
||||
clock-names = "refclk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
120
arch/arm/boot/dts/bcm6855.dtsi
Normal file
120
arch/arm/boot/dts/bcm6855.dtsi
Normal file
@ -0,0 +1,120 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm6855", "brcm,bcmbca";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CA7_0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
CA7_1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
CA7_2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x2>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
arm,cpu-registers-not-fw-configured;
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a7-pmu";
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>;
|
||||
};
|
||||
|
||||
clocks: clocks {
|
||||
periph_clk: periph-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
|
||||
uart_clk: uart-clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&periph_clk>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
axi@81000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x81000000 0x8000>;
|
||||
|
||||
gic: interrupt-controller@1000 {
|
||||
compatible = "arm,cortex-a7-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
reg = <0x1000 0x1000>,
|
||||
<0x2000 0x2000>,
|
||||
<0x4000 0x2000>,
|
||||
<0x6000 0x2000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus@ff800000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0xff800000 0x800000>;
|
||||
|
||||
uart0: serial@12000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x12000 0x1000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uart_clk>, <&uart_clk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
110
arch/arm/boot/dts/bcm6878.dtsi
Normal file
110
arch/arm/boot/dts/bcm6878.dtsi
Normal file
@ -0,0 +1,110 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm6878", "brcm,bcmbca";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CA7_0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
CA7_1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x1>;
|
||||
next-level-cache = <&L2_0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
arm,cpu-registers-not-fw-configured;
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a7-pmu";
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&CA7_0>, <&CA7_1>;
|
||||
};
|
||||
|
||||
clocks: clocks {
|
||||
periph_clk: periph-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
uart_clk: uart-clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&periph_clk>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
axi@81000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x81000000 0x8000>;
|
||||
|
||||
gic: interrupt-controller@1000 {
|
||||
compatible = "arm,cortex-a7-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x1000 0x1000>,
|
||||
<0x2000 0x2000>,
|
||||
<0x4000 0x2000>,
|
||||
<0x6000 0x2000>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
};
|
||||
|
||||
bus@ff800000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0xff800000 0x800000>;
|
||||
|
||||
uart0: serial@12000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x12000 0x1000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uart_clk>, <&uart_clk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
30
arch/arm/boot/dts/bcm947622.dts
Normal file
30
arch/arm/boot/dts/bcm947622.dts
Normal file
@ -0,0 +1,30 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2019 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm47622.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Broadcom BCM947622 Reference Board";
|
||||
compatible = "brcm,bcm947622", "brcm,bcm47622", "brcm,bcmbca";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x08000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
27
arch/arm/boot/dts/bcm963138.dts
Normal file
27
arch/arm/boot/dts/bcm963138.dts
Normal file
@ -0,0 +1,27 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm63138.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Broadcom BCM963138 Reference Board";
|
||||
compatible = "brcm,bcm963138", "brcm,bcm63138", "brcm,bcmbca";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
stdout-path = &serial0;
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x08000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
status = "okay";
|
||||
};
|
30
arch/arm/boot/dts/bcm963148.dts
Normal file
30
arch/arm/boot/dts/bcm963148.dts
Normal file
@ -0,0 +1,30 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2019 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm63148.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Broadcom BCM963148 Reference Board";
|
||||
compatible = "brcm,bcm963148", "brcm,bcm63148", "brcm,bcmbca";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x08000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
30
arch/arm/boot/dts/bcm963178.dts
Normal file
30
arch/arm/boot/dts/bcm963178.dts
Normal file
@ -0,0 +1,30 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2019 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm63178.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Broadcom BCM963178 Reference Board";
|
||||
compatible = "brcm,bcm963178", "brcm,bcm63178", "brcm,bcmbca";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x08000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
30
arch/arm/boot/dts/bcm96756.dts
Normal file
30
arch/arm/boot/dts/bcm96756.dts
Normal file
@ -0,0 +1,30 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2019 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm6756.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Broadcom BCM96756 Reference Board";
|
||||
compatible = "brcm,bcm96756", "brcm,bcm6756", "brcm,bcmbca";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x08000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
30
arch/arm/boot/dts/bcm96846.dts
Normal file
30
arch/arm/boot/dts/bcm96846.dts
Normal file
@ -0,0 +1,30 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm6846.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Broadcom BCM96846 Reference Board";
|
||||
compatible = "brcm,bcm96846", "brcm,bcm6846", "brcm,bcmbca";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x08000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
30
arch/arm/boot/dts/bcm96855.dts
Normal file
30
arch/arm/boot/dts/bcm96855.dts
Normal file
@ -0,0 +1,30 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2019 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm6855.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Broadcom BCM96855 Reference Board";
|
||||
compatible = "brcm,bcm96855", "brcm,bcm6855", "brcm,bcmbca";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x08000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
30
arch/arm/boot/dts/bcm96878.dts
Normal file
30
arch/arm/boot/dts/bcm96878.dts
Normal file
@ -0,0 +1,30 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2019 Broadcom Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm6878.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Broadcom BCM96878 Reference Board";
|
||||
compatible = "brcm,bcm96878", "brcm,bcm6878", "brcm,bcmbca";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x08000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
55
arch/arm/boot/dts/exynos-pinctrl.h
Normal file
55
arch/arm/boot/dts/exynos-pinctrl.h
Normal file
@ -0,0 +1,55 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Samsung Exynos DTS pinctrl constants
|
||||
*
|
||||
* Copyright (c) 2016 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
* Copyright (c) 2022 Linaro Ltd
|
||||
* Author: Krzysztof Kozlowski <krzk@kernel.org>
|
||||
*/
|
||||
|
||||
#ifndef __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__
|
||||
#define __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__
|
||||
|
||||
#define EXYNOS_PIN_PULL_NONE 0
|
||||
#define EXYNOS_PIN_PULL_DOWN 1
|
||||
#define EXYNOS_PIN_PULL_UP 3
|
||||
|
||||
/* Pin function in power down mode */
|
||||
#define EXYNOS_PIN_PDN_OUT0 0
|
||||
#define EXYNOS_PIN_PDN_OUT1 1
|
||||
#define EXYNOS_PIN_PDN_INPUT 2
|
||||
#define EXYNOS_PIN_PDN_PREV 3
|
||||
|
||||
/* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */
|
||||
#define EXYNOS4_PIN_DRV_LV1 0
|
||||
#define EXYNOS4_PIN_DRV_LV2 2
|
||||
#define EXYNOS4_PIN_DRV_LV3 1
|
||||
#define EXYNOS4_PIN_DRV_LV4 3
|
||||
|
||||
/* Drive strengths for Exynos5260 */
|
||||
#define EXYNOS5260_PIN_DRV_LV1 0
|
||||
#define EXYNOS5260_PIN_DRV_LV2 1
|
||||
#define EXYNOS5260_PIN_DRV_LV4 2
|
||||
#define EXYNOS5260_PIN_DRV_LV6 3
|
||||
|
||||
/*
|
||||
* Drive strengths for Exynos5410, Exynos542x, Exynos5800 and Exynos850 (except
|
||||
* GPIO_HSI block)
|
||||
*/
|
||||
#define EXYNOS5420_PIN_DRV_LV1 0
|
||||
#define EXYNOS5420_PIN_DRV_LV2 1
|
||||
#define EXYNOS5420_PIN_DRV_LV3 2
|
||||
#define EXYNOS5420_PIN_DRV_LV4 3
|
||||
|
||||
#define EXYNOS_PIN_FUNC_INPUT 0
|
||||
#define EXYNOS_PIN_FUNC_OUTPUT 1
|
||||
#define EXYNOS_PIN_FUNC_2 2
|
||||
#define EXYNOS_PIN_FUNC_3 3
|
||||
#define EXYNOS_PIN_FUNC_4 4
|
||||
#define EXYNOS_PIN_FUNC_5 5
|
||||
#define EXYNOS_PIN_FUNC_6 6
|
||||
#define EXYNOS_PIN_FUNC_EINT 0xf
|
||||
#define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT
|
||||
|
||||
#endif /* __DTS_ARM_SAMSUNG_EXYNOS_PINCTRL_H__ */
|
26
arch/arm/boot/dts/hpe-bmc-dl360gen10.dts
Normal file
26
arch/arm/boot/dts/hpe-bmc-dl360gen10.dts
Normal file
@ -0,0 +1,26 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree file for HPE DL360Gen10
|
||||
*/
|
||||
|
||||
/include/ "hpe-gxp.dtsi"
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "hpe,gxp-dl360gen10", "hpe,gxp";
|
||||
model = "Hewlett Packard Enterprise ProLiant dl360 Gen10";
|
||||
|
||||
aliases {
|
||||
serial0 = &uartc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x40000000 0x20000000>;
|
||||
};
|
||||
};
|
127
arch/arm/boot/dts/hpe-gxp.dtsi
Normal file
127
arch/arm/boot/dts/hpe-gxp.dtsi
Normal file
@ -0,0 +1,127 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree file for HPE GXP
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
model = "Hewlett Packard Enterprise GXP BMC";
|
||||
compatible = "hpe,gxp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
device_type = "cpu";
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
pll: clock-0 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1600000000>;
|
||||
};
|
||||
|
||||
iopclk: clock-1 {
|
||||
compatible = "fixed-factor-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-div = <4>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&pll>;
|
||||
};
|
||||
};
|
||||
|
||||
axi {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
dma-ranges;
|
||||
|
||||
L2: cache-controller@b0040000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0xb0040000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
ahb@c0000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0xc0000000 0x30000000>;
|
||||
dma-ranges;
|
||||
|
||||
vic0: interrupt-controller@eff0000 {
|
||||
compatible = "arm,pl192-vic";
|
||||
reg = <0xeff0000 0x1000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
vic1: interrupt-controller@80f00000 {
|
||||
compatible = "arm,pl192-vic";
|
||||
reg = <0x80f00000 0x1000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
uarta: serial@e0 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0xe0 0x8>;
|
||||
interrupts = <17>;
|
||||
interrupt-parent = <&vic0>;
|
||||
clock-frequency = <1846153>;
|
||||
reg-shift = <0>;
|
||||
};
|
||||
|
||||
uartb: serial@e8 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0xe8 0x8>;
|
||||
interrupts = <18>;
|
||||
interrupt-parent = <&vic0>;
|
||||
clock-frequency = <1846153>;
|
||||
reg-shift = <0>;
|
||||
};
|
||||
|
||||
uartc: serial@f0 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0xf0 0x8>;
|
||||
interrupts = <19>;
|
||||
interrupt-parent = <&vic0>;
|
||||
clock-frequency = <1846153>;
|
||||
reg-shift = <0>;
|
||||
};
|
||||
|
||||
usb0: usb@efe0000 {
|
||||
compatible = "hpe,gxp-ehci", "generic-ehci";
|
||||
reg = <0xefe0000 0x100>;
|
||||
interrupts = <7>;
|
||||
interrupt-parent = <&vic0>;
|
||||
};
|
||||
|
||||
st: timer@80 {
|
||||
compatible = "hpe,gxp-timer";
|
||||
reg = <0x80 0x16>;
|
||||
interrupts = <0>;
|
||||
interrupt-parent = <&vic0>;
|
||||
clocks = <&iopclk>;
|
||||
clock-names = "iop";
|
||||
};
|
||||
|
||||
usb1: usb@efe0100 {
|
||||
compatible = "hpe,gxp-ohci", "generic-ohci";
|
||||
reg = <0xefe0100 0x110>;
|
||||
interrupts = <6>;
|
||||
interrupt-parent = <&vic0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
113
arch/arm/boot/dts/imx6dl-colibri-aster.dts
Normal file
113
arch/arm/boot/dts/imx6dl-colibri-aster.dts
Normal file
@ -0,0 +1,113 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2022 Toradex
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-colibri.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Colibri iMX6DL/S on Colibri Aster Board";
|
||||
compatible = "toradex,colibri_imx6dl-aster", "toradex,colibri_imx6dl",
|
||||
"fsl,imx6dl";
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c2;
|
||||
i2c1 = &i2c3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
/* Colibri SSP */
|
||||
&ecspi4 {
|
||||
cs-gpios = <
|
||||
&gpio5 2 GPIO_ACTIVE_HIGH
|
||||
&gpio5 4 GPIO_ACTIVE_HIGH
|
||||
>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi4 &pinctrl_csi_gpio_2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <
|
||||
&pinctrl_csi_gpio_1
|
||||
&pinctrl_gpio_2
|
||||
&pinctrl_gpio_aster
|
||||
&pinctrl_usbh_oc_1
|
||||
&pinctrl_usbc_id_1
|
||||
&pinctrl_weim_gpio_5
|
||||
>;
|
||||
|
||||
pinctrl_gpio_aster: gpioaster {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
|
||||
MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
|
||||
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0
|
||||
MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
|
||||
MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
®_usb_host_vbus {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
vbus-supply = <®_usb_host_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri MMC */
|
||||
&usdhc1 {
|
||||
status = "okay";
|
||||
};
|
46
arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts
Normal file
46
arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts
Normal file
@ -0,0 +1,46 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2022 Toradex
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6dl-colibri-iris.dts"
|
||||
|
||||
/ {
|
||||
model = "Toradex Colibri iMX6DL/S on Colibri Iris V2 Board";
|
||||
compatible = "toradex,colibri_imx6dl-iris-v2", "toradex,colibri_imx6dl",
|
||||
"fsl,imx6dl";
|
||||
|
||||
reg_3v3_vmmc: regulator-3v3-vmmc {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enable_3v3_vmmc>;
|
||||
regulator-name = "3v3_vmmc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <100>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_iris &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1>;
|
||||
|
||||
pinctrl_enable_3v3_vmmc: enable3v3vmmcgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Colibri MMC */
|
||||
&usdhc1 {
|
||||
cap-power-off-card;
|
||||
/* uncomment the following to enable SD card UHS mode if you have a V1.1 module */
|
||||
/* /delete-property/ no-1-8-v; */
|
||||
vmmc-supply = <®_3v3_vmmc>;
|
||||
status = "okay";
|
||||
};
|
152
arch/arm/boot/dts/imx6dl-colibri-iris.dts
Normal file
152
arch/arm/boot/dts/imx6dl-colibri-iris.dts
Normal file
@ -0,0 +1,152 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2022 Toradex
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-colibri.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Colibri iMX6DL/S on Colibri Iris Board";
|
||||
compatible = "toradex,colibri_imx6dl-iris", "toradex,colibri_imx6dl",
|
||||
"fsl,imx6dl";
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c2;
|
||||
i2c1 = &i2c3;
|
||||
};
|
||||
|
||||
aliases {
|
||||
rtc0 = &rtc_i2c;
|
||||
rtc1 = &snvs_rtc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
/* Colibri SSP */
|
||||
&ecspi4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_forceoff &pinctrl_uart23_forceoff>;
|
||||
|
||||
/*
|
||||
* uart-a-on-x13-enable turns the UART transceiver for UART_A on. If one
|
||||
* wants to turn the transceiver off, that property has to be deleted
|
||||
* and the gpio handled in userspace.
|
||||
* The same applies to uart-b-c-on-x14-enable where the UART_B and
|
||||
* UART_C transceiver is turned on.
|
||||
*/
|
||||
uart-a-on-x13-enable-hog {
|
||||
gpio-hog;
|
||||
gpios = <4 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */
|
||||
output-high;
|
||||
};
|
||||
|
||||
uart-b-c-on-x14-enable-hog {
|
||||
gpio-hog;
|
||||
gpios = <8 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
|
||||
*/
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
|
||||
rtc_i2c: rtc@68 {
|
||||
compatible = "st,m41t0";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <
|
||||
&pinctrl_gpio_iris
|
||||
&pinctrl_usbh_oc_1
|
||||
&pinctrl_usbc_id_1
|
||||
>;
|
||||
|
||||
pinctrl_gpio_iris: gpioirisgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0
|
||||
MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0
|
||||
MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0
|
||||
MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0
|
||||
MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
|
||||
MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1_forceoff: uart1forceoffgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart23_forceoff: uart23forceoffgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
®_usb_host_vbus {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
vbus-supply = <®_usb_host_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri MMC */
|
||||
&usdhc1 {
|
||||
status = "okay";
|
||||
};
|
276
arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts
Normal file
276
arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts
Normal file
@ -0,0 +1,276 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2014-2022 Toradex
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include "imx6q.dtsi"
|
||||
#include "imx6qdl-apalis.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.2";
|
||||
compatible = "toradex,apalis_imx6q-ixora-v1.2", "toradex,apalis_imx6q",
|
||||
"fsl,imx6q";
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c3;
|
||||
i2c2 = &i2c2;
|
||||
rtc0 = &rtc_i2c;
|
||||
rtc1 = &snvs_rtc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_leds_ixora>;
|
||||
|
||||
led4-green {
|
||||
gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
|
||||
label = "LED_4_GREEN";
|
||||
};
|
||||
|
||||
led4-red {
|
||||
gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
|
||||
label = "LED_4_RED";
|
||||
};
|
||||
|
||||
led5-green {
|
||||
gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
|
||||
label = "LED_5_GREEN";
|
||||
};
|
||||
|
||||
led5-red {
|
||||
gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
|
||||
label = "LED_5_RED";
|
||||
};
|
||||
};
|
||||
|
||||
reg_3v3_vmmc: regulator-3v3-vmmc {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enable_3v3_vmmc>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-name = "3v3_vmmc";
|
||||
startup-delay-us = <100>;
|
||||
};
|
||||
|
||||
reg_can1_supply: regulator-can1-supply {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enable_can1_power>;
|
||||
regulator-name = "can1_supply";
|
||||
};
|
||||
|
||||
reg_can2_supply: regulator-can2-supply {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enable_can2_power>;
|
||||
regulator-name = "can2_supply";
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
xceiver-supply = <®_can1_supply>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can2 {
|
||||
xceiver-supply = <®_can2_supply>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart24_forceoff>;
|
||||
|
||||
/*
|
||||
* uart-2-4-on-x21-enable-hog enables the UART transceiver for Apalis
|
||||
* UART2 and UART3. If one wants to disable the transceiver force
|
||||
* the GPIO to output-low, if one wants to control the transceiver
|
||||
* from user space delete the hog node.
|
||||
*/
|
||||
uart-2-4-on-x21-enable-hog {
|
||||
gpio-hog;
|
||||
gpios = <11 GPIO_ACTIVE_HIGH>; /* MXM3 180 */
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
/* M41T0M6 real time clock on carrier board */
|
||||
rtc_i2c: rtc@68 {
|
||||
compatible = "st,m41t0";
|
||||
reg = <0x68>;
|
||||
};
|
||||
|
||||
eeprom: eeprom@50 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x50>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier
|
||||
* board)
|
||||
*/
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_reset_moci>;
|
||||
/* active-high meaning opposite of regular PERST# active-low polarity */
|
||||
reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpio-active-high;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
®_usb_host_vbus {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
®_usb_otg_vbus {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sound_spdif {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spdif {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
vbus-supply = <®_usb_host_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
vbus-supply = <®_usb_otg_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* MMC1 */
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_4bit_sleep &pinctrl_mmc_cd_sleep>;
|
||||
bus-width = <4>;
|
||||
cap-power-off-card;
|
||||
vmmc-supply = <®_3v3_vmmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_enable_3v3_vmmc: enable3v3vmmcgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enable_can1_power: enablecan1powergrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enable_can2_power: enablecan2powergrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart24_forceoff: uart24forceoffgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_leds_ixora: ledsixoragrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
|
||||
MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
|
||||
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_mmc_cd_sleep: mmccdslpgrp {
|
||||
fsl,pins = <
|
||||
/* MMC1 CD */
|
||||
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_4bit_sleep: usdhc1-4bitslpgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x3000
|
||||
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x3000
|
||||
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x3000
|
||||
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x3000
|
||||
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x3000
|
||||
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x3000
|
||||
>;
|
||||
};
|
||||
};
|
779
arch/arm/boot/dts/imx6q-bosch-acc.dts
Normal file
779
arch/arm/boot/dts/imx6q-bosch-acc.dts
Normal file
@ -0,0 +1,779 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Support for the i.MX6-based Bosch ACC board.
|
||||
*
|
||||
* Copyright (C) 2016 Garz & Fricke GmbH
|
||||
* Copyright (C) 2018 DENX Software Engineering GmbH, Heiko Schocher <hs@denx.de>
|
||||
* Copyright (C) 2018 DENX Software Engineering GmbH, Niel Fourie <lusus@denx.de>
|
||||
* Copyright (C) 2019-2021 Bosch Thermotechnik GmbH, Matthias Winker <matthias.winker@bosch.com>
|
||||
* Copyright (C) 2022 DENX Software Engineering GmbH, Philip Oberfichtner <pro@denx.de>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include "imx6q.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Bosch ACC";
|
||||
compatible = "bosch,imx6q-acc", "fsl,imx6q";
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c2;
|
||||
i2c2 = &i2c3;
|
||||
mmc0 = &usdhc4;
|
||||
mmc1 = &usdhc2;
|
||||
serial0 = &uart2;
|
||||
serial1 = &uart1;
|
||||
};
|
||||
|
||||
memory@10000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x10000000 0x40000000>;
|
||||
};
|
||||
|
||||
backlight_lvds: backlight-lvds {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm1 0 200000>;
|
||||
brightness-levels = <0 61 499 1706 4079 8022 13938 22237 33328 47623 65535>;
|
||||
num-interpolated-steps = <10>;
|
||||
default-brightness-level = <60>;
|
||||
power-supply = <®_lcd>;
|
||||
};
|
||||
|
||||
panel {
|
||||
compatible = "dataimage,fg1001l0dsswmg01";
|
||||
backlight = <&backlight_lvds>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
refclk: refclk {
|
||||
compatible = "fixed-factor-clock";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&clks IMX6QDL_CLK_CKO2>;
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clock-output-names = "12mhz_refclk";
|
||||
assigned-clocks = <&clks IMX6QDL_CLK_CKO>,
|
||||
<&clks IMX6QDL_CLK_CKO2>,
|
||||
<&clks IMX6QDL_CLK_CKO2_SEL>;
|
||||
assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>,
|
||||
<&clks IMX6QDL_CLK_CKO2_PODF>,
|
||||
<&clks IMX6QDL_CLK_OSC>;
|
||||
assigned-clock-rates = <0>, <12000000>, <0>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
cpu0: cpu@0 {
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
1200000 1275000
|
||||
996000 1225000
|
||||
852000 1225000
|
||||
792000 1150000
|
||||
396000 950000
|
||||
>;
|
||||
fsl,soc-operating-points = <
|
||||
/* ARM kHz SOC-PU uV */
|
||||
1200000 1225000
|
||||
996000 1175000
|
||||
852000 1175000
|
||||
792000 1150000
|
||||
396000 1150000
|
||||
>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
1200000 1275000
|
||||
996000 1225000
|
||||
852000 1225000
|
||||
792000 1150000
|
||||
396000 950000
|
||||
>;
|
||||
fsl,soc-operating-points = <
|
||||
/* ARM kHz SOC-PU uV */
|
||||
1200000 1225000
|
||||
996000 1175000
|
||||
852000 1175000
|
||||
792000 1150000
|
||||
396000 1150000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm-leds {
|
||||
compatible = "pwm-leds";
|
||||
|
||||
led_red: led-0 {
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
max-brightness = <248>;
|
||||
default-state = "off";
|
||||
pwms = <&pwm2 0 500000>;
|
||||
};
|
||||
|
||||
led_white: led-1 {
|
||||
color = <LED_COLOR_ID_WHITE>;
|
||||
max-brightness = <248>;
|
||||
default-state = "off";
|
||||
pwms = <&pwm3 0 500000>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_reset_gpio_led>;
|
||||
|
||||
led-2 {
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
reg_5p0: regulator-5p0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "5p0";
|
||||
};
|
||||
|
||||
reg_vin: regulator-vin {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VIN";
|
||||
regulator-min-microvolt = <4500000>;
|
||||
regulator-max-microvolt = <4500000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_5p0>;
|
||||
};
|
||||
|
||||
reg_usb_otg_vbus: regulator-usb-otg-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_otg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
reg_usb_h1_vbus: regulator-usb-h1-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_h1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_5p0>;
|
||||
};
|
||||
|
||||
reg_usb_h2_vbus: regulator-usb-h2-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_h2_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <®_5p0> ;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_vsnvs: regulator-vsnvs {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VSNVS_3V0";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_5p0>;
|
||||
};
|
||||
|
||||
reg_lcd: regulator-lcd {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "LCD0 POWER";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcd_enable>;
|
||||
gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_dac: regulator-dac {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vref_dac";
|
||||
regulator-min-microvolt = <20000>;
|
||||
regulator-max-microvolt = <20000>;
|
||||
vin-supply = <®_5p0> ;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_sw4: regulator-sw4 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "SW4_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_5p0>;
|
||||
};
|
||||
|
||||
reg_sys: regulator-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "SYS_4V2";
|
||||
regulator-min-microvolt = <4200000>;
|
||||
regulator-max-microvolt = <4200000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_5p0>;
|
||||
};
|
||||
};
|
||||
|
||||
®_arm {
|
||||
vin-supply = <&sw2_reg>;
|
||||
};
|
||||
|
||||
®_soc {
|
||||
vin-supply = <&sw1c_reg>;
|
||||
};
|
||||
|
||||
®_vdd1p1 {
|
||||
vin-supply = <®_vsnvs>;
|
||||
};
|
||||
|
||||
®_vdd2p5 {
|
||||
vin-supply = <®_vsnvs>;
|
||||
};
|
||||
|
||||
®_vdd3p0 {
|
||||
vin-supply = <®_vsnvs>;
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet>;
|
||||
clocks = <&clks IMX6QDL_CLK_ENET>,
|
||||
<&clks IMX6QDL_CLK_ENET>,
|
||||
<&clks IMX6QDL_CLK_ENET>,
|
||||
<&clks IMX6QDL_CLK_ENET_REF>;
|
||||
clock-names = "ipg", "ahb", "ptp", "enet_out";
|
||||
phy-mode = "rmii";
|
||||
phy-supply = <®_sw4>;
|
||||
phy-handle = <ðphy>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
|
||||
smsc,disable-energy-detect;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpu_vg {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&gpu_2d {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
pmic: pmic@8 {
|
||||
compatible = "fsl,pfuze100";
|
||||
reg = <0x08>;
|
||||
|
||||
regulators {
|
||||
sw1c_reg: sw1c {
|
||||
regulator-name = "VDD_SOC (sw1abc)";
|
||||
regulator-min-microvolt = <1275000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <6250>;
|
||||
};
|
||||
|
||||
sw2_reg: sw2 {
|
||||
regulator-name = "VDD_ARM (sw2)";
|
||||
regulator-min-microvolt = <1050000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <6250>;
|
||||
};
|
||||
|
||||
sw3a_reg: sw3a {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "DDR_1V5a";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
|
||||
};
|
||||
|
||||
sw3b_reg: sw3b {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "DDR_1V5b";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
|
||||
};
|
||||
|
||||
sw4_reg: sw4 {
|
||||
regulator-name = "AUX 3V15 (sw4)";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
swbst_reg: swbst {
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5150000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
snvs_reg: vsnvs {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vref_reg: vrefddr {
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen1_reg: vgen1 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen2_reg: vgen2 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen3_reg: vgen3 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen4_reg: vgen4 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vgen5_reg: vgen5 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vgen6_reg: vgen6 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lm75: sensor@49 {
|
||||
compatible = "national,lm75b";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lm75>;
|
||||
reg = <0x49>;
|
||||
};
|
||||
|
||||
eeprom: eeprom@50 {
|
||||
compatible = "atmel,24c32";
|
||||
reg = <0x50>;
|
||||
pagesize = <32>;
|
||||
};
|
||||
|
||||
rtc: rtc@51 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_rtc>;
|
||||
compatible = "nxp,pcf8563";
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
|
||||
eeprom_ext: eeprom@50 {
|
||||
compatible = "atmel,24c32";
|
||||
reg = <0x50>;
|
||||
pagesize = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
usb3503: usb@8 {
|
||||
compatible = "smsc,usb3503";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb3503>;
|
||||
reg = <0x08>;
|
||||
connect-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* Old: 0, SS: HIGH */
|
||||
intn-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; /* Old: 1, SS: HIGH */
|
||||
reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* Old: 0, SS: HIGH */
|
||||
initial-mode = <1>;
|
||||
clocks = <&refclk>;
|
||||
clock-names = "refclk";
|
||||
refclk-frequency = <12000000>;
|
||||
};
|
||||
|
||||
exc3000: touchscreen@2a {
|
||||
compatible = "eeti,exc3000";
|
||||
reg = <0x2a>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ctouch>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
|
||||
touchscreen-size-x = <4096>;
|
||||
touchscreen-size-y = <4096>;
|
||||
};
|
||||
|
||||
vcnl4035: light-sensor@60 {
|
||||
compatible = "vishay,vcnl4035";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_proximity>;
|
||||
reg = <0x60>;
|
||||
};
|
||||
};
|
||||
|
||||
&ldb {
|
||||
status = "okay";
|
||||
|
||||
lvds0: lvds-channel@0 {
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <24>;
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
#pwm-cells = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
#pwm-cells = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
#pwm-cells = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm4 {
|
||||
#pwm-cells = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
rts-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
|
||||
linux,rs485-enabled-at-boot-time;
|
||||
rs485-rx-during-tx;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
vbus-supply = <®_usb_h1_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh2 {
|
||||
pinctrl-names = "idle", "active";
|
||||
pinctrl-0 = <&pinctrl_usbh2_idle>;
|
||||
pinctrl-1 = <&pinctrl_usbh2_active>;
|
||||
vbus-supply = <®_usb_h2_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg>;
|
||||
vbus-supply = <®_usb_otg_vbus>;
|
||||
disable-over-current;
|
||||
dr_mode = "otg";
|
||||
srp-disable;
|
||||
hnp-disable;
|
||||
adp-disable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphynop1 {
|
||||
clocks = <&clks IMX6QDL_CLK_USBPHY1>;
|
||||
clock-names = "main_clk";
|
||||
vcc-supply = <®_usb_h1_vbus>;
|
||||
};
|
||||
|
||||
&usbphynop2 {
|
||||
vcc-supply = <®_usb_h2_vbus>;
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
|
||||
no-1-8-v;
|
||||
keep-power-in-suspend;
|
||||
wakeup-source;
|
||||
voltage-ranges = <3300 3300>;
|
||||
vmmc-supply = <®_sw4>;
|
||||
fsl,wp-controller;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc4>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
no-1-8-v;
|
||||
keep-power-in-suspend;
|
||||
voltage-ranges = <3300 3300>;
|
||||
vmmc-supply = <®_sw4>;
|
||||
fsl,wp-controller;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog1>;
|
||||
fsl,ext-reset-output;
|
||||
timeout-sec = <10>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
|
||||
MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 /* FEC INT */
|
||||
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001b098
|
||||
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
|
||||
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001b098
|
||||
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001b098
|
||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reset_gpio_led: reset-gpio-led-grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
|
||||
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b810
|
||||
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b810
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lcd_enable: lcdenablegrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* lcd enable */
|
||||
MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0 /* sel6_8 */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lm75: lm75grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_proximity: proximitygrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm1: pwm1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x0001b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm2: pwm2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x0001b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm3: pwm3grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x0001b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm4: pwm4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x0001b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_rtc: rtc-grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 /* RTC INT */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ctouch: ctouch-grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* CTOUCH_INT */
|
||||
MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x0001b0b0 /* CTOUCH_RESET */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x0001b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh2_idle: usbh2-idle-grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018
|
||||
MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00013018
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh2_active: usbh2-active-grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018
|
||||
MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00017018
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usb3503: usb3503-grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x00000018
|
||||
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* USB INT */
|
||||
MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0001b0b0 /* USB Reset */
|
||||
MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 /* USB Connect */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017069
|
||||
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00010038
|
||||
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017069
|
||||
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017069
|
||||
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017069
|
||||
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017069
|
||||
MX6QDL_PAD_GPIO_4__SD2_CD_B 0x0001b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc4: usdhc4grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x00017059
|
||||
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x00010059
|
||||
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x00017059
|
||||
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x00017059
|
||||
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x00017059
|
||||
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x00017059
|
||||
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x00017059
|
||||
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x00017059
|
||||
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x00017059
|
||||
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x00017059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog1: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0
|
||||
>;
|
||||
};
|
||||
};
|
128
arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi
Normal file
128
arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi
Normal file
@ -0,0 +1,128 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright (c) 2021 Protonic Holland
|
||||
*/
|
||||
|
||||
/ {
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpiokeys>;
|
||||
autorepeat;
|
||||
|
||||
power {
|
||||
label = "Power Button";
|
||||
gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_POWER>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
panel {
|
||||
compatible = "kyo,tcg121xglp";
|
||||
backlight = <&backlight_lcd>;
|
||||
power-supply = <®_3v3>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <&rgmii_phy>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* Microchip KSZ9031RNX PHY */
|
||||
rgmii_phy: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <300>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
gpio-line-names =
|
||||
"CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR",
|
||||
"CAM2_MIRROR", "", "", "SMBALERT",
|
||||
"DEBUG_0", "DEBUG_1", "", "", "", "", "", "",
|
||||
"SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK",
|
||||
"SD1_DATA3", "ETH_MDIO", "",
|
||||
"", "ETH_RESET", "", "", "ETH_INT", "", "", "ETH_MDC";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
gpio-line-names =
|
||||
"", "", "", "", "", "", "UART4_TXD", "UART4_RXD",
|
||||
"UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR",
|
||||
"CAN2_SR", "CAN2_TX", "CAN2_RX",
|
||||
"", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL",
|
||||
"HITCH_IN_OUT",
|
||||
"LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "",
|
||||
"ISB_LED";
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
gpio-line-names =
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET",
|
||||
"I2S_BITCLK", "I2S_DOUT",
|
||||
"I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX",
|
||||
"YACO_AUX_TX", "ITU656_D0", "ITU656_D1";
|
||||
};
|
||||
|
||||
&gpio6 {
|
||||
gpio-line-names =
|
||||
"ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5",
|
||||
"ITU656_D6", "ITU656_D7", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2",
|
||||
"RGMII_TD3",
|
||||
"RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1",
|
||||
"RGMII_RD2", "RGMII_RD3", "", "";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_enet: enetgrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
|
||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
|
||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
|
||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030
|
||||
/* Phy reset */
|
||||
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpiokeys: gpiokeygrp {
|
||||
fsl,pins = <
|
||||
/* nON_SWITCH */
|
||||
MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0
|
||||
>;
|
||||
};
|
||||
};
|
211
arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi
Normal file
211
arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi
Normal file
@ -0,0 +1,211 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
|
||||
/*
|
||||
* Copyright 2018-2022 TQ-Systems GmbH
|
||||
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
|
||||
*/
|
||||
|
||||
/*
|
||||
* Common for
|
||||
* - TQMa6ULx
|
||||
* - TQMa6ULxL
|
||||
* - TQMa6ULLx
|
||||
* - TQMa6ULLxL
|
||||
*/
|
||||
|
||||
/ {
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c4>;
|
||||
pinctrl-1 = <&pinctrl_i2c4_recovery>;
|
||||
scl-gpios = <&gpio1 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
status = "okay";
|
||||
|
||||
pfuze3000: pmic@8 {
|
||||
compatible = "fsl,pfuze3000";
|
||||
reg = <0x08>;
|
||||
|
||||
regulators {
|
||||
reg_sw1a: sw1a {
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-ramp-delay = <6250>;
|
||||
/* not used */
|
||||
};
|
||||
|
||||
reg_sw1b_core: sw1b {
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1475000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <6250>;
|
||||
};
|
||||
|
||||
reg_sw2: sw2 {
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
reg_sw3_ddr: sw3 {
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1650000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_swbst: swbst {
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5150000>;
|
||||
/* not used */
|
||||
};
|
||||
|
||||
reg_snvs_3v0: vsnvs {
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_vrefddr: vrefddr {
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_vccsd: vccsd {
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
reg_v33_3v3: v33 {
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_vldo1_3v3: vldo1 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
/* not used */
|
||||
};
|
||||
|
||||
reg_vldo2: vldo2 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
/* not used */
|
||||
};
|
||||
|
||||
reg_vldo3: vldo3 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
/* not used */
|
||||
};
|
||||
|
||||
reg_vldo4: vldo4 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
jc42_1a: eeprom-temperature-sensor@1a {
|
||||
compatible = "nxp,se97", "jedec,jc-42.4-temp";
|
||||
reg = <0x1a>;
|
||||
};
|
||||
|
||||
m24c64_50: eeprom@50 {
|
||||
compatible = "atmel,24c64";
|
||||
reg = <0x50>;
|
||||
pagesize = <32>;
|
||||
};
|
||||
|
||||
m24c02_52: eeprom@52 {
|
||||
compatible = "nxp,se97b", "atmel,24c02";
|
||||
reg = <0x52>;
|
||||
pagesize = <16>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
rtc0: rtc@68 {
|
||||
compatible = "dallas,ds1339";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pmic>;
|
||||
|
||||
/*
|
||||
* PMIC & temperature sensor IRQ
|
||||
* Both do currently not use IRQ
|
||||
* potentially dangerous if used on baseboard
|
||||
*/
|
||||
pmic-int-hog {
|
||||
gpio-hog;
|
||||
gpios = <24 0>;
|
||||
input;
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_qspi>;
|
||||
status = "okay";
|
||||
|
||||
flash0: flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <33000000>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <1>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz" , "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
|
||||
|
||||
bus-width = <8>;
|
||||
disable-wp;
|
||||
non-removable;
|
||||
no-sdio;
|
||||
no-sd;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_i2c4: i2c4grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001b8b0
|
||||
MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001b8b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c4_recovery: i2c4recoverygrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x4001b8b0
|
||||
MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x4001b8b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmic {
|
||||
fsl,pins = <
|
||||
/* PMIC irq */
|
||||
MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x1b099
|
||||
>;
|
||||
};
|
||||
};
|
55
arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts
Normal file
55
arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts
Normal file
@ -0,0 +1,55 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
|
||||
/*
|
||||
* Copyright 2018-2022 TQ-Systems GmbH
|
||||
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6ul-tqma6ul1.dtsi"
|
||||
#include "mba6ulx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TQ-Systems TQMa6UL1 SoM on MBa6ULx board";
|
||||
compatible = "tq,imx6ul-tqma6ul1-mba6ulx", "tq,imx6ul-tqma6ul1", "fsl,imx6ul";
|
||||
};
|
||||
|
||||
/*
|
||||
* Note: can2 and fec2 are enabled on mba6ulx level (for i.MX6ULG2 usage)
|
||||
* and need to be disabled here again
|
||||
*/
|
||||
&can2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_mdc>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
max-speed = <100>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec2 {
|
||||
/delete-property/ phy-handle;
|
||||
/delete-node/ mdio;
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_enet1_mdc: enet1mdcgrp {
|
||||
fsl,pins = <
|
||||
/* mdio */
|
||||
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
|
||||
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
|
||||
>;
|
||||
};
|
||||
};
|
37
arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi
Normal file
37
arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi
Normal file
@ -0,0 +1,37 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
|
||||
/*
|
||||
* Copyright 2018-2022 TQ-Systems GmbH
|
||||
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
|
||||
*/
|
||||
|
||||
#include "imx6ul-tqma6ul2.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TQ-Systems TQMa6UL1 SoM";
|
||||
compatible = "tq,imx6ul-tqma6ul1", "fsl,imx6ul";
|
||||
};
|
||||
|
||||
/*
|
||||
* There are no module specific differences compared to TQMa6UL2,
|
||||
* only external interfaces differ
|
||||
*/
|
||||
|
||||
/*
|
||||
* Devices not available on i.MX6ULG1 and should not be enabled on
|
||||
* mainboard level (again)
|
||||
*/
|
||||
&can2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&csi {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&fec2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&lcdif {
|
||||
status = "disabled";
|
||||
};
|
15
arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts
Normal file
15
arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts
Normal file
@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
|
||||
/*
|
||||
* Copyright 2018-2022 TQ-Systems GmbH
|
||||
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6ul-tqma6ul2.dtsi"
|
||||
#include "mba6ulx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TQ-Systems TQMa6ULx SoM on MBa6ULx board";
|
||||
compatible = "tq,imx6ul-tqma6ul2-mba6ulx", "tq,imx6ul-tqma6ul2", "fsl,imx6ul";
|
||||
};
|
71
arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi
Normal file
71
arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi
Normal file
@ -0,0 +1,71 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
|
||||
/*
|
||||
* Copyright 2018-2022 TQ-Systems GmbH
|
||||
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
|
||||
*/
|
||||
|
||||
#include "imx6ul.dtsi"
|
||||
#include "imx6ul-tqma6ul-common.dtsi"
|
||||
#include "imx6ul-tqma6ulx-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TQ-Systems TQMa6UL2 SoM";
|
||||
compatible = "tq,imx6ul-tqma6ul2", "fsl,imx6ul";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
fsl,tuning-step = <6>;
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017051
|
||||
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017051
|
||||
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017051
|
||||
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017051
|
||||
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017051
|
||||
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017051
|
||||
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017051
|
||||
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017051
|
||||
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017051
|
||||
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051
|
||||
/* rst */
|
||||
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170e1
|
||||
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
|
||||
/* rst */
|
||||
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1
|
||||
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170e1
|
||||
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170e1
|
||||
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170e1
|
||||
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170e1
|
||||
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170e1
|
||||
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170e1
|
||||
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170e1
|
||||
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170e1
|
||||
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170e1
|
||||
/* rst */
|
||||
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
|
||||
>;
|
||||
};
|
||||
};
|
15
arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts
Normal file
15
arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts
Normal file
@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
|
||||
/*
|
||||
* Copyright 2018-2022 TQ Systems GmbH
|
||||
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6ul-tqma6ul2l.dtsi"
|
||||
#include "mba6ulx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TQ Systems TQMa6UL2L SoM on MBa6ULx board";
|
||||
compatible = "tq,imx6ul-tqma6ul2l-mba6ulx", "tq,imx6ul-tqma6ul2l", "fsl,imx6ul";
|
||||
};
|
71
arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi
Normal file
71
arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi
Normal file
@ -0,0 +1,71 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
|
||||
/*
|
||||
* Copyright 2018-2022 TQ-Systems GmbH
|
||||
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
|
||||
*/
|
||||
|
||||
#include "imx6ul.dtsi"
|
||||
#include "imx6ul-tqma6ul-common.dtsi"
|
||||
#include "imx6ul-tqma6ulxl-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TQ-Systems TQMa6UL2L SoM";
|
||||
compatible = "tq,imx6ul-tqma6ul2l", "fsl,imx6ul";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
fsl,tuning-step = <6>;
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017051
|
||||
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017051
|
||||
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017051
|
||||
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017051
|
||||
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017051
|
||||
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017051
|
||||
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017051
|
||||
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017051
|
||||
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017051
|
||||
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051
|
||||
/* rst */
|
||||
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170e1
|
||||
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
|
||||
/* rst */
|
||||
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f9
|
||||
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
|
||||
/* rst */
|
||||
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
|
||||
>;
|
||||
};
|
||||
};
|
43
arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi
Normal file
43
arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi
Normal file
@ -0,0 +1,43 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
|
||||
/*
|
||||
* Copyright 2018-2022 TQ-Systems GmbH
|
||||
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
|
||||
*/
|
||||
|
||||
/*
|
||||
* Common for
|
||||
* - TQMa6ULx
|
||||
* - TQMa6ULLx
|
||||
*/
|
||||
|
||||
&m24c64_50 {
|
||||
vcc-supply = <®_sw2>;
|
||||
};
|
||||
|
||||
&m24c02_52 {
|
||||
vcc-supply = <®_sw2>;
|
||||
};
|
||||
|
||||
®_sw2 {
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
&usdhc2 {
|
||||
vmmc-supply = <®_sw2>;
|
||||
vqmmc-supply = <®_vldo4>;
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_qspi: qspigrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70b9
|
||||
MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70b9
|
||||
MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70b9
|
||||
MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70b9
|
||||
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70b9
|
||||
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
|
||||
>;
|
||||
};
|
||||
};
|
48
arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi
Normal file
48
arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi
Normal file
@ -0,0 +1,48 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
|
||||
/*
|
||||
* Copyright 2018-2022 TQ-Systems GmbH
|
||||
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
|
||||
*/
|
||||
|
||||
/*
|
||||
* Common for
|
||||
* - TQMa6ULxL
|
||||
* - TQMa6ULLxL
|
||||
*/
|
||||
|
||||
/ {
|
||||
reg_vin: reg-vin {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VIN";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&m24c64_50 {
|
||||
vcc-supply = <®_vin>;
|
||||
};
|
||||
|
||||
&m24c02_52 {
|
||||
vcc-supply = <®_vin>;
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
&usdhc2 {
|
||||
vmmc-supply = <®_vin>;
|
||||
vqmmc-supply = <®_vldo4>;
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_qspi: qspigrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a9
|
||||
MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a9
|
||||
MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a9
|
||||
MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a9
|
||||
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a9
|
||||
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
|
||||
>;
|
||||
};
|
||||
};
|
20
arch/arm/boot/dts/imx6ull-colibri-aster.dts
Normal file
20
arch/arm/boot/dts/imx6ull-colibri-aster.dts
Normal file
@ -0,0 +1,20 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2017-2022 Toradex
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6ull-colibri-nonwifi.dtsi"
|
||||
#include "imx6ull-colibri-aster.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Aster";
|
||||
compatible = "toradex,colibri-imx6ull-aster",
|
||||
"toradex,colibri-imx6ull",
|
||||
"fsl,imx6ull";
|
||||
};
|
||||
|
||||
&atmel_mxt_ts {
|
||||
status = "okay";
|
||||
};
|
145
arch/arm/boot/dts/imx6ull-colibri-aster.dtsi
Normal file
145
arch/arm/boot/dts/imx6ull-colibri-aster.dtsi
Normal file
@ -0,0 +1,145 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2017-2022 Toradex
|
||||
*/
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_snvs_gpiokeys>;
|
||||
|
||||
power {
|
||||
label = "Wake-Up";
|
||||
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <KEY_WAKEUP>;
|
||||
debounce-interval = <10>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
reg_3v3: regulator-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
reg_5v0: regulator-5v0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "5V";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
reg_usbh_vbus: regulator-usbh-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbh_reg>;
|
||||
regulator-name = "VCC_USB[1-4]";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
|
||||
vin-supply = <®_5v0>;
|
||||
};
|
||||
};
|
||||
|
||||
&adc1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
status = "okay";
|
||||
|
||||
num-cs = <2>;
|
||||
cs-gpios = <
|
||||
&gpio3 26 GPIO_ACTIVE_HIGH /* SODIMM 86 LCD_DATA21 */
|
||||
&gpio4 28 GPIO_ACTIVE_HIGH /* SODIMM 65 CSI_DATA07 */
|
||||
>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Following SODIMM Pins should not be accessed as GPIO on Aster board:
|
||||
* 134 - AIN5_SCL (no connection)
|
||||
* 127 - Voltage Level Translator OE# signal (IC11 and IC12)
|
||||
*
|
||||
* To configure GPIO to LED5, please disable FEC2 and uncomment the following:
|
||||
* &iomuxc {
|
||||
* pinctrl-names = "default";
|
||||
* pinctrl-0 = <
|
||||
* &pinctrl_gpio1
|
||||
* &pinctrl_gpio2
|
||||
* &pinctrl_gpio3
|
||||
* &pinctrl_gpio4
|
||||
* &pinctrl_gpio6 - for non-WiFi modules only
|
||||
* &pinctrl_gpio7
|
||||
* &pinctrl_gpio_aster
|
||||
* >;
|
||||
*
|
||||
* pinctrl_gpio_aster: gpio-aster {
|
||||
* fsl,pins = <
|
||||
* MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x1b0b0
|
||||
* >;
|
||||
* };
|
||||
* };
|
||||
*/
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
m41t0m6: rtc@68 {
|
||||
compatible = "st,m41t0";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PWM <A> */
|
||||
&pwm4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* PWM <B> */
|
||||
&pwm5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* PWM <C> */
|
||||
&pwm6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* PWM <D> */
|
||||
&pwm7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg1 {
|
||||
vbus-supply = <®_usbh_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg2 {
|
||||
vbus-supply = <®_usbh_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
vmmc-supply = <®_3v3>;
|
||||
status = "okay";
|
||||
};
|
17
arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts
Normal file
17
arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts
Normal file
@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2022 Toradex
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6ull-colibri-emmc-nonwifi.dtsi"
|
||||
#include "imx6ull-colibri-aster.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Aster";
|
||||
compatible = "toradex,colibri-imx6ull-emmc-aster",
|
||||
"toradex,colibri-imx6ull-emmc",
|
||||
"toradex,colibri-imx6ull",
|
||||
"fsl,imx6ull";
|
||||
};
|
17
arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts
Normal file
17
arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts
Normal file
@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2022 Toradex
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6ull-colibri-emmc-nonwifi.dtsi"
|
||||
#include "imx6ull-colibri-iris-v2.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Colibri iMX6ULL 1G (eMMC) on Colibri Iris V2";
|
||||
compatible = "toradex,colibri-imx6ull-iris-v2",
|
||||
"toradex,colibri-imx6ull-emmc",
|
||||
"toradex,colibri-imx6ull",
|
||||
"fsl,imx6ull";
|
||||
};
|
17
arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts
Normal file
17
arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts
Normal file
@ -0,0 +1,17 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2022 Toradex
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6ull-colibri-emmc-nonwifi.dtsi"
|
||||
#include "imx6ull-colibri-iris.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Iris";
|
||||
compatible = "toradex,colibri-imx6ull-emmc-iris",
|
||||
"toradex,colibri-imx6ull-emmc",
|
||||
"toradex,colibri-imx6ull",
|
||||
"fsl,imx6ull";
|
||||
};
|
65
arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts
Normal file
65
arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts
Normal file
@ -0,0 +1,65 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2018-2022 Toradex
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6ull-colibri-nonwifi.dtsi"
|
||||
#include "imx6ull-colibri-iris-v2.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Colibri iMX6ULL 256M/512B on Colibri Iris V2";
|
||||
compatible = "toradex,colibri-imx6ull-iris-v2",
|
||||
"toradex,colibri-imx6ull",
|
||||
"fsl,imx6ull";
|
||||
};
|
||||
|
||||
&atmel_mxt_ts {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
/* This turns the LVDS transceiver on */
|
||||
lvds-power-on {
|
||||
gpio-hog;
|
||||
gpios = <14 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */
|
||||
line-name = "LVDS_POWER_ON";
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
/*
|
||||
* This switches the LVDS transceiver to the single-channel
|
||||
* output mode.
|
||||
*/
|
||||
lvds-ch-mode {
|
||||
gpio-hog;
|
||||
gpios = <0 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */
|
||||
line-name = "LVDS_CH_MODE";
|
||||
output-high;
|
||||
};
|
||||
|
||||
/*
|
||||
* This switches the LVDS transceiver to the 24-bit RGB mode.
|
||||
*/
|
||||
lvds-rgb-mode {
|
||||
gpio-hog;
|
||||
gpios = <1 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */
|
||||
line-name = "LVDS_RGB_MODE";
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
/*
|
||||
* This switches the LVDS transceiver to VESA color mapping mode.
|
||||
*/
|
||||
lvds-color-map {
|
||||
gpio-hog;
|
||||
gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */
|
||||
line-name = "LVDS_COLOR_MAP";
|
||||
output-low;
|
||||
};
|
||||
};
|
27
arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi
Normal file
27
arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi
Normal file
@ -0,0 +1,27 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2018-2022 Toradex
|
||||
*/
|
||||
|
||||
#include "imx6ull-colibri-iris.dtsi"
|
||||
|
||||
/ {
|
||||
reg_3v3_vmmc: regulator-3v3-vmmc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3v3_vmmc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <100>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
&usdhc1 {
|
||||
cap-power-off-card;
|
||||
vmmc-supply = <®_3v3_vmmc>;
|
||||
/delete-property/ keep-power-in-suspend;
|
||||
/delete-property/ no-1-8-v;
|
||||
status = "okay";
|
||||
};
|
20
arch/arm/boot/dts/imx6ull-colibri-iris.dts
Normal file
20
arch/arm/boot/dts/imx6ull-colibri-iris.dts
Normal file
@ -0,0 +1,20 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2018-2022 Toradex
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6ull-colibri-nonwifi.dtsi"
|
||||
#include "imx6ull-colibri-iris.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Iris";
|
||||
compatible = "toradex,colibri-imx6ull-iris",
|
||||
"toradex,colibri-imx6ull",
|
||||
"fsl,imx6ull";
|
||||
};
|
||||
|
||||
&atmel_mxt_ts {
|
||||
status = "okay";
|
||||
};
|
132
arch/arm/boot/dts/imx6ull-colibri-iris.dtsi
Normal file
132
arch/arm/boot/dts/imx6ull-colibri-iris.dtsi
Normal file
@ -0,0 +1,132 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2018-2022 Toradex
|
||||
*/
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_snvs_gpiokeys>;
|
||||
|
||||
power {
|
||||
label = "Wake-Up";
|
||||
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <KEY_WAKEUP>;
|
||||
debounce-interval = <10>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
reg_3v3: regulator-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
reg_5v0: regulator-5v0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "5V";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
reg_usbh_vbus: regulator-usbh-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbh_reg>;
|
||||
regulator-name = "VCC_USB[1-4]";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
|
||||
vin-supply = <®_5v0>;
|
||||
};
|
||||
};
|
||||
|
||||
&adc1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
/*
|
||||
* uart25_tx_on turns the UART transceiver on. If one wants to turn the
|
||||
* transceiver off, that property has to be deleted and the gpio handled
|
||||
* in userspace.
|
||||
* The same applies to uart1_tx_on.
|
||||
*/
|
||||
uart25_tx_on {
|
||||
gpio-hog;
|
||||
gpios = <15 0>;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
uart1_tx_on {
|
||||
gpio-hog;
|
||||
gpios = <7 0>;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
/* M41T0M6 real time clock on carrier board */
|
||||
m41t0m6: rtc@68 {
|
||||
compatible = "st,m41t0";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PWM <A> */
|
||||
&pwm4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* PWM <B> */
|
||||
&pwm5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* PWM <C> */
|
||||
&pwm6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* PWM <D> */
|
||||
&pwm7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg1 {
|
||||
vbus-supply = <®_usbh_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg2 {
|
||||
vbus-supply = <®_usbh_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
vmmc-supply = <®_3v3>;
|
||||
status = "okay";
|
||||
};
|
20
arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts
Normal file
20
arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts
Normal file
@ -0,0 +1,20 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2017-2022 Toradex
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6ull-colibri-wifi.dtsi"
|
||||
#include "imx6ull-colibri-aster.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Colibri iMX6ULL 512MB on Colibri Aster";
|
||||
compatible = "toradex,colibri-imx6ull-wifi-aster",
|
||||
"toradex,colibri-imx6ull",
|
||||
"fsl,imx6ull";
|
||||
};
|
||||
|
||||
&atmel_mxt_ts {
|
||||
status = "okay";
|
||||
};
|
65
arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts
Normal file
65
arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts
Normal file
@ -0,0 +1,65 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2018-2022 Toradex
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6ull-colibri-wifi.dtsi"
|
||||
#include "imx6ull-colibri-iris-v2.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris V2";
|
||||
compatible = "toradex,colibri-imx6ull-wifi-iris-v2",
|
||||
"toradex,colibri-imx6ull",
|
||||
"fsl,imx6ull";
|
||||
};
|
||||
|
||||
&atmel_mxt_ts {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
/* This turns the LVDS transceiver on */
|
||||
lvds-power-on {
|
||||
gpio-hog;
|
||||
gpios = <14 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */
|
||||
line-name = "LVDS_POWER_ON";
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
/*
|
||||
* This switches the LVDS transceiver to the single-channel
|
||||
* output mode.
|
||||
*/
|
||||
lvds-ch-mode {
|
||||
gpio-hog;
|
||||
gpios = <0 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */
|
||||
line-name = "LVDS_CH_MODE";
|
||||
output-high;
|
||||
};
|
||||
|
||||
/*
|
||||
* This switches the LVDS transceiver to the 24-bit RGB mode.
|
||||
*/
|
||||
lvds-rgb-mode {
|
||||
gpio-hog;
|
||||
gpios = <1 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */
|
||||
line-name = "LVDS_RGB_MODE";
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
/*
|
||||
* This switches the LVDS transceiver to VESA color mapping mode.
|
||||
*/
|
||||
lvds-color-map {
|
||||
gpio-hog;
|
||||
gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */
|
||||
line-name = "LVDS_COLOR_MAP";
|
||||
output-low;
|
||||
};
|
||||
};
|
20
arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts
Normal file
20
arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts
Normal file
@ -0,0 +1,20 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2018-2022 Toradex
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6ull-colibri-wifi.dtsi"
|
||||
#include "imx6ull-colibri-iris.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris";
|
||||
compatible = "toradex,colibri-imx6ull-wifi-iris",
|
||||
"toradex,colibri-imx6ull",
|
||||
"fsl,imx6ull";
|
||||
};
|
||||
|
||||
&atmel_mxt_ts {
|
||||
status = "okay";
|
||||
};
|
20
arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts
Normal file
20
arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts
Normal file
@ -0,0 +1,20 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2021 PHYTEC Messtechnik GmbH
|
||||
* Author: Alexander Bauer <a.bauer@phytec.de>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6ull-phytec-tauri.dtsi"
|
||||
|
||||
/ {
|
||||
model = "PHYTEC phyGate-Tauri i.MX6 UltraLite";
|
||||
compatible = "phytec,imx6ull-phygate-tauri",
|
||||
"phytec,imx6ull-phygate-tauri-emmc",
|
||||
"phytec,imx6ull-pcl063", "fsl,imx6ull";
|
||||
};
|
||||
|
||||
/* EMMC-Version */
|
||||
&usdhc2 {
|
||||
status = "okay";
|
||||
};
|
20
arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts
Normal file
20
arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts
Normal file
@ -0,0 +1,20 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2021 PHYTEC Messtechnik GmbH
|
||||
* Author: Alexander Bauer <a.bauer@phytec.de>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6ull-phytec-tauri.dtsi"
|
||||
|
||||
/ {
|
||||
model = "PHYTEC phyGate-Tauri i.MX6 UltraLite";
|
||||
compatible = "phytec,imx6ull-phygate-tauri",
|
||||
"phytec,imx6ull-phygate-tauri-nand",
|
||||
"phytec,imx6ull-pcl063", "fsl,imx6ull";
|
||||
};
|
||||
|
||||
/* NAND-Version */
|
||||
&gpmi {
|
||||
status = "okay";
|
||||
};
|
588
arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi
Normal file
588
arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi
Normal file
@ -0,0 +1,588 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2021 PHYTEC Messtechnik GmbH
|
||||
* Author: Alexander Bauer <a.bauer@phytec.de>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx6ull.dtsi"
|
||||
#include "imx6ull-phytec-phycore-som.dtsi"
|
||||
|
||||
/ {
|
||||
|
||||
model = "PHYTEC phyGate-Tauri i.MX6 UltraLite";
|
||||
compatible = "phytec,imx6ull-phygate-tauri",
|
||||
"phytec,imx6ull-pcl063", "fsl,imx6ull";
|
||||
|
||||
aliases {
|
||||
rtc0 = &i2c_rtc;
|
||||
rtc1 = &snvs_rtc;
|
||||
};
|
||||
|
||||
gpio_keys: gpio-keys {
|
||||
compatible = "gpio-key";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_keys>;
|
||||
|
||||
key {
|
||||
label = "KEY-A";
|
||||
gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_A>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
reg_adc1_vref_3v3: regulator-vref-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vref-3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
reg_s25fl064_hold: regulator-s25fl064-hold {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_s25fl064_hold>;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "s25fl064_hold";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio3 17 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usb_hub_vbus: regulator-hub-otg1-vbus {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbhubpwr>;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_hub_vbus";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg1pwr>;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_otg1_vbus";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
user_leds: user-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_user_leds>,
|
||||
<&pinctrl_user_leds_snvs>;
|
||||
|
||||
user-led1 {
|
||||
label = "yellow";
|
||||
gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "off";
|
||||
};
|
||||
|
||||
user-led2 {
|
||||
label = "red";
|
||||
gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1>,
|
||||
<&pinctrl_ecspi1_cs>;
|
||||
cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>,
|
||||
<&gpio3 10 GPIO_ACTIVE_LOW>,
|
||||
<&gpio3 11 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
|
||||
tpm_tis: tpm@1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_tpm>;
|
||||
compatible = "tcg,tpm_tis-spi";
|
||||
reg = <1>;
|
||||
spi-max-frequency = <20000000>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
s25fl064: flash@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = " jedec,spi-nor";
|
||||
reg = <2>;
|
||||
spi-max-frequency = <40000000>;
|
||||
m25p,fast-read;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&ecspi3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi3>;
|
||||
cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
|
||||
dmas = <&sdma 7 8 0>,
|
||||
<&sdma 8 8 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ðphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet2>;
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <ðphy2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
tmp102: tmp@49 {
|
||||
compatible = "ti,tmp102";
|
||||
reg = <0x49>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_tempsense>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
i2c_rtc: rtc@68 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_rtc_int>;
|
||||
compatible = "microcrystal,rv4162";
|
||||
reg = <0x68>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
pinctrl-1 = <&pinctrl_i2c2_gpio>;
|
||||
sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
pinctrl-1 = <&pinctrl_i2c3_gpio>;
|
||||
sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c4>;
|
||||
pinctrl-1 = <&pinctrl_i2c4_gpio>;
|
||||
sda-gpios = <&gpio3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
scl-gpios = <&gpio3 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio {
|
||||
ethphy2: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
micrel,led-mode = <1>;
|
||||
clocks = <&clks IMX6UL_CLK_ENET2_REF>;
|
||||
clock-names = "rmii-ref";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm6 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm6>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm7 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm7>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm8 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* UART4 * RS485 */
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4>;
|
||||
rts-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>;
|
||||
rs485-rts-active-high;
|
||||
linux,rs485-enabled-at-boot-time;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* UART5 * RS232 */
|
||||
&uart5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart5>;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart7 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart7>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* USB */
|
||||
&usbotg1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb_otg1>;
|
||||
vbus-supply = <®_usb_otg1_vbus>;
|
||||
dr_mode = "host";
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg2 {
|
||||
vbus-supply = <®_usb_hub_vbus>;
|
||||
disable-over-current;
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
||||
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
|
||||
no-1-8-v;
|
||||
keep-power-in-suspend;
|
||||
wakeup-source;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&iomuxc_snvs {
|
||||
pinctrl_rtc_int: rtcintgrp {
|
||||
fsl,pins = <
|
||||
MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_stmpe: stmpegrp {
|
||||
fsl,pins = <
|
||||
MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_tempsense: tempsensegrp {
|
||||
fsl,pins = <
|
||||
MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_tpm: tpmgrp {
|
||||
fsl,pins = <
|
||||
MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbhubpwr: usbhubpwrgrp {
|
||||
fsl,pins = <
|
||||
MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_user_leds_snvs: user_ledsgrp {
|
||||
fsl,pins = <
|
||||
MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_gpio: gpiogrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x17059 /* nUART_MUX_RS232 */
|
||||
MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* nUART_MUX_DUAL_RX_TX */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_keys: gpiokeysgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x79
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi3: ecspi3grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x100b1
|
||||
MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x100b1
|
||||
MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x100b1
|
||||
MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x100b1
|
||||
MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100b1
|
||||
MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x100b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1_cs: ecspi1csgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0
|
||||
MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x10b0
|
||||
MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x10b0
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
pinctrl_enet2: enet2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
|
||||
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
|
||||
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
|
||||
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
|
||||
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010
|
||||
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010
|
||||
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010
|
||||
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan1: flexcan1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
|
||||
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan2: flexcan2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0b0b0
|
||||
MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
princtrl_flexcan2_en: flexcan2engrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0xb0
|
||||
MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0xb0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2_gpio: i2c2gpiogrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0
|
||||
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_LCD_DATA01__I2C3_SCL 0xb0
|
||||
MX6UL_PAD_LCD_DATA00__I2C3_SDA 0xb0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3_gpio: i2c3gpiogrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0xb0
|
||||
MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0xb0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c4: i2c4grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_LCD_DATA03__I2C4_SCL 0xb0
|
||||
MX6UL_PAD_LCD_DATA02__I2C4_SDA 0xb0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c4_gpio: i2c4gpiogrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0xb0
|
||||
MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0xb0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm3: pwm3grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm6: pwm6grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm7: pwm7grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm8: pwm8grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_s25fl064_hold: s25fl064holdgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x100b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sai2: sai2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
|
||||
MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
|
||||
MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
|
||||
MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
|
||||
MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
|
||||
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart4: uart4grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1
|
||||
MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1
|
||||
MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart5: uart5grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
|
||||
MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart7: uart7grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x1b0b1
|
||||
MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usb_otg1: usbotg1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x80
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg1pwr: usbotg1pwrgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
|
||||
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
|
||||
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
|
||||
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
|
||||
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
|
||||
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
|
||||
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
|
||||
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
|
||||
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
|
||||
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
|
||||
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
|
||||
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
|
||||
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
|
||||
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
|
||||
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
|
||||
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
|
||||
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_user_leds: userledsgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x79
|
||||
>;
|
||||
};
|
||||
};
|
15
arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts
Normal file
15
arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts
Normal file
@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
|
||||
/*
|
||||
* Copyright 2018-2022 TQ-Systems GmbH
|
||||
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6ull-tqma6ull2.dtsi"
|
||||
#include "mba6ulx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TQ-Systems TQMa6ULL2 SoM on MBa6ULx board";
|
||||
compatible = "tq,imx6ull-tqma6ull2-mba6ulx", "tq,imx6ull-tqma6ull2", "fsl,imx6ull";
|
||||
};
|
76
arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi
Normal file
76
arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi
Normal file
@ -0,0 +1,76 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
|
||||
/*
|
||||
* Copyright 2018-2022 TQ-Systems GmbH
|
||||
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
|
||||
*/
|
||||
|
||||
#include "imx6ull.dtsi"
|
||||
#include "imx6ul-tqma6ul-common.dtsi"
|
||||
#include "imx6ul-tqma6ulx-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TQ-Systems TQMa6ULL2 SoM";
|
||||
compatible = "tq,imx6ull-tqma6ull2", "fsl,imx6ull";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
fsl,tuning-step = <6>;
|
||||
/* Errata ERR010450 Workaround */
|
||||
max-frequency = <99000000>;
|
||||
assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
|
||||
assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
|
||||
assigned-clock-rates = <0>, <198000000>;
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031
|
||||
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039
|
||||
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039
|
||||
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039
|
||||
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039
|
||||
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039
|
||||
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039
|
||||
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039
|
||||
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039
|
||||
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039
|
||||
/* rst */
|
||||
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1
|
||||
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
|
||||
/* rst */
|
||||
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1
|
||||
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
|
||||
/* rst */
|
||||
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
|
||||
>;
|
||||
};
|
||||
};
|
15
arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts
Normal file
15
arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts
Normal file
@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
|
||||
/*
|
||||
* Copyright 2018-2022 TQ-Systems GmbH
|
||||
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6ull-tqma6ull2l.dtsi"
|
||||
#include "mba6ulx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TQ Systems TQMa6ULL2L SoM on MBa6ULx board";
|
||||
compatible = "tq,imx6ull-tqma6ull2l-mba6ulx", "tq,imx6ull-tqma6ull2l", "fsl,imx6ull";
|
||||
};
|
76
arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi
Normal file
76
arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi
Normal file
@ -0,0 +1,76 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
|
||||
/*
|
||||
* Copyright 2018-2022 TQ-Systems GmbH
|
||||
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
|
||||
*/
|
||||
|
||||
#include "imx6ull.dtsi"
|
||||
#include "imx6ul-tqma6ul-common.dtsi"
|
||||
#include "imx6ul-tqma6ulxl-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TQ Systems TQMa6ULL2L SoM";
|
||||
compatible = "tq,imx6ull-tqma6ull2l", "fsl,imx6ull";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
fsl,tuning-step = <6>;
|
||||
/* Errata ERR010450 Workaround */
|
||||
max-frequency = <99000000>;
|
||||
assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
|
||||
assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
|
||||
assigned-clock-rates = <0>, <198000000>;
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031
|
||||
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039
|
||||
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039
|
||||
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039
|
||||
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039
|
||||
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039
|
||||
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039
|
||||
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039
|
||||
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039
|
||||
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039
|
||||
/* rst */
|
||||
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1
|
||||
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
|
||||
/* rst */
|
||||
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1
|
||||
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
|
||||
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
|
||||
/* rst */
|
||||
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
|
||||
>;
|
||||
};
|
||||
};
|
112
arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi
Normal file
112
arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi
Normal file
@ -0,0 +1,112 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2022 Toradex
|
||||
*/
|
||||
|
||||
/ {
|
||||
reg_3v3_vmmc: regulator-3v3-vmmc {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* SODIMM 100 */
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-name = "3v3_vmmc";
|
||||
startup-delay-us = <100>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Colibri AD0 to AD3 */
|
||||
&adc1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri SSP */
|
||||
&ecspi3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri Fast Ethernet */
|
||||
&fec1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
/*
|
||||
* uart_b_c_on_x14_enable turns the UART transceiver for UART2 and 5 on. If one wants to
|
||||
* turn the transceiver off, that property has to be deleted and the gpio handled in
|
||||
* userspace.
|
||||
* The same applies to uart_a_on_x13_enable where the UART_A transceiver is turned on.
|
||||
*/
|
||||
uart-b-c-on-x14-enable-hog {
|
||||
gpio-hog;
|
||||
gpios = <27 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
uart-a-on-x13-enable-hog {
|
||||
gpio-hog;
|
||||
gpios = <17 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri PWM<A> */
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri PWM<B> */
|
||||
&pwm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri PWM<C> */
|
||||
&pwm3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri PWM<D> */
|
||||
&pwm4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* M41T0M6 real time clock */
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri UART_A */
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri UART_B */
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri UART_C */
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri USBC */
|
||||
&usbotg1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri MMC/SD, UHS-I capable uSD slot */
|
||||
&usdhc1 {
|
||||
cap-power-off-card;
|
||||
/delete-property/ keep-power-in-suspend;
|
||||
/delete-property/ no-1-8-v;
|
||||
vmmc-supply = <®_3v3_vmmc>;
|
||||
status = "okay";
|
||||
};
|
108
arch/arm/boot/dts/imx7-colibri-iris.dtsi
Normal file
108
arch/arm/boot/dts/imx7-colibri-iris.dtsi
Normal file
@ -0,0 +1,108 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2022 Toradex
|
||||
*/
|
||||
|
||||
/* Colibri AD0 to AD3 */
|
||||
&adc1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3.
|
||||
* So if you enable following capacitive touch controller, disable pwm2/pwm3 first.
|
||||
*/
|
||||
&atmel_mxt_ts {
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 / INT */
|
||||
pinctrl-0 = <&pinctrl_atmel_adapter>;
|
||||
reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 30 / RST */
|
||||
};
|
||||
|
||||
/* Colibri SSP */
|
||||
&ecspi3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri Fast Ethernet */
|
||||
&fec1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
/*
|
||||
* uart25 turns the UART transceiver for UART2 and 5 on. If one wants to turn the
|
||||
* transceiver off, that property has to be deleted and the gpio handled in userspace.
|
||||
* The same applies to uart1_tx_on where the UART1 transceiver is turned on.
|
||||
*/
|
||||
uart25-tx-on-hog {
|
||||
gpio-hog;
|
||||
gpios = <27 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
uart1-tx-on-hog {
|
||||
gpio-hog;
|
||||
gpios = <17 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri PWM<A> */
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri PWM<B> */
|
||||
&pwm2 {
|
||||
/* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri PWM<C> */
|
||||
&pwm3 {
|
||||
/* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri PWM<D> */
|
||||
&pwm4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* M41T0M6 real time clock */
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri UART_A */
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri UART_B */
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri UART_C */
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri USBC */
|
||||
&usbotg1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri MMC/SD */
|
||||
&usdhc1 {
|
||||
status = "okay";
|
||||
};
|
21
arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts
Normal file
21
arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts
Normal file
@ -0,0 +1,21 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2022 Toradex
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx7d-colibri-emmc.dtsi"
|
||||
#include "imx7-colibri-iris-v2.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Colibri iMX7D 1GB on Iris V2 Carrier Board";
|
||||
compatible = "toradex,colibri-imx7d-emmc-iris-v2",
|
||||
"toradex,colibri-imx7d-emmc",
|
||||
"toradex,colibri-imx7d",
|
||||
"fsl,imx7d";
|
||||
};
|
||||
|
||||
/* Colibri USBH */
|
||||
&usbotg2 {
|
||||
status = "okay";
|
||||
};
|
21
arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts
Normal file
21
arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts
Normal file
@ -0,0 +1,21 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2022 Toradex
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx7d-colibri-emmc.dtsi"
|
||||
#include "imx7-colibri-iris.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Colibri iMX7D 1GB on Iris Carrier Board";
|
||||
compatible = "toradex,colibri-imx7d-emmc-iris",
|
||||
"toradex,colibri-imx7d-emmc",
|
||||
"toradex,colibri-imx7d",
|
||||
"fsl,imx7d";
|
||||
};
|
||||
|
||||
/* Colibri USBH */
|
||||
&usbotg2 {
|
||||
status = "okay";
|
||||
};
|
83
arch/arm/boot/dts/imx7d-colibri-iris-v2.dts
Normal file
83
arch/arm/boot/dts/imx7d-colibri-iris-v2.dts
Normal file
@ -0,0 +1,83 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2022 Toradex
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx7d-colibri.dtsi"
|
||||
#include "imx7-colibri-iris-v2.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Colibri iMX7D on Iris V2 Carrier Board";
|
||||
compatible = "toradex,colibri-imx7d-iris-v2",
|
||||
"toradex,colibri-imx7d",
|
||||
"fsl,imx7d";
|
||||
};
|
||||
|
||||
&ad7879_ts {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&atmel_mxt_ts {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&backlight {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
/*
|
||||
* This switches the LVDS transceiver to VESA color mapping mode.
|
||||
*/
|
||||
lvds-color-map-hog {
|
||||
gpio-hog;
|
||||
gpios = <13 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */
|
||||
line-name = "LVDS_COLOR_MAP";
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio7 {
|
||||
/*
|
||||
* This switches the LVDS transceiver to the 24-bit RGB mode.
|
||||
*/
|
||||
lvds-rgb-mode-hog {
|
||||
gpio-hog;
|
||||
gpios = <2 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */
|
||||
line-name = "LVDS_RGB_MODE";
|
||||
output-low;
|
||||
};
|
||||
|
||||
/*
|
||||
* This switches the LVDS transceiver to the single-channel
|
||||
* output mode.
|
||||
*/
|
||||
lvds-ch-mode-hog {
|
||||
gpio-hog;
|
||||
gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */
|
||||
line-name = "LVDS_CH_MODE";
|
||||
output-high;
|
||||
};
|
||||
|
||||
/* This turns the LVDS transceiver on */
|
||||
lvds-power-on-hog {
|
||||
gpio-hog;
|
||||
gpios = <11 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */
|
||||
line-name = "LVDS_POWER_ON";
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
&lcdif {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&panel_dpi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri USBH */
|
||||
&usbotg2 {
|
||||
status = "okay";
|
||||
};
|
56
arch/arm/boot/dts/imx7d-colibri-iris.dts
Normal file
56
arch/arm/boot/dts/imx7d-colibri-iris.dts
Normal file
@ -0,0 +1,56 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2022 Toradex
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx7d-colibri.dtsi"
|
||||
#include "imx7-colibri-iris.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Colibri iMX7D on Iris Carrier Board";
|
||||
compatible = "toradex,colibri-imx7d-iris",
|
||||
"toradex,colibri-imx7d",
|
||||
"fsl,imx7d";
|
||||
};
|
||||
|
||||
&ad7879_ts {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3.
|
||||
* So if you enable following capacitive touch controller, disable pwm2/pwm3 first.
|
||||
*/
|
||||
&atmel_mxt_ts {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&backlight {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lcdif {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&panel_dpi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri PWM<B> */
|
||||
&pwm2 {
|
||||
/* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri PWM<C> */
|
||||
&pwm3 {
|
||||
/* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri USBH */
|
||||
&usbotg2 {
|
||||
status = "okay";
|
||||
};
|
467
arch/arm/boot/dts/imx7d-smegw01.dts
Normal file
467
arch/arm/boot/dts/imx7d-smegw01.dts
Normal file
@ -0,0 +1,467 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
//
|
||||
// Copyright (C) 2020 PHYTEC Messtechnik GmbH
|
||||
// Author: Jens Lang <J.Lang@phytec.de>
|
||||
// Copyright (C) 2021 Fabio Estevam <festevam@denx.de>
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "imx7d.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Storopack SMEGW01 board";
|
||||
compatible = "storopack,imx7d-smegw01", "fsl,imx7d";
|
||||
|
||||
aliases {
|
||||
mmc0 = &usdhc1;
|
||||
mmc1 = &usdhc3;
|
||||
mmc2 = &usdhc2;
|
||||
rtc0 = &i2c_rtc;
|
||||
rtc1 = &snvs_rtc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart1;
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x20000000>;
|
||||
};
|
||||
|
||||
reg_lte_on: regulator-lte-on {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lte_on>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "lte_on";
|
||||
gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_lte_nreset: regulator-lte-nreset {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lte_nreset>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "LTE_nReset";
|
||||
gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_wifi: regulator-wifi {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wifi>;
|
||||
regulator-name = "wifi_reg";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
reg_wlan_rfkill: regulator-wlan-rfkill {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-2 = <&pinctrl_rfkill>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "wlan_rfkill";
|
||||
gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usbotg_vbus: regulator-usbotg-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg1_pwr_gpio>;
|
||||
regulator-name = "usb_otg_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 05 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1>;
|
||||
cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
|
||||
sram@0 {
|
||||
compatible = "microchip,48l640";
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <16000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet1>;
|
||||
assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
|
||||
<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
|
||||
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
|
||||
assigned-clock-rates = <0>, <100000000>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy0>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
|
||||
mdio: mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy0: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-id0022.1622",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
ethphy1: ethernet-phy@2 {
|
||||
compatible = "ethernet-phy-id0022.1622",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
reg = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet2>;
|
||||
assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
|
||||
<&clks IMX7D_ENET2_TIME_ROOT_CLK>;
|
||||
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
|
||||
assigned-clock-rates = <0>, <100000000>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy1>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 =<&pinctrl_i2c2>;
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
|
||||
i2c_rtc: rtc@52 {
|
||||
compatible = "microcrystal,rv3028";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_rtc_int>;
|
||||
reg = <0x52>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&flexcan1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&flexcan2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg1_lpsr>;
|
||||
dr_mode = "otg";
|
||||
vbus-supply = <®_usbotg_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg2>;
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
|
||||
no-1-8-v;
|
||||
wakeup-source;
|
||||
keep-power-in-suspend;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
bus-width = <4>;
|
||||
no-1-8-v;
|
||||
non-removable;
|
||||
vmmc-supply = <®_wifi>;
|
||||
wakeup-source;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
max-frequency = <200000000>;
|
||||
bus-width = <8>;
|
||||
fsl,tuning-step = <1>;
|
||||
non-removable;
|
||||
cap-mmc-highspeed;
|
||||
cap-mmc-hw-reset;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-ddr-1_8v;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x04
|
||||
MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x04
|
||||
MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x04
|
||||
MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x04
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet1: enet1grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x5
|
||||
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x5
|
||||
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x5
|
||||
MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x5
|
||||
MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x5
|
||||
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x5
|
||||
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x5
|
||||
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x5
|
||||
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x5
|
||||
MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x5
|
||||
MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x5
|
||||
MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x5
|
||||
MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x7
|
||||
MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x7
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet2: enet2grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x5
|
||||
MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x5
|
||||
MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x5
|
||||
MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x5
|
||||
MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x5
|
||||
MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x5
|
||||
MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x5
|
||||
MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x5
|
||||
MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x5
|
||||
MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x5
|
||||
MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x5
|
||||
MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x5
|
||||
MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x08
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000004
|
||||
MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000004
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan1: flexcan1grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0b0b0
|
||||
MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan2: flexcan2grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x0b0b0
|
||||
MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lte_on: lteongrp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lte_nreset: ltenresetgrp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_rfkill: rfkillrp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_rtc_int: rtcintgrp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x74
|
||||
MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x7c
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x7c
|
||||
MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x74
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg1_lpsr: usbotg1 {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x04
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg1_pwr: usbotg1-pwr {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x04
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg1_pwr_gpio: usbotg1-pwr-gpio {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x04
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg2: usbotg2grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x04
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59
|
||||
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
|
||||
MX7D_PAD_SD1_CLK__SD1_CLK 0x19
|
||||
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
|
||||
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
|
||||
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
|
||||
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SD2_CLK__SD2_CLK 0x19
|
||||
MX7D_PAD_SD2_CMD__SD2_CMD 0x59
|
||||
MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
|
||||
MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
|
||||
MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
|
||||
MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
|
||||
MX7D_PAD_SD2_CD_B__SD2_CD_B 0x08
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SD3_CMD__SD3_CMD 0x5d
|
||||
MX7D_PAD_SD3_CLK__SD3_CLK 0x1d
|
||||
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5d
|
||||
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5d
|
||||
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5d
|
||||
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5d
|
||||
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5d
|
||||
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5d
|
||||
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5d
|
||||
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5d
|
||||
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1d
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SD3_CMD__SD3_CMD 0x5e
|
||||
MX7D_PAD_SD3_CLK__SD3_CLK 0x1e
|
||||
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5e
|
||||
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5e
|
||||
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5e
|
||||
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5e
|
||||
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5e
|
||||
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5e
|
||||
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5e
|
||||
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5e
|
||||
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_SD3_CMD__SD3_CMD 0x5f
|
||||
MX7D_PAD_SD3_CLK__SD3_CLK 0x0f
|
||||
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5f
|
||||
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5f
|
||||
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5f
|
||||
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5f
|
||||
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5f
|
||||
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5f
|
||||
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5f
|
||||
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5f
|
||||
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1f
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wifi: wifigrp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x04
|
||||
MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x04
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc_lpsr {
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
|
||||
>;
|
||||
};
|
||||
};
|
78
arch/arm/boot/dts/imx7s-colibri-iris-v2.dts
Normal file
78
arch/arm/boot/dts/imx7s-colibri-iris-v2.dts
Normal file
@ -0,0 +1,78 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2022 Toradex
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx7s-colibri.dtsi"
|
||||
#include "imx7-colibri-iris-v2.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Colibri iMX7S on Iris V2 Carrier Board";
|
||||
compatible = "toradex,colibri-imx7s-iris-v2",
|
||||
"toradex,colibri-imx7s",
|
||||
"fsl,imx7s";
|
||||
};
|
||||
|
||||
&ad7879_ts {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&atmel_mxt_ts {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&backlight {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
/*
|
||||
* This switches the LVDS transceiver to VESA color mapping mode.
|
||||
*/
|
||||
lvds-color-map-hog {
|
||||
gpio-hog;
|
||||
gpios = <13 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */
|
||||
line-name = "LVDS_COLOR_MAP";
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio7 {
|
||||
/*
|
||||
* This switches the LVDS transceiver to the 24-bit RGB mode.
|
||||
*/
|
||||
lvds-rgb-mode-hog {
|
||||
gpio-hog;
|
||||
gpios = <2 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */
|
||||
line-name = "LVDS_RGB_MODE";
|
||||
output-low;
|
||||
};
|
||||
|
||||
/*
|
||||
* This switches the LVDS transceiver to the single-channel
|
||||
* output mode.
|
||||
*/
|
||||
lvds-ch-mode-hog {
|
||||
gpio-hog;
|
||||
gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */
|
||||
line-name = "LVDS_CH_MODE";
|
||||
output-high;
|
||||
};
|
||||
|
||||
/* This turns the LVDS transceiver on */
|
||||
lvds-power-on-hog {
|
||||
gpio-hog;
|
||||
gpios = <11 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */
|
||||
line-name = "LVDS_POWER_ON";
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
&lcdif {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&panel_dpi {
|
||||
status = "okay";
|
||||
};
|
51
arch/arm/boot/dts/imx7s-colibri-iris.dts
Normal file
51
arch/arm/boot/dts/imx7s-colibri-iris.dts
Normal file
@ -0,0 +1,51 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2022 Toradex
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx7s-colibri.dtsi"
|
||||
#include "imx7-colibri-iris.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Colibri iMX7S on Iris Carrier Board";
|
||||
compatible = "toradex,colibri-imx7s-iris",
|
||||
"toradex,colibri-imx7s",
|
||||
"fsl,imx7s";
|
||||
};
|
||||
|
||||
&ad7879_ts {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* The Atmel maxtouch controller uses SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3.
|
||||
* So if you enable following capacitive touch controller, disable pwm2/pwm3 first.
|
||||
*/
|
||||
&atmel_mxt_ts {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&backlight {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lcdif {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&panel_dpi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri PWM<B> */
|
||||
&pwm2 {
|
||||
/* The pwm2 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Colibri PWM<C> */
|
||||
&pwm3 {
|
||||
/* The pwm3 should be disabled to enable atmel_mxt_ts touchscreen for adapter. */
|
||||
status = "okay";
|
||||
};
|
72
arch/arm/boot/dts/imxrt1050-evk.dts
Normal file
72
arch/arm/boot/dts/imxrt1050-evk.dts
Normal file
@ -0,0 +1,72 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2019
|
||||
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imxrt1050.dtsi"
|
||||
#include "imxrt1050-pinfunc.h"
|
||||
|
||||
/ {
|
||||
model = "NXP IMXRT1050-evk board";
|
||||
compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
|
||||
|
||||
chosen {
|
||||
stdout-path = &lpuart1;
|
||||
};
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio1;
|
||||
gpio1 = &gpio2;
|
||||
gpio2 = &gpio3;
|
||||
gpio3 = &gpio4;
|
||||
gpio4 = &gpio5;
|
||||
mmc0 = &usdhc1;
|
||||
serial0 = &lpuart1;
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&lpuart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lpuart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl_lpuart1: lpuart1grp {
|
||||
fsl,pins = <
|
||||
MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1
|
||||
MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc0: usdhc0grp {
|
||||
fsl,pins = <
|
||||
MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000
|
||||
MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069
|
||||
MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061
|
||||
MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061
|
||||
MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061
|
||||
MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061
|
||||
MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061
|
||||
MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
|
||||
pinctrl-0 = <&pinctrl_usdhc0>;
|
||||
pinctrl-1 = <&pinctrl_usdhc0>;
|
||||
pinctrl-2 = <&pinctrl_usdhc0>;
|
||||
pinctrl-3 = <&pinctrl_usdhc0>;
|
||||
cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
160
arch/arm/boot/dts/imxrt1050.dtsi
Normal file
160
arch/arm/boot/dts/imxrt1050.dtsi
Normal file
@ -0,0 +1,160 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2019
|
||||
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
|
||||
*/
|
||||
|
||||
#include "armv7-m.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/imxrt1050-clock.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
clocks {
|
||||
osc: osc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
osc3M: osc3M {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
lpuart1: serial@40184000 {
|
||||
compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart";
|
||||
reg = <0x40184000 0x4000>;
|
||||
interrupts = <20>;
|
||||
clocks = <&clks IMXRT1050_CLK_LPUART1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
iomuxc: pinctrl@401f8000 {
|
||||
compatible = "fsl,imxrt1050-iomuxc";
|
||||
reg = <0x401f8000 0x4000>;
|
||||
fsl,mux_mask = <0x7>;
|
||||
};
|
||||
|
||||
anatop: anatop@400d8000 {
|
||||
compatible = "fsl,imxrt-anatop";
|
||||
reg = <0x400d8000 0x4000>;
|
||||
};
|
||||
|
||||
clks: clock-controller@400fc000 {
|
||||
compatible = "fsl,imxrt1050-ccm";
|
||||
reg = <0x400fc000 0x4000>;
|
||||
interrupts = <95>, <96>;
|
||||
clocks = <&osc>;
|
||||
clock-names = "osc";
|
||||
#clock-cells = <1>;
|
||||
assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>,
|
||||
<&clks IMXRT1050_CLK_PLL1_BYPASS>,
|
||||
<&clks IMXRT1050_CLK_PLL2_BYPASS>,
|
||||
<&clks IMXRT1050_CLK_PLL3_BYPASS>,
|
||||
<&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>,
|
||||
<&clks IMXRT1050_CLK_PLL2_PFD2_396M>;
|
||||
assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>,
|
||||
<&clks IMXRT1050_CLK_PLL1_ARM>,
|
||||
<&clks IMXRT1050_CLK_PLL2_SYS>,
|
||||
<&clks IMXRT1050_CLK_PLL3_USB_OTG>,
|
||||
<&clks IMXRT1050_CLK_PLL3_USB_OTG>,
|
||||
<&clks IMXRT1050_CLK_PLL2_SYS>;
|
||||
};
|
||||
|
||||
edma1: dma-controller@400e8000 {
|
||||
#dma-cells = <2>;
|
||||
compatible = "fsl,imx7ulp-edma";
|
||||
reg = <0x400e8000 0x4000>,
|
||||
<0x400ec000 0x4000>;
|
||||
dma-channels = <32>;
|
||||
interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>,
|
||||
<9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>;
|
||||
clock-names = "dma", "dmamux0";
|
||||
clocks = <&clks IMXRT1050_CLK_DMA>,
|
||||
<&clks IMXRT1050_CLK_DMA_MUX>;
|
||||
};
|
||||
|
||||
usdhc1: mmc@402c0000 {
|
||||
compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc";
|
||||
reg = <0x402c0000 0x4000>;
|
||||
interrupts = <110>;
|
||||
clocks = <&clks IMXRT1050_CLK_IPG_PDOF>,
|
||||
<&clks IMXRT1050_CLK_OSC>,
|
||||
<&clks IMXRT1050_CLK_USDHC1>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
bus-width = <4>;
|
||||
fsl,wp-controller;
|
||||
no-1-8-v;
|
||||
max-frequency = <4000000>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio1: gpio@401b8000 {
|
||||
compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x401b8000 0x4000>;
|
||||
interrupts = <80>, <81>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@401bc000 {
|
||||
compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x401bc000 0x4000>;
|
||||
interrupts = <82>, <83>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@401c0000 {
|
||||
compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x401c0000 0x4000>;
|
||||
interrupts = <84>, <85>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio4: gpio@401c4000 {
|
||||
compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x401c4000 0x4000>;
|
||||
interrupts = <86>, <87>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio5: gpio@400c0000 {
|
||||
compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x400c0000 0x4000>;
|
||||
interrupts = <88>, <89>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpt: timer@401ec000 {
|
||||
compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt";
|
||||
reg = <0x401ec000 0x4000>;
|
||||
interrupts = <100>;
|
||||
clocks = <&osc3M>;
|
||||
clock-names = "per";
|
||||
};
|
||||
};
|
||||
};
|
1561
arch/arm/boot/dts/imxrt1170-pinfunc.h
Normal file
1561
arch/arm/boot/dts/imxrt1170-pinfunc.h
Normal file
File diff suppressed because it is too large
Load Diff
94
arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
Normal file
94
arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
Normal file
@ -0,0 +1,94 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree file for the Kontron KSwitch D10 MMT 6G-2GS
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "lan966x-kontron-kswitch-d10-mmt.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Kontron KSwitch D10 MMT 6G-2GS";
|
||||
compatible = "kontron,kswitch-d10-mmt-6g-2gs", "kontron,s1921",
|
||||
"microchip,lan9668", "microchip,lan966";
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c4;
|
||||
i2c1 = &i2c1;
|
||||
};
|
||||
|
||||
sfp0: sfp0 {
|
||||
compatible = "sff,sfp";
|
||||
i2c-bus = <&i2c4>;
|
||||
los-gpios = <&sgpio_in 1 0 GPIO_ACTIVE_HIGH>;
|
||||
mod-def0-gpios = <&sgpio_in 1 1 GPIO_ACTIVE_LOW>;
|
||||
maximum-power-milliwatt = <2500>;
|
||||
tx-disable-gpios = <&sgpio_out 3 0 GPIO_ACTIVE_LOW>;
|
||||
tx-fault-gpios = <&sgpio_in 0 2 GPIO_ACTIVE_HIGH>;
|
||||
rate-select0-gpios = <&sgpio_out 2 0 GPIO_ACTIVE_HIGH>;
|
||||
rate-select1-gpios = <&sgpio_out 2 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
sfp1: sfp1 {
|
||||
compatible = "sff,sfp";
|
||||
i2c-bus = <&i2c1>;
|
||||
los-gpios = <&sgpio_in 1 2 GPIO_ACTIVE_HIGH>;
|
||||
mod-def0-gpios = <&sgpio_in 1 3 GPIO_ACTIVE_LOW>;
|
||||
maximum-power-milliwatt = <2500>;
|
||||
tx-disable-gpios = <&sgpio_out 3 1 GPIO_ACTIVE_LOW>;
|
||||
tx-fault-gpios = <&sgpio_in 0 3 GPIO_ACTIVE_HIGH>;
|
||||
rate-select0-gpios = <&sgpio_out 2 2 GPIO_ACTIVE_HIGH>;
|
||||
rate-select1-gpios = <&sgpio_out 2 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&flx1 {
|
||||
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
|
||||
status = "okay";
|
||||
|
||||
i2c1: i2c@600 {
|
||||
pinctrl-0 = <&fc1_c_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&flx4 {
|
||||
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
|
||||
status = "okay";
|
||||
|
||||
i2c4: i2c@600 {
|
||||
pinctrl-0 = <&fc4_b_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
fc1_c_pins: fc1-c-i2c-pins {
|
||||
/* SCL, SDA */
|
||||
pins = "GPIO_47", "GPIO_48";
|
||||
function = "fc1_c";
|
||||
};
|
||||
|
||||
fc4_b_pins: fc4-b-i2c-pins {
|
||||
/* SCL, SDA */
|
||||
pins = "GPIO_57", "GPIO_58";
|
||||
function = "fc4_b";
|
||||
};
|
||||
};
|
||||
|
||||
&port2 {
|
||||
phys = <&serdes 2 SERDES6G(0)>;
|
||||
sfp = <&sfp0>;
|
||||
managed = "in-band-status";
|
||||
phy-mode = "sgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&port3 {
|
||||
phys = <&serdes 3 SERDES6G(1)>;
|
||||
sfp = <&sfp1>;
|
||||
managed = "in-band-status";
|
||||
phy-mode = "sgmii";
|
||||
status = "okay";
|
||||
};
|
39
arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts
Normal file
39
arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts
Normal file
@ -0,0 +1,39 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree file for the Kontron KSwitch D10 MMT 8G
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "lan966x-kontron-kswitch-d10-mmt.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Kontron KSwitch D10 MMT 8G";
|
||||
compatible = "kontron,kswitch-d10-mmt-8g", "kontron,s1921",
|
||||
"microchip,lan9668", "microchip,lan966";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
phy2: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
phy3: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
&port2 {
|
||||
phys = <&serdes 2 SERDES6G(0)>;
|
||||
phy-handle = <&phy2>;
|
||||
phy-mode = "sgmii";
|
||||
managed = "in-band-status";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&port3 {
|
||||
phys = <&serdes 3 SERDES6G(1)>;
|
||||
phy-handle = <&phy3>;
|
||||
phy-mode = "sgmii";
|
||||
managed = "in-band-status";
|
||||
status = "okay";
|
||||
};
|
203
arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi
Normal file
203
arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi
Normal file
@ -0,0 +1,203 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Common part of the device tree for the Kontron KSwitch D10 MMT
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "lan966x.dtsi"
|
||||
#include "dt-bindings/phy/phy-lan966x-serdes.h"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
serial0 = &usart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-restart {
|
||||
compatible = "gpio-restart";
|
||||
gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
|
||||
priority = <200>;
|
||||
};
|
||||
};
|
||||
|
||||
&flx0 {
|
||||
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
|
||||
status = "okay";
|
||||
|
||||
usart0: serial@200 {
|
||||
pinctrl-0 = <&usart0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&flx3 {
|
||||
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
|
||||
status = "okay";
|
||||
|
||||
spi3: spi@400 {
|
||||
pinctrl-0 = <&fc3_b_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
cs-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
fc3_b_pins: fc3-b-pins {
|
||||
/* SCK, MISO, MOSI */
|
||||
pins = "GPIO_51", "GPIO_52", "GPIO_53";
|
||||
function = "fc3_b";
|
||||
};
|
||||
|
||||
miim_c_pins: miim-c-pins {
|
||||
/* MDC, MDIO */
|
||||
pins = "GPIO_59", "GPIO_60";
|
||||
function = "miim_c";
|
||||
};
|
||||
|
||||
sgpio_a_pins: sgpio-a-pins {
|
||||
/* SCK, D0, D1 */
|
||||
pins = "GPIO_32", "GPIO_33", "GPIO_34";
|
||||
function = "sgpio_a";
|
||||
};
|
||||
|
||||
sgpio_b_pins: sgpio-b-pins {
|
||||
/* LD */
|
||||
pins = "GPIO_64";
|
||||
function = "sgpio_b";
|
||||
};
|
||||
|
||||
usart0_pins: usart0-pins {
|
||||
/* RXD, TXD */
|
||||
pins = "GPIO_25", "GPIO_26";
|
||||
function = "fc0_b";
|
||||
};
|
||||
|
||||
usbs_a_pins: usbs-a-pins {
|
||||
/* VBUS_DET */
|
||||
pins = "GPIO_66";
|
||||
function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
pinctrl-0 = <&miim_c_pins>;
|
||||
pinctrl-names = "default";
|
||||
reset-gpios = <&gpio 29 GPIO_ACTIVE_LOW>;
|
||||
clock-frequency = <2500000>;
|
||||
status = "okay";
|
||||
|
||||
phy4: ethernet-phy@5 {
|
||||
reg = <5>;
|
||||
coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>;
|
||||
};
|
||||
|
||||
phy5: ethernet-phy@6 {
|
||||
reg = <6>;
|
||||
coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>;
|
||||
};
|
||||
|
||||
phy6: ethernet-phy@7 {
|
||||
reg = <7>;
|
||||
coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>;
|
||||
};
|
||||
|
||||
phy7: ethernet-phy@8 {
|
||||
reg = <8>;
|
||||
coma-mode-gpios = <&gpio 37 GPIO_OPEN_DRAIN>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&port0 {
|
||||
phys = <&serdes 0 CU(0)>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "gmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&port1 {
|
||||
phys = <&serdes 1 CU(1)>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-mode = "gmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&port4 {
|
||||
phys = <&serdes 4 SERDES6G(2)>;
|
||||
phy-handle = <&phy4>;
|
||||
phy-mode = "qsgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&port5 {
|
||||
phys = <&serdes 5 SERDES6G(2)>;
|
||||
phy-handle = <&phy5>;
|
||||
phy-mode = "qsgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&port6 {
|
||||
phys = <&serdes 6 SERDES6G(2)>;
|
||||
phy-handle = <&phy6>;
|
||||
phy-mode = "qsgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&port7 {
|
||||
phys = <&serdes 7 SERDES6G(2)>;
|
||||
phy-handle = <&phy7>;
|
||||
phy-mode = "qsgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&serdes {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sgpio {
|
||||
pinctrl-0 = <&sgpio_a_pins>, <&sgpio_b_pins>;
|
||||
pinctrl-names = "default";
|
||||
bus-frequency = <8000000>;
|
||||
/* arbitrary range because all GPIOs are in software mode */
|
||||
microchip,sgpio-port-ranges = <0 11>;
|
||||
status = "okay";
|
||||
|
||||
sgpio_in: gpio@0 {
|
||||
ngpios = <128>;
|
||||
};
|
||||
|
||||
sgpio_out: gpio@1 {
|
||||
ngpios = <128>;
|
||||
};
|
||||
};
|
||||
|
||||
&switch {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&udc {
|
||||
pinctrl-0 = <&usbs_a_pins>;
|
||||
pinctrl-names = "default";
|
||||
atmel,vbus-gpio = <&gpio 66 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog {
|
||||
status = "okay";
|
||||
};
|
184
arch/arm/boot/dts/lan966x-pcb8309.dts
Normal file
184
arch/arm/boot/dts/lan966x-pcb8309.dts
Normal file
@ -0,0 +1,184 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* lan966x_pcb8309.dts - Device Tree file for PCB8309
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "lan966x.dtsi"
|
||||
#include "dt-bindings/phy/phy-lan966x-serdes.h"
|
||||
|
||||
/ {
|
||||
model = "Microchip EVB - LAN9662";
|
||||
compatible = "microchip,lan9662-pcb8309", "microchip,lan9662", "microchip,lan966";
|
||||
|
||||
aliases {
|
||||
serial0 = &usart3;
|
||||
i2c102 = &i2c102;
|
||||
i2c103 = &i2c103;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
gpio-restart {
|
||||
compatible = "gpio-restart";
|
||||
gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
|
||||
priority = <200>;
|
||||
};
|
||||
|
||||
i2c-mux {
|
||||
compatible = "i2c-mux";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
mux-controls = <&mux>;
|
||||
i2c-parent = <&i2c4>;
|
||||
|
||||
i2c102: i2c-sfp@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
i2c103: i2c-sfp@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
mux: mux-controller {
|
||||
compatible = "gpio-mux";
|
||||
#mux-control-cells = <0>;
|
||||
|
||||
mux-gpios = <&sgpio_out 11 0 GPIO_ACTIVE_HIGH>, /* p11b0 */
|
||||
<&sgpio_out 11 1 GPIO_ACTIVE_HIGH>; /* p11b1 */
|
||||
};
|
||||
|
||||
sfp2: sfp2 {
|
||||
compatible = "sff,sfp";
|
||||
i2c-bus = <&i2c102>;
|
||||
tx-disable-gpios = <&sgpio_out 10 0 GPIO_ACTIVE_LOW>;
|
||||
los-gpios = <&sgpio_in 2 0 GPIO_ACTIVE_HIGH>;
|
||||
mod-def0-gpios = <&sgpio_in 2 1 GPIO_ACTIVE_LOW>;
|
||||
tx-fault-gpios = <&sgpio_in 1 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
sfp3: sfp3 {
|
||||
compatible = "sff,sfp";
|
||||
i2c-bus = <&i2c103>;
|
||||
tx-disable-gpios = <&sgpio_out 10 1 GPIO_ACTIVE_LOW>;
|
||||
los-gpios = <&sgpio_in 3 0 GPIO_ACTIVE_HIGH>;
|
||||
mod-def0-gpios = <&sgpio_in 3 1 GPIO_ACTIVE_LOW>;
|
||||
tx-fault-gpios = <&sgpio_in 1 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&flx3 {
|
||||
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
|
||||
status = "okay";
|
||||
|
||||
usart3: serial@200 {
|
||||
pinctrl-0 = <&fc3_b_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&flx4 {
|
||||
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
|
||||
status = "okay";
|
||||
|
||||
i2c4: i2c@600 {
|
||||
compatible = "microchip,sam9x60-i2c";
|
||||
reg = <0x600 0x200>;
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&nic_clk>;
|
||||
pinctrl-0 = <&fc4_b_pins>;
|
||||
pinctrl-names = "default";
|
||||
i2c-analog-filter;
|
||||
i2c-digital-filter;
|
||||
i2c-digital-filter-width-ns = <35>;
|
||||
i2c-sda-hold-time-ns = <1500>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
fc3_b_pins: fc3-b-pins {
|
||||
/* RXD, TXD */
|
||||
pins = "GPIO_52", "GPIO_53";
|
||||
function = "fc3_b";
|
||||
};
|
||||
|
||||
fc4_b_pins: fc4-b-pins {
|
||||
/* SCL, SDA */
|
||||
pins = "GPIO_57", "GPIO_58";
|
||||
function = "fc4_b";
|
||||
};
|
||||
|
||||
sgpio_a_pins: sgpio-a-pins {
|
||||
/* SCK, D0, D1, LD */
|
||||
pins = "GPIO_32", "GPIO_33", "GPIO_34", "GPIO_35";
|
||||
function = "sgpio_a";
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&port0 {
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "gmii";
|
||||
phys = <&serdes 0 CU(0)>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&port1 {
|
||||
phy-handle = <&phy1>;
|
||||
phy-mode = "gmii";
|
||||
phys = <&serdes 1 CU(1)>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&port2 {
|
||||
sfp = <&sfp2>;
|
||||
managed = "in-band-status";
|
||||
phy-mode = "sgmii";
|
||||
phys = <&serdes 2 SERDES6G(0)>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&port3 {
|
||||
sfp = <&sfp3>;
|
||||
managed = "in-band-status";
|
||||
phy-mode = "sgmii";
|
||||
phys = <&serdes 3 SERDES6G(1)>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&serdes {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sgpio {
|
||||
pinctrl-0 = <&sgpio_a_pins>;
|
||||
pinctrl-names = "default";
|
||||
microchip,sgpio-port-ranges = <0 3>, <8 11>;
|
||||
status = "okay";
|
||||
|
||||
gpio@0 {
|
||||
ngpios = <64>;
|
||||
};
|
||||
gpio@1 {
|
||||
ngpios = <64>;
|
||||
};
|
||||
};
|
||||
|
||||
&switch {
|
||||
status = "okay";
|
||||
};
|
227
arch/arm/boot/dts/ls1021a-iot.dts
Normal file
227
arch/arm/boot/dts/ls1021a-iot.dts
Normal file
@ -0,0 +1,227 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright 2021-2022 NXP
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "ls1021a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "LS1021A-IOT Board";
|
||||
compatible = "fsl,ls1021a-iot", "fsl,ls1021a";
|
||||
|
||||
sys_mclk: clock-mclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24576000>;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator-3V3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_2p5v: regulator-2V5 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "2P5V";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,widgets =
|
||||
"Microphone", "Microphone Jack",
|
||||
"Headphone", "Headphone Jack",
|
||||
"Speaker", "Speaker Ext",
|
||||
"Line", "Line In Jack";
|
||||
simple-audio-card,routing =
|
||||
"MIC_IN", "Microphone Jack",
|
||||
"Microphone Jack", "Mic Bias",
|
||||
"LINE_IN", "Line In Jack",
|
||||
"Headphone Jack", "HP_OUT",
|
||||
"Speaker Ext", "LINE_OUT";
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&sai2>;
|
||||
frame-master;
|
||||
bitclock-master;
|
||||
};
|
||||
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&sgtl5000>;
|
||||
frame-master;
|
||||
bitclock-master;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&can0{
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&can1{
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&can2{
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&can3{
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dcu {
|
||||
display = <&display>;
|
||||
status = "okay";
|
||||
|
||||
display: display@0 {
|
||||
bits-per-pixel = <24>;
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
|
||||
timing0: mode0 {
|
||||
clock-frequency = <25000000>;
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <80>;
|
||||
hfront-porch = <80>;
|
||||
vback-porch = <16>;
|
||||
vfront-porch = <16>;
|
||||
hsync-len = <12>;
|
||||
vsync-len = <2>;
|
||||
hsync-active = <1>;
|
||||
vsync-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&enet0 {
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "sgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet1 {
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&phy3>;
|
||||
phy-connection-type = "sgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet2 {
|
||||
fixed-link = <0 1 1000 0 0>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc{
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
pca9555: gpio@23 {
|
||||
compatible = "nxp,pca9555";
|
||||
reg = <0x23>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
sgtl5000: audio-codec@2a {
|
||||
#sound-dai-cells = <0x0>;
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x2a>;
|
||||
VDDA-supply = <®_3p3v>;
|
||||
VDDIO-supply = <®_2p5v>;
|
||||
clocks = <&sys_mclk>;
|
||||
};
|
||||
|
||||
max1239: adc@35 {
|
||||
compatible = "maxim,max1239";
|
||||
reg = <0x35>;
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
ina2201: core-monitor@44 {
|
||||
compatible = "ti,ina220";
|
||||
reg = <0x44>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
ina2202: current-monitor@45 {
|
||||
compatible = "ti,ina220";
|
||||
reg = <0x45>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
lm75b: thermal-monitor@48 {
|
||||
compatible = "national,lm75b";
|
||||
reg = <0x48>;
|
||||
};
|
||||
};
|
||||
|
||||
&lpuart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
phy2: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
phy3: ethernet-phy@3 {
|
||||
reg = <0x3>;
|
||||
};
|
||||
|
||||
tbi1: tbi-phy@1f {
|
||||
reg = <0x1f>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
num-cs = <2>;
|
||||
status = "okay";
|
||||
|
||||
s25fl128s: flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&sai2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
569
arch/arm/boot/dts/mba6ulx.dtsi
Normal file
569
arch/arm/boot/dts/mba6ulx.dtsi
Normal file
@ -0,0 +1,569 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
|
||||
/*
|
||||
* Copyright 2018-2022 TQ-Systems GmbH
|
||||
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
|
||||
*/
|
||||
|
||||
/ {
|
||||
model = "TQ-Systems MBA6ULx Baseboard";
|
||||
|
||||
aliases {
|
||||
mmc0 = &usdhc2;
|
||||
mmc1 = &usdhc1;
|
||||
rtc0 = &rtc0;
|
||||
rtc1 = &snvs_rtc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart1;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
power-supply = <®_mba6ul_3v3>;
|
||||
enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
beeper: beeper {
|
||||
compatible = "gpio-beeper";
|
||||
gpios = <&expander_out1 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
gpio_buttons: gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_buttons>;
|
||||
|
||||
button1 {
|
||||
label = "s14";
|
||||
linux,code = <KEY_1>;
|
||||
gpios = <&expander_in0 0 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
button2 {
|
||||
label = "s6";
|
||||
linux,code = <KEY_2>;
|
||||
gpios = <&expander_in0 1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
button3 {
|
||||
label = "s7";
|
||||
linux,code = <KEY_3>;
|
||||
gpios = <&expander_in0 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
power-button {
|
||||
label = "POWER";
|
||||
linux,code = <KEY_POWER>;
|
||||
gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
status = "okay";
|
||||
|
||||
led1 {
|
||||
label = "led1";
|
||||
gpios = <&expander_out1 4 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
|
||||
led2 {
|
||||
label = "led2";
|
||||
gpios = <&expander_out1 5 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
reg_lcd_pwr: regulator-lcd-pwr {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "lcd-pwr";
|
||||
gpio = <&expander_out0 1 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
reg_mba6ul_3v3: regulator-mba6ul-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "supply-mba6ul-3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_mba6ul_5v0: regulator-mba6ul-5v0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "supply-mba6ul-5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_mpcie: regulator-mpcie-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "mpcie-3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&expander_out0 2 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
startup-delay-us = <500000>;
|
||||
vin-supply = <®_mba6ul_3v3>;
|
||||
};
|
||||
|
||||
reg_otg2vbus_5v0: regulator-otg2-vbus-5v0 {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&expander_out1 0 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-name = "otg2-vbus-supply-5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <®_mpcie>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
size = <0x6000000>;
|
||||
linux,cma-default;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx-audio-tlv320aic32x4";
|
||||
model = "imx-audio-tlv320aic32x4";
|
||||
ssi-controller = <&sai1>;
|
||||
audio-codec = <&tlv320aic32x4>;
|
||||
audio-asrc = <&asrc>;
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan1>;
|
||||
xceiver-supply = <®_mba6ul_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan2>;
|
||||
xceiver-supply = <®_mba6ul_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&clks {
|
||||
assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
|
||||
assigned-clock-rates = <768000000>;
|
||||
};
|
||||
|
||||
&ecspi2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi2>;
|
||||
num-cs = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet1>;
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <ðphy0>;
|
||||
phy-supply = <®_mba6ul_3v3>;
|
||||
phy-reset-gpios = <&expander_out1 1 GPIO_ACTIVE_LOW>;
|
||||
phy-reset-duration = <25>;
|
||||
phy-reset-post-delay = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_mdc>;
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <ðphy1>;
|
||||
phy-supply = <®_mba6ul_3v3>;
|
||||
phy-reset-gpios = <&expander_out1 2 GPIO_ACTIVE_LOW>;
|
||||
phy-reset-duration = <25>;
|
||||
phy-reset-post-delay = <1>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
clocks = <&clks IMX6UL_CLK_ENET_REF>;
|
||||
reg = <0>;
|
||||
max-speed = <100>;
|
||||
};
|
||||
|
||||
ethphy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>;
|
||||
reg = <1>;
|
||||
max-speed = <100>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
tlv320aic32x4: audio-codec@18 {
|
||||
compatible = "ti,tlv320aic32x4";
|
||||
reg = <0x18>;
|
||||
clocks = <&clks IMX6UL_CLK_SAI1>;
|
||||
clock-names = "mclk";
|
||||
ldoin-supply = <®_mba6ul_3v3>;
|
||||
iov-supply = <®_mba6ul_3v3>;
|
||||
};
|
||||
|
||||
jc42: temperature-sensor@19 {
|
||||
compatible = "nxp,se97", "jedec,jc-42.4-temp";
|
||||
reg = <0x19>;
|
||||
};
|
||||
|
||||
expander_out0: gpio-expander@20 {
|
||||
compatible = "nxp,pca9554";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
expander_in0: gpio-expander@21 {
|
||||
compatible = "nxp,pca9554";
|
||||
reg = <0x21>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_expander_in0>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
enet1_int-hog {
|
||||
gpio-hog;
|
||||
gpios = <6 0>;
|
||||
input;
|
||||
};
|
||||
|
||||
enet2_int-hog {
|
||||
gpio-hog;
|
||||
gpios = <7 0>;
|
||||
input;
|
||||
};
|
||||
};
|
||||
|
||||
expander_out1: gpio-expander@22 {
|
||||
compatible = "nxp,pca9554";
|
||||
reg = <0x22>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
analog_touch: touchscreen@41 {
|
||||
compatible = "st,stmpe811";
|
||||
reg = <0x41>;
|
||||
interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupt-controller;
|
||||
status = "disabled";
|
||||
|
||||
stmpe_touchscreen {
|
||||
compatible = "st,stmpe-ts";
|
||||
st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */
|
||||
st,ave-ctrl = <3>; /* 8 sample average control */
|
||||
st,fraction-z = <7>; /* 7 length fractional part in z */
|
||||
/*
|
||||
* 50 mA typical 80 mA max touchscreen drivers
|
||||
* current limit value
|
||||
*/
|
||||
st,i-drive = <1>;
|
||||
st,mod-12b = <1>; /* 12-bit ADC */
|
||||
st,ref-sel = <0>; /* internal ADC reference */
|
||||
st,sample-time = <4>; /* ADC converstion time: 80 clocks */
|
||||
st,settling = <3>; /* 1 ms panel driver settling time */
|
||||
st,touch-det-delay = <5>; /* 5 ms touch detect interrupt delay */
|
||||
};
|
||||
};
|
||||
|
||||
/* NXP SE97BTP with temperature sensor + eeprom */
|
||||
se97b: eeprom@51 {
|
||||
compatible = "nxp,se97b", "atmel,24c02";
|
||||
reg = <0x51>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sai1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sai1>;
|
||||
assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>,
|
||||
<&clks IMX6UL_CLK_SAI1>;
|
||||
assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
|
||||
assigned-clock-rates = <0>, <24000000>;
|
||||
fsl,sai-mclk-direction-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart6 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart6>;
|
||||
/* for DTE mode, add below change */
|
||||
/* fsl,dte-mode; */
|
||||
/* pinctrl-0 = <&pinctrl_uart6dte>; */
|
||||
uart-has-rtscts;
|
||||
linux,rs485-enabled-at-boot-time;
|
||||
rs485-rts-active-low;
|
||||
rs485-rx-during-tx;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* otg-port */
|
||||
&usbotg1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb_otg1>;
|
||||
power-active-high;
|
||||
over-current-active-low;
|
||||
/* we implement only dual role but not a fully featured OTG */
|
||||
hnp-disable;
|
||||
srp-disable;
|
||||
adp-disable;
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* 7-port usb hub */
|
||||
/* id, pwr, oc pins not connected */
|
||||
&usbotg2 {
|
||||
disable-over-current;
|
||||
vbus-supply = <®_otg2vbus_5v0>;
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <®_mba6ul_3v3>;
|
||||
vqmmc-supply = <®_vccsd>;
|
||||
no-1-8-v;
|
||||
no-mmc;
|
||||
no-sdio;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog1>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_buttons: buttonsgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x100b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi2: ecspi2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x1b020
|
||||
MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x1b020
|
||||
MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x1b020
|
||||
MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x1b020
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet1: enet1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
|
||||
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
|
||||
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
|
||||
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
|
||||
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
|
||||
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
|
||||
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
|
||||
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a8
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet2: enet2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
|
||||
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
|
||||
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
|
||||
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
|
||||
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0a0
|
||||
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0a0
|
||||
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
|
||||
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b0a8
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet2_mdc: enet2mdcgrp {
|
||||
fsl,pins = <
|
||||
/* mdio */
|
||||
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
|
||||
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_expander_in0: expanderin0grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan1: flexcan1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
|
||||
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan2: flexcan2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
|
||||
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm2: pwm2grp {
|
||||
fsl,pins = <
|
||||
/* 100 k PD, DSE 120 OHM, SPPEED LO */
|
||||
MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x00003050
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sai1: sai1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b1
|
||||
MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b1
|
||||
MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8
|
||||
MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0
|
||||
MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
|
||||
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
|
||||
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart6: uart6grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
|
||||
MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1
|
||||
MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1
|
||||
MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart6dte: uart6dte {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x1b0b1
|
||||
MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x1b0b1
|
||||
MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x1b0b1
|
||||
MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usb_otg1: usbotg1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x00017059
|
||||
MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0001b0b0
|
||||
MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x0001b099
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069
|
||||
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x00017059
|
||||
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x00017059
|
||||
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x00017059
|
||||
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x00017059
|
||||
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x00017059
|
||||
/* WP */
|
||||
MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099
|
||||
/* CD */
|
||||
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069
|
||||
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170b9
|
||||
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170b9
|
||||
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170b9
|
||||
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170b9
|
||||
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170b9
|
||||
/* WP */
|
||||
MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099
|
||||
/* CD */
|
||||
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069
|
||||
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170f9
|
||||
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170f9
|
||||
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170f9
|
||||
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170f9
|
||||
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170f9
|
||||
/* WP */
|
||||
MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099
|
||||
/* CD */
|
||||
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog1: wdog1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0001b099
|
||||
>;
|
||||
};
|
||||
};
|
94
arch/arm/boot/dts/overlays/arducam-64mp-overlay.dts
Normal file
94
arch/arm/boot/dts/overlays/arducam-64mp-overlay.dts
Normal file
@ -0,0 +1,94 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
// Definitions for Arducam 64MP camera module on VC I2C bus
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/{
|
||||
compatible = "brcm,bcm2835";
|
||||
|
||||
i2c_frag: fragment@0 {
|
||||
target = <&i2c_csi_dsi>;
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
arducam_64mp: arducam_64mp@1a {
|
||||
compatible = "arducam,64mp";
|
||||
reg = <0x1a>;
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cam1_clk>;
|
||||
clock-names = "xclk";
|
||||
|
||||
VANA-supply = <&cam1_reg>; /* 2.8v */
|
||||
VDIG-supply = <&cam_dummy_reg>; /* 1.8v */
|
||||
VDDL-supply = <&cam_dummy_reg>; /* 1.2v */
|
||||
|
||||
rotation = <0>;
|
||||
orientation = <2>;
|
||||
|
||||
port {
|
||||
arducam_64mp_0: endpoint {
|
||||
remote-endpoint = <&csi1_ep>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
clock-noncontinuous;
|
||||
link-frequencies =
|
||||
/bits/ 64 <456000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
csi_frag: fragment@1 {
|
||||
target = <&csi1>;
|
||||
csi: __overlay__ {
|
||||
status = "okay";
|
||||
brcm,media-controller;
|
||||
|
||||
port{
|
||||
csi1_ep: endpoint{
|
||||
remote-endpoint = <&arducam_64mp_0>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
clock-noncontinuous;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@2 {
|
||||
target = <&i2c0if>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
clk_frag: fragment@3 {
|
||||
target = <&cam1_clk>;
|
||||
__overlay__ {
|
||||
clock-frequency = <24000000>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@4 {
|
||||
target = <&i2c0mux>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
__overrides__ {
|
||||
rotation = <&arducam_64mp>,"rotation:0";
|
||||
orientation = <&arducam_64mp>,"orientation:0";
|
||||
media-controller = <&csi>,"brcm,media-controller?";
|
||||
cam0 = <&i2c_frag>, "target:0=",<&i2c_vc>,
|
||||
<&csi_frag>, "target:0=",<&csi0>,
|
||||
<&clk_frag>, "target:0=",<&cam0_clk>,
|
||||
<&arducam_64mp>, "clocks:0=",<&cam0_clk>,
|
||||
<&arducam_64mp>, "VANA-supply:0=",<&cam0_reg>;
|
||||
};
|
||||
};
|
94
arch/arm/boot/dts/overlays/arducam-pivariety-overlay.dts
Normal file
94
arch/arm/boot/dts/overlays/arducam-pivariety-overlay.dts
Normal file
@ -0,0 +1,94 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
// Definitions for Arducam Pivariety camera module on VC I2C bus
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/{
|
||||
compatible = "brcm,bcm2835";
|
||||
|
||||
i2c_frag: fragment@0 {
|
||||
target = <&i2c_csi_dsi>;
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
arducam_pivariety: arducam_pivariety@c {
|
||||
compatible = "arducam,arducam-pivariety";
|
||||
reg = <0x0c>;
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cam1_clk>;
|
||||
clock-names = "xclk";
|
||||
|
||||
VANA-supply = <&cam1_reg>; /* 2.8v */
|
||||
VDIG-supply = <&cam_dummy_reg>; /* 1.8v */
|
||||
VDDL-supply = <&cam_dummy_reg>; /* 1.2v */
|
||||
|
||||
rotation = <0>;
|
||||
orientation = <2>;
|
||||
|
||||
port {
|
||||
arducam_pivariety_0: endpoint {
|
||||
remote-endpoint = <&csi1_ep>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
clock-noncontinuous;
|
||||
link-frequencies =
|
||||
/bits/ 64 <493500000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
csi_frag: fragment@1 {
|
||||
target = <&csi1>;
|
||||
csi: __overlay__ {
|
||||
status = "okay";
|
||||
brcm,media-controller;
|
||||
|
||||
port{
|
||||
csi1_ep: endpoint{
|
||||
remote-endpoint = <&arducam_pivariety_0>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
clock-noncontinuous;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@2 {
|
||||
target = <&i2c0if>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
clk_frag: fragment@3 {
|
||||
target = <&cam1_clk>;
|
||||
__overlay__ {
|
||||
clock-frequency = <24000000>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@4 {
|
||||
target = <&i2c0mux>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
__overrides__ {
|
||||
rotation = <&arducam_pivariety>,"rotation:0";
|
||||
orientation = <&arducam_pivariety>,"orientation:0";
|
||||
media-controller = <&csi>,"brcm,media-controller?";
|
||||
cam0 = <&i2c_frag>, "target:0=",<&i2c_vc>,
|
||||
<&csi_frag>, "target:0=",<&csi0>,
|
||||
<&clk_frag>, "target:0=",<&cam0_clk>,
|
||||
<&arducam_pivariety>, "clocks:0=",<&cam0_clk>,
|
||||
<&arducam_pivariety>, "VANA-supply:0=",<&cam0_reg>;
|
||||
};
|
||||
};
|
409
arch/arm/boot/dts/overlays/camera-mux-2port-overlay.dts
Normal file
409
arch/arm/boot/dts/overlays/camera-mux-2port-overlay.dts
Normal file
@ -0,0 +1,409 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
// Overlay to configure a 2 port camera multiplexer
|
||||
//
|
||||
// Configuration is based on the Arducam Doubleplexer
|
||||
// which uses a PCA9543 I2C multiplexer to handle the
|
||||
// I2C, and GPIO 4 to control the MIPI mux, and GPIO 17
|
||||
// to enable the CSI-2 mux output (gpio-hog).
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/{
|
||||
compatible = "brcm,bcm2835";
|
||||
|
||||
/* Fragments that complete the individual sensor fragments */
|
||||
/* IMX290 */
|
||||
fragment@0 {
|
||||
target = <&imx290_0_ep>;
|
||||
__overlay__ {
|
||||
data-lanes = <1 2>;
|
||||
link-frequencies =
|
||||
/bits/ 64 <445500000 297000000>;
|
||||
};
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target = <&imx290_1_ep>;
|
||||
__overlay__ {
|
||||
data-lanes = <1 2>;
|
||||
link-frequencies =
|
||||
/bits/ 64 <445500000 297000000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* IMX477 */
|
||||
fragment@10 {
|
||||
target = <&imx477_0>;
|
||||
__overlay__ {
|
||||
compatible = "sony,imx477";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@11 {
|
||||
target = <&imx477_1>;
|
||||
__overlay__ {
|
||||
compatible = "sony,imx477";
|
||||
};
|
||||
};
|
||||
|
||||
/* Additional fragments affecting the mux nodes */
|
||||
fragment@100 {
|
||||
target = <&mux_in0>;
|
||||
__dormant__ {
|
||||
data-lanes = <1>;
|
||||
};
|
||||
};
|
||||
fragment@101 {
|
||||
target = <&mux_in0>;
|
||||
__overlay__ {
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
|
||||
fragment@102 {
|
||||
target = <&mux_in1>;
|
||||
__dormant__ {
|
||||
data-lanes = <1>;
|
||||
};
|
||||
};
|
||||
fragment@103 {
|
||||
target = <&mux_in1>;
|
||||
__overlay__ {
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Mux define */
|
||||
fragment@200 {
|
||||
target = <&i2c_csi_dsi>;
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
pca@70 {
|
||||
reg = <0x70>;
|
||||
compatible = "nxp,pca9543";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
#define cam_node imx219_0
|
||||
#define cam_endpoint imx219_0_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "imx219.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node imx477_0
|
||||
#define cam_endpoint imx477_0_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "imx477_378.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node ov5647_0
|
||||
#define cam_endpoint ov5647_0_ep
|
||||
#define cam1_clk clk_25mhz
|
||||
#include "ov5647.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node ov7251_0
|
||||
#define cam_endpoint ov7251_0_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "ov7251.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node ov9281_0
|
||||
#define cam_endpoint ov9281_0_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "ov9281.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node imx258_0
|
||||
#define cam_endpoint imx258_0_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "imx258.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node imx290_0
|
||||
#define cam_endpoint imx290_0_ep
|
||||
#define cam1_clk clk_imx290
|
||||
#include "imx290_327.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node ov2311_0
|
||||
#define cam_endpoint ov2311_0_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "ov2311.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
};
|
||||
|
||||
i2c@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
#define cam_node imx219_1
|
||||
#define cam_endpoint imx219_1_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "imx219.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node imx477_1
|
||||
#define cam_endpoint imx477_1_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "imx477_378.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node ov5647_1
|
||||
#define cam_endpoint ov5647_1_ep
|
||||
#define cam1_clk clk_25mhz
|
||||
#include "ov5647.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node ov7251_1
|
||||
#define cam_endpoint ov7251_1_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "ov7251.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node ov9281_1
|
||||
#define cam_endpoint ov9281_1_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "ov9281.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node imx258_1
|
||||
#define cam_endpoint imx258_1_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "imx258.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node imx290_1
|
||||
#define cam_endpoint imx290_1_ep
|
||||
#define cam1_clk clk_imx290
|
||||
#include "imx290_327.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node ov2311_1
|
||||
#define cam_endpoint ov2311_1_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "ov2311.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@201 {
|
||||
target = <&csi1>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
|
||||
brcm,media-controller;
|
||||
|
||||
port {
|
||||
csi1_ep: endpoint {
|
||||
remote-endpoint = <&mux_out>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@202 {
|
||||
target = <&i2c0if>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@203 {
|
||||
target-path="/";
|
||||
__overlay__ {
|
||||
mux: mux-controller {
|
||||
compatible = "gpio-mux";
|
||||
#mux-control-cells = <0>;
|
||||
|
||||
mux-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
video-mux {
|
||||
compatible = "video-mux";
|
||||
mux-controls = <&mux>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
mux_in0: endpoint {
|
||||
clock-lanes = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
mux_in1: endpoint {
|
||||
clock-lanes = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
mux_out: endpoint {
|
||||
remote-endpoint = <&csi1_ep>;
|
||||
clock-lanes = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
clk_24mhz: clk_24mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
|
||||
clock-frequency = <24000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
clk_25mhz: clk_25mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
|
||||
clock-frequency = <25000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
clk_imx290: clk_imx290 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
|
||||
clock-frequency = <37125000>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@204 {
|
||||
target = <&i2c0mux>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@205 {
|
||||
target = <&gpio>;
|
||||
__overlay__ {
|
||||
mipi_sw_oe_hog {
|
||||
gpio-hog;
|
||||
gpios = <17 GPIO_ACTIVE_LOW>;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
__overrides__ {
|
||||
cam0-imx219 = <&mux_in0>, "remote-endpoint:0=",<&imx219_0_ep>,
|
||||
<&imx219_0_ep>, "remote-endpoint:0=",<&mux_in0>,
|
||||
<&mux_in0>, "clock-noncontinuous?",
|
||||
<&imx219_0>, "status=okay";
|
||||
cam0-imx477 = <&mux_in0>, "remote-endpoint:0=",<&imx477_0_ep>,
|
||||
<&imx477_0_ep>, "remote-endpoint:0=",<&mux_in0>,
|
||||
<&mux_in0>, "clock-noncontinuous?",
|
||||
<&imx477_0>, "status=okay";
|
||||
cam0-ov5647 = <&mux_in0>, "remote-endpoint:0=",<&ov5647_0_ep>,
|
||||
<&ov5647_0_ep>, "remote-endpoint:0=",<&mux_in0>,
|
||||
<&ov5647_0>, "status=okay";
|
||||
cam0-ov7251 = <&mux_in0>, "remote-endpoint:0=",<&ov7251_0_ep>,
|
||||
<&ov7251_0_ep>, "remote-endpoint:0=",<&mux_in0>,
|
||||
<&ov7251_0>, "status=okay",
|
||||
<0>,"+100-101";
|
||||
cam0-ov9281 = <&mux_in0>, "remote-endpoint:0=",<&ov9281_0_ep>,
|
||||
<&ov9281_0_ep>, "remote-endpoint:0=",<&mux_in0>,
|
||||
<&ov9281_0>, "status=okay";
|
||||
cam0-imx258 = <&mux_in0>, "remote-endpoint:0=",<&imx258_0_ep>,
|
||||
<&imx258_0_ep>, "remote-endpoint:0=",<&mux_in0>,
|
||||
<&imx258_0>, "status=okay";
|
||||
cam0-imx290 = <&mux_in0>, "remote-endpoint:0=",<&imx290_0_ep>,
|
||||
<&imx290_0_ep>, "remote-endpoint:0=",<&mux_in0>,
|
||||
<&imx290_0>, "status=okay";
|
||||
cam0-ov2311 = <&mux_in0>, "remote-endpoint:0=",<&ov2311_0_ep>,
|
||||
<&ov2311_0_ep>, "remote-endpoint:0=",<&mux_in0>,
|
||||
<&ov2311_0>, "status=okay";
|
||||
|
||||
cam1-imx219 = <&mux_in1>, "remote-endpoint:0=",<&imx219_1_ep>,
|
||||
<&imx219_1_ep>, "remote-endpoint:0=",<&mux_in1>,
|
||||
<&mux_in1>, "clock-noncontinuous?",
|
||||
<&imx219_1>, "status=okay";
|
||||
cam1-imx477 = <&mux_in1>, "remote-endpoint:0=",<&imx477_1_ep>,
|
||||
<&imx477_1_ep>, "remote-endpoint:0=",<&mux_in1>,
|
||||
<&mux_in1>, "clock-noncontinuous?",
|
||||
<&imx477_1>, "status=okay";
|
||||
cam1-ov5647 = <&mux_in1>, "remote-endpoint:0=",<&ov5647_1_ep>,
|
||||
<&ov5647_1_ep>, "remote-endpoint:0=",<&mux_in1>,
|
||||
<&ov5647_1>, "status=okay";
|
||||
cam1-ov7251 = <&mux_in1>, "remote-endpoint:0=",<&ov7251_1_ep>,
|
||||
<&ov7251_1_ep>, "remote-endpoint:0=",<&mux_in1>,
|
||||
<&ov7251_1>, "status=okay",
|
||||
<0>,"+102-103";
|
||||
cam1-ov9281 = <&mux_in1>, "remote-endpoint:0=",<&ov9281_1_ep>,
|
||||
<&ov9281_1_ep>, "remote-endpoint:0=",<&mux_in1>,
|
||||
<&ov9281_1>, "status=okay";
|
||||
cam1-imx258 = <&mux_in1>, "remote-endpoint:0=",<&imx258_1_ep>,
|
||||
<&imx258_1_ep>, "remote-endpoint:0=",<&mux_in1>,
|
||||
<&imx258_1>, "status=okay";
|
||||
cam1-imx290 = <&mux_in1>, "remote-endpoint:0=",<&imx290_1_ep>,
|
||||
<&imx290_1_ep>, "remote-endpoint:0=",<&mux_in1>,
|
||||
<&imx290_1>, "status=okay";
|
||||
cam1-ov2311 = <&mux_in1>, "remote-endpoint:0=",<&ov2311_1_ep>,
|
||||
<&ov2311_1_ep>, "remote-endpoint:0=",<&mux_in1>,
|
||||
<&ov2311_1>, "status=okay";
|
||||
|
||||
cam0-imx290-clk-freq = <&clk_imx290>,"clock-frequency:0",
|
||||
<&imx290_0>,"clock-frequency:0";
|
||||
cam1-imx290-clk-freq = <&clk_imx290>,"clock-frequency:0",
|
||||
<&imx290_1>,"clock-frequency:0";
|
||||
};
|
||||
};
|
684
arch/arm/boot/dts/overlays/camera-mux-4port-overlay.dts
Normal file
684
arch/arm/boot/dts/overlays/camera-mux-4port-overlay.dts
Normal file
@ -0,0 +1,684 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
// Overlay to configure a 4 port camera multiplexer
|
||||
//
|
||||
// Configuration is based on the Arducam 4 channel multiplexer
|
||||
// which uses a PCA9543 I2C multiplexer to handle the
|
||||
// I2C, and GPIOs 4, 17, and 18 to control the MIPI muxes.
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/{
|
||||
compatible = "brcm,bcm2835";
|
||||
|
||||
/* Fragments that complete the individual sensor fragments */
|
||||
/* IMX290 */
|
||||
fragment@0 {
|
||||
target = <&imx290_0_ep>;
|
||||
__overlay__ {
|
||||
data-lanes = <1 2>;
|
||||
link-frequencies =
|
||||
/bits/ 64 <445500000 297000000>;
|
||||
};
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target = <&imx290_1_ep>;
|
||||
__overlay__ {
|
||||
data-lanes = <1 2>;
|
||||
link-frequencies =
|
||||
/bits/ 64 <445500000 297000000>;
|
||||
};
|
||||
};
|
||||
|
||||
fragment@2 {
|
||||
target = <&imx290_2_ep>;
|
||||
__overlay__ {
|
||||
data-lanes = <1 2>;
|
||||
link-frequencies =
|
||||
/bits/ 64 <445500000 297000000>;
|
||||
};
|
||||
};
|
||||
|
||||
fragment@3 {
|
||||
target = <&imx290_3_ep>;
|
||||
__overlay__ {
|
||||
data-lanes = <1 2>;
|
||||
link-frequencies =
|
||||
/bits/ 64 <445500000 297000000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* IMX477 */
|
||||
fragment@10 {
|
||||
target = <&imx477_0>;
|
||||
__overlay__ {
|
||||
compatible = "sony,imx477";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@11 {
|
||||
target = <&imx477_1>;
|
||||
__overlay__ {
|
||||
compatible = "sony,imx477";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@12 {
|
||||
target = <&imx477_2>;
|
||||
__overlay__ {
|
||||
compatible = "sony,imx477";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@13 {
|
||||
target = <&imx477_3>;
|
||||
__overlay__ {
|
||||
compatible = "sony,imx477";
|
||||
};
|
||||
};
|
||||
|
||||
/* Additional fragments affecting the mux nodes */
|
||||
fragment@100 {
|
||||
target = <&mux_in0>;
|
||||
__dormant__ {
|
||||
data-lanes = <1>;
|
||||
};
|
||||
};
|
||||
fragment@101 {
|
||||
target = <&mux_in0>;
|
||||
__overlay__ {
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
|
||||
fragment@102 {
|
||||
target = <&mux_in1>;
|
||||
__dormant__ {
|
||||
data-lanes = <1>;
|
||||
};
|
||||
};
|
||||
fragment@103 {
|
||||
target = <&mux_in1>;
|
||||
__overlay__ {
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
|
||||
fragment@104 {
|
||||
target = <&mux_in2>;
|
||||
__dormant__ {
|
||||
data-lanes = <1>;
|
||||
};
|
||||
};
|
||||
fragment@105 {
|
||||
target = <&mux_in2>;
|
||||
__overlay__ {
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
|
||||
fragment@106 {
|
||||
target = <&mux_in3>;
|
||||
__dormant__ {
|
||||
data-lanes = <1>;
|
||||
};
|
||||
};
|
||||
fragment@107 {
|
||||
target = <&mux_in3>;
|
||||
__overlay__ {
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Mux define */
|
||||
fragment@200 {
|
||||
target = <&i2c_csi_dsi>;
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
pca@70 {
|
||||
reg = <0x70>;
|
||||
compatible = "nxp,pca9544";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
#define cam_node imx219_0
|
||||
#define cam_endpoint imx219_0_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "imx219.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node imx477_0
|
||||
#define cam_endpoint imx477_0_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "imx477_378.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node ov5647_0
|
||||
#define cam_endpoint ov5647_0_ep
|
||||
#define cam1_clk clk_25mhz
|
||||
#include "ov5647.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node ov7251_0
|
||||
#define cam_endpoint ov7251_0_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "ov7251.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node ov9281_0
|
||||
#define cam_endpoint ov9281_0_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "ov9281.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node imx258_0
|
||||
#define cam_endpoint imx258_0_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "imx258.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node imx290_0
|
||||
#define cam_endpoint imx290_0_ep
|
||||
#define cam1_clk clk_imx290
|
||||
#include "imx290_327.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node ov2311_0
|
||||
#define cam_endpoint ov2311_0_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "ov2311.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
};
|
||||
|
||||
i2c@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
#define cam_node imx219_1
|
||||
#define cam_endpoint imx219_1_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "imx219.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node imx477_1
|
||||
#define cam_endpoint imx477_1_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "imx477_378.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node ov5647_1
|
||||
#define cam_endpoint ov5647_1_ep
|
||||
#define cam1_clk clk_25mhz
|
||||
#include "ov5647.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node ov7251_1
|
||||
#define cam_endpoint ov7251_1_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "ov7251.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node ov9281_1
|
||||
#define cam_endpoint ov9281_1_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "ov9281.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node imx258_1
|
||||
#define cam_endpoint imx258_1_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "imx258.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node imx290_1
|
||||
#define cam_endpoint imx290_1_ep
|
||||
#define cam1_clk clk_imx290
|
||||
#include "imx290_327.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node ov2311_1
|
||||
#define cam_endpoint ov2311_1_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "ov2311.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
reg = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
#define cam_node imx219_2
|
||||
#define cam_endpoint imx219_2_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "imx219.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node imx477_2
|
||||
#define cam_endpoint imx477_2_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "imx477_378.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node ov5647_2
|
||||
#define cam_endpoint ov5647_2_ep
|
||||
#define cam1_clk clk_25mhz
|
||||
#include "ov5647.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node ov7251_2
|
||||
#define cam_endpoint ov7251_2_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "ov7251.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node ov9281_2
|
||||
#define cam_endpoint ov9281_2_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "ov9281.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node imx258_2
|
||||
#define cam_endpoint imx258_2_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "imx258.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node imx290_2
|
||||
#define cam_endpoint imx290_2_ep
|
||||
#define cam1_clk clk_imx290
|
||||
#include "imx290_327.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node ov2311_2
|
||||
#define cam_endpoint ov2311_2_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "ov2311.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
reg = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
#define cam_node imx219_3
|
||||
#define cam_endpoint imx219_3_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "imx219.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node imx477_3
|
||||
#define cam_endpoint imx477_3_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "imx477_378.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node ov5647_3
|
||||
#define cam_endpoint ov5647_3_ep
|
||||
#define cam1_clk clk_25mhz
|
||||
#include "ov5647.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node ov7251_3
|
||||
#define cam_endpoint ov7251_3_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "ov7251.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node ov9281_3
|
||||
#define cam_endpoint ov9281_3_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "ov9281.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node imx258_3
|
||||
#define cam_endpoint imx258_3_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "imx258.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node imx290_3
|
||||
#define cam_endpoint imx290_3_ep
|
||||
#define cam1_clk clk_imx290
|
||||
#include "imx290_327.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
|
||||
#define cam_node ov2311_3
|
||||
#define cam_endpoint ov2311_3_ep
|
||||
#define cam1_clk clk_24mhz
|
||||
#include "ov2311.dtsi"
|
||||
#undef cam_node
|
||||
#undef cam_endpoint
|
||||
#undef cam1_clk
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@201 {
|
||||
target = <&csi1>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
|
||||
brcm,media-controller;
|
||||
|
||||
port {
|
||||
csi1_ep: endpoint {
|
||||
remote-endpoint = <&mux_out>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@202 {
|
||||
target = <&i2c0if>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@203 {
|
||||
target-path="/";
|
||||
__overlay__ {
|
||||
mux: mux-controller {
|
||||
compatible = "gpio-mux";
|
||||
#mux-control-cells = <0>;
|
||||
|
||||
/* SEL, En2, En1 */
|
||||
mux-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>,
|
||||
<&gpio 18 GPIO_ACTIVE_HIGH>,
|
||||
<&gpio 17 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
video-mux {
|
||||
compatible = "video-mux";
|
||||
mux-controls = <&mux>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* GPIO mappings settings for selecting the different
|
||||
* camera connectors are not direct, hence port@ values
|
||||
* are not straight forward.
|
||||
*/
|
||||
port@2 {
|
||||
/* Port A - GPIO 17 = 0, GPIO 18 = 1,GPIO 4 = 0 */
|
||||
reg = <2>;
|
||||
|
||||
mux_in0: endpoint {
|
||||
clock-lanes = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@3 {
|
||||
/* Port B - GPIO 17 = 0, GPIO 18 = 1,GPIO 4 = 1 */
|
||||
reg = <3>;
|
||||
|
||||
mux_in1: endpoint {
|
||||
clock-lanes = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@4 {
|
||||
/* Port C - GPIO 17 = 1, GPIO 18 = 0, GPIO 4 = 0 */
|
||||
reg = <4>;
|
||||
|
||||
mux_in2: endpoint {
|
||||
clock-lanes = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@5 {
|
||||
/* Port D - GPIO 17 = 1, GPIO 18 = 0, GPIO 4 = 1 */
|
||||
reg = <5>;
|
||||
|
||||
mux_in3: endpoint {
|
||||
clock-lanes = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@6 {
|
||||
/* Output port needs to be the highest port number */
|
||||
reg = <6>;
|
||||
|
||||
mux_out: endpoint {
|
||||
remote-endpoint = <&csi1_ep>;
|
||||
clock-lanes = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
clk_24mhz: clk_24mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
|
||||
clock-frequency = <24000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
clk_25mhz: clk_25mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
|
||||
clock-frequency = <25000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
clk_imx290: clk_imx290 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
|
||||
clock-frequency = <37125000>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@204 {
|
||||
target = <&i2c0mux>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
__overrides__ {
|
||||
cam0-imx219 = <&mux_in0>, "remote-endpoint:0=",<&imx219_0_ep>,
|
||||
<&imx219_0_ep>, "remote-endpoint:0=",<&mux_in0>,
|
||||
<&mux_in0>, "clock-noncontinuous?",
|
||||
<&imx219_0>, "status=okay";
|
||||
cam0-imx477 = <&mux_in0>, "remote-endpoint:0=",<&imx477_0_ep>,
|
||||
<&imx477_0_ep>, "remote-endpoint:0=",<&mux_in0>,
|
||||
<&mux_in0>, "clock-noncontinuous?",
|
||||
<&imx477_0>, "status=okay";
|
||||
cam0-ov5647 = <&mux_in0>, "remote-endpoint:0=",<&ov5647_0_ep>,
|
||||
<&ov5647_0_ep>, "remote-endpoint:0=",<&mux_in0>,
|
||||
<&ov5647_0>, "status=okay";
|
||||
cam0-ov7251 = <&mux_in0>, "remote-endpoint:0=",<&ov7251_0_ep>,
|
||||
<&ov7251_0_ep>, "remote-endpoint:0=",<&mux_in0>,
|
||||
<&ov7251_0>, "status=okay",
|
||||
<0>,"+100-101";
|
||||
cam0-ov9281 = <&mux_in0>, "remote-endpoint:0=",<&ov9281_0_ep>,
|
||||
<&ov9281_0_ep>, "remote-endpoint:0=",<&mux_in0>,
|
||||
<&ov9281_0>, "status=okay";
|
||||
cam0-imx258 = <&mux_in0>, "remote-endpoint:0=",<&imx258_0_ep>,
|
||||
<&imx258_0_ep>, "remote-endpoint:0=",<&mux_in0>,
|
||||
<&imx258_0>, "status=okay";
|
||||
cam0-imx290 = <&mux_in0>, "remote-endpoint:0=",<&imx290_0_ep>,
|
||||
<&imx290_0_ep>, "remote-endpoint:0=",<&mux_in0>,
|
||||
<&imx290_0>, "status=okay";
|
||||
cam0-ov2311 = <&mux_in0>, "remote-endpoint:0=",<&ov2311_0_ep>,
|
||||
<&ov2311_0_ep>, "remote-endpoint:0=",<&mux_in0>,
|
||||
<&ov2311_0>, "status=okay";
|
||||
|
||||
cam1-imx219 = <&mux_in1>, "remote-endpoint:0=",<&imx219_1_ep>,
|
||||
<&imx219_1_ep>, "remote-endpoint:0=",<&mux_in1>,
|
||||
<&mux_in1>, "clock-noncontinuous?",
|
||||
<&imx219_1>, "status=okay";
|
||||
cam1-imx477 = <&mux_in1>, "remote-endpoint:0=",<&imx477_1_ep>,
|
||||
<&imx477_1_ep>, "remote-endpoint:0=",<&mux_in1>,
|
||||
<&mux_in1>, "clock-noncontinuous?",
|
||||
<&imx477_1>, "status=okay";
|
||||
cam1-ov5647 = <&mux_in1>, "remote-endpoint:0=",<&ov5647_1_ep>,
|
||||
<&ov5647_1_ep>, "remote-endpoint:0=",<&mux_in1>,
|
||||
<&ov5647_1>, "status=okay";
|
||||
cam1-ov7251 = <&mux_in1>, "remote-endpoint:0=",<&ov7251_1_ep>,
|
||||
<&ov7251_1_ep>, "remote-endpoint:0=",<&mux_in1>,
|
||||
<&ov7251_1>, "status=okay",
|
||||
<0>,"+102-103";
|
||||
cam1-ov9281 = <&mux_in1>, "remote-endpoint:0=",<&ov9281_1_ep>,
|
||||
<&ov9281_1_ep>, "remote-endpoint:0=",<&mux_in1>,
|
||||
<&ov9281_1>, "status=okay";
|
||||
cam1-imx258 = <&mux_in1>, "remote-endpoint:0=",<&imx258_1_ep>,
|
||||
<&imx258_1_ep>, "remote-endpoint:0=",<&mux_in1>,
|
||||
<&imx258_1>, "status=okay";
|
||||
cam1-imx290 = <&mux_in1>, "remote-endpoint:0=",<&imx290_1_ep>,
|
||||
<&imx290_1_ep>, "remote-endpoint:0=",<&mux_in1>,
|
||||
<&imx290_1>, "status=okay";
|
||||
cam1-ov2311 = <&mux_in1>, "remote-endpoint:0=",<&ov2311_1_ep>,
|
||||
<&ov2311_1_ep>, "remote-endpoint:0=",<&mux_in1>,
|
||||
<&ov2311_1>, "status=okay";
|
||||
|
||||
cam2-imx219 = <&mux_in2>, "remote-endpoint:0=",<&imx219_2_ep>,
|
||||
<&imx219_2_ep>, "remote-endpoint:0=",<&mux_in2>,
|
||||
<&mux_in2>, "clock-noncontinuous?",
|
||||
<&imx219_2>, "status=okay";
|
||||
cam2-imx477 = <&mux_in2>, "remote-endpoint:0=",<&imx477_2_ep>,
|
||||
<&imx477_2_ep>, "remote-endpoint:0=",<&mux_in2>,
|
||||
<&mux_in2>, "clock-noncontinuous?",
|
||||
<&imx477_2>, "status=okay";
|
||||
cam2-ov5647 = <&mux_in2>, "remote-endpoint:0=",<&ov5647_2_ep>,
|
||||
<&ov5647_2_ep>, "remote-endpoint:0=",<&mux_in2>,
|
||||
<&ov5647_2>, "status=okay";
|
||||
cam2-ov7251 = <&mux_in2>, "remote-endpoint:0=",<&ov7251_2_ep>,
|
||||
<&ov7251_2_ep>, "remote-endpoint:0=",<&mux_in2>,
|
||||
<&ov7251_2>, "status=okay",
|
||||
<0>,"+104-105";
|
||||
cam2-ov9281 = <&mux_in2>, "remote-endpoint:0=",<&ov9281_2_ep>,
|
||||
<&ov9281_2_ep>, "remote-endpoint:0=",<&mux_in2>,
|
||||
<&ov9281_2>, "status=okay";
|
||||
cam2-imx258 = <&mux_in2>, "remote-endpoint:0=",<&imx258_2_ep>,
|
||||
<&imx258_2>, "status=okay",
|
||||
<&imx258_2>, "remote-endpoint:0=",<&mux_in2>;
|
||||
cam2-imx290 = <&mux_in2>, "remote-endpoint:0=",<&imx290_2_ep>,
|
||||
<&imx290_2_ep>, "remote-endpoint:0=",<&mux_in2>,
|
||||
<&imx290_2>, "status=okay";
|
||||
cam2-ov2311 = <&mux_in2>, "remote-endpoint:0=",<&ov2311_2_ep>,
|
||||
<&ov2311_2_ep>, "remote-endpoint:0=",<&mux_in2>,
|
||||
<&ov2311_2>, "status=okay";
|
||||
|
||||
cam3-imx219 = <&mux_in3>, "remote-endpoint:0=",<&imx219_3_ep>,
|
||||
<&imx219_3_ep>, "remote-endpoint:0=",<&mux_in3>,
|
||||
<&mux_in3>, "clock-noncontinuous?",
|
||||
<&imx219_3>, "status=okay";
|
||||
cam3-imx477 = <&mux_in3>, "remote-endpoint:0=",<&imx477_3_ep>,
|
||||
<&imx477_3_ep>, "remote-endpoint:0=",<&mux_in3>,
|
||||
<&mux_in3>, "clock-noncontinuous?",
|
||||
<&imx477_3>, "status=okay";
|
||||
cam3-ov5647 = <&mux_in3>, "remote-endpoint:0=",<&ov5647_3_ep>,
|
||||
<&ov5647_3_ep>, "remote-endpoint:0=",<&mux_in3>,
|
||||
<&ov5647_3>, "status=okay";
|
||||
cam3-ov7251 = <&mux_in3>, "remote-endpoint:0=",<&ov7251_3_ep>,
|
||||
<&ov7251_3_ep>, "remote-endpoint:0=",<&mux_in3>,
|
||||
<&ov7251_3>, "status=okay",
|
||||
<0>,"+106-107";
|
||||
cam3-ov9281 = <&mux_in3>, "remote-endpoint:0=",<&ov9281_3_ep>,
|
||||
<&ov9281_3_ep>, "remote-endpoint:0=",<&mux_in3>,
|
||||
<&ov9281_3>, "status=okay";
|
||||
cam3-imx258 = <&mux_in3>, "remote-endpoint:0=",<&imx258_3_ep>,
|
||||
<&imx258_3_ep>, "remote-endpoint:0=",<&mux_in3>,
|
||||
<&imx258_3>, "status=okay";
|
||||
cam3-imx290 = <&mux_in3>, "remote-endpoint:0=",<&imx290_3_ep>,
|
||||
<&imx290_3_ep>, "remote-endpoint:0=",<&mux_in3>,
|
||||
<&imx290_3>, "status=okay";
|
||||
cam3-ov2311 = <&mux_in3>, "remote-endpoint:0=",<&ov2311_3_ep>,
|
||||
<&ov2311_3_ep>, "remote-endpoint:0=",<&mux_in3>,
|
||||
<&ov2311_3>, "status=okay";
|
||||
|
||||
cam0-imx290-clk-freq = <&clk_imx290>,"clock-frequency:0",
|
||||
<&imx290_0>,"clock-frequency:0";
|
||||
cam1-imx290-clk-freq = <&clk_imx290>,"clock-frequency:0",
|
||||
<&imx290_1>,"clock-frequency:0";
|
||||
cam2-imx290-clk-freq = <&clk_imx290>,"clock-frequency:0",
|
||||
<&imx290_2>,"clock-frequency:0";
|
||||
cam3-imx290-clk-freq = <&clk_imx290>,"clock-frequency:0",
|
||||
<&imx290_3>,"clock-frequency:0";
|
||||
};
|
||||
};
|
172
arch/arm/boot/dts/overlays/cirrus-wm5102-overlay.dts
Normal file
172
arch/arm/boot/dts/overlays/cirrus-wm5102-overlay.dts
Normal file
@ -0,0 +1,172 @@
|
||||
// Definitions for the Cirrus Logic Audio Card
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
#include <dt-bindings/pinctrl/bcm2835.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/mfd/arizona.h>
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm2835";
|
||||
|
||||
fragment@0 {
|
||||
target = <&i2s>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target = <&gpio>;
|
||||
__overlay__ {
|
||||
wlf_5102_pins: wlf_5102_pins {
|
||||
brcm,pins = <17 22 27>;
|
||||
brcm,function = <
|
||||
BCM2835_FSEL_GPIO_OUT
|
||||
BCM2835_FSEL_GPIO_OUT
|
||||
BCM2835_FSEL_GPIO_IN
|
||||
>;
|
||||
};
|
||||
wlf_8804_pins: wlf_8804_pins {
|
||||
brcm,pins = <8>;
|
||||
brcm,function = <BCM2835_FSEL_GPIO_OUT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@2 {
|
||||
target = <&spi0_cs_pins>;
|
||||
__overlay__ {
|
||||
brcm,pins = <7>;
|
||||
brcm,function = <BCM2835_FSEL_GPIO_OUT>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
fragment@3 {
|
||||
target-path = "/";
|
||||
__overlay__ {
|
||||
rpi_cirrus_reg_1v8: rpi_cirrus_reg_1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "RPi-Cirrus 1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@4 {
|
||||
target = <&spidev0>;
|
||||
__overlay__ {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@5 {
|
||||
target = <&spidev1>;
|
||||
__overlay__ {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@6 {
|
||||
target = <&spi0>;
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
cs-gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
|
||||
|
||||
wm5102@0{
|
||||
compatible = "wlf,wm5102";
|
||||
reg = <0>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wlf_5102_pins>;
|
||||
|
||||
spi-max-frequency = <500000>;
|
||||
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <27 8>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
LDOVDD-supply = <&rpi_cirrus_reg_1v8>;
|
||||
AVDD-supply = <&rpi_cirrus_reg_1v8>;
|
||||
DBVDD1-supply = <&rpi_cirrus_reg_1v8>;
|
||||
DBVDD2-supply = <&vdd_3v3_reg>;
|
||||
DBVDD3-supply = <&vdd_3v3_reg>;
|
||||
CPVDD-supply = <&rpi_cirrus_reg_1v8>;
|
||||
SPKVDDL-supply = <&vdd_5v0_reg>;
|
||||
SPKVDDR-supply = <&vdd_5v0_reg>;
|
||||
DCVDD-supply = <&arizona_ldo1>;
|
||||
|
||||
reset-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
|
||||
wlf,ldoena = <&gpio 22 GPIO_ACTIVE_HIGH>;
|
||||
wlf,gpio-defaults = <
|
||||
ARIZONA_GP_DEFAULT
|
||||
ARIZONA_GP_DEFAULT
|
||||
ARIZONA_GP_DEFAULT
|
||||
ARIZONA_GP_DEFAULT
|
||||
ARIZONA_GP_DEFAULT
|
||||
>;
|
||||
wlf,micd-configs = <0 1 0>;
|
||||
wlf,dmic-ref = <
|
||||
ARIZONA_DMIC_MICVDD
|
||||
ARIZONA_DMIC_MICBIAS2
|
||||
ARIZONA_DMIC_MICVDD
|
||||
ARIZONA_DMIC_MICVDD
|
||||
>;
|
||||
wlf,inmode = <
|
||||
ARIZONA_INMODE_DIFF
|
||||
ARIZONA_INMODE_DMIC
|
||||
ARIZONA_INMODE_SE
|
||||
ARIZONA_INMODE_DIFF
|
||||
>;
|
||||
status = "okay";
|
||||
|
||||
arizona_ldo1: ldo1 {
|
||||
regulator-name = "LDO1";
|
||||
// default constraints as in
|
||||
// arizona-ldo1.c
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@7 {
|
||||
target = <&i2c1>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
wm8804@3b {
|
||||
compatible = "wlf,wm8804";
|
||||
reg = <0x3b>;
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wlf_8804_pins>;
|
||||
|
||||
PVDD-supply = <&vdd_3v3_reg>;
|
||||
DVDD-supply = <&vdd_3v3_reg>;
|
||||
wlf,reset-gpio = <&gpio 8 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@8 {
|
||||
target = <&sound>;
|
||||
__overlay__ {
|
||||
compatible = "wlf,rpi-cirrus";
|
||||
i2s-controller = <&i2s>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
71
arch/arm/boot/dts/overlays/dacberry400-overlay.dts
Normal file
71
arch/arm/boot/dts/overlays/dacberry400-overlay.dts
Normal file
@ -0,0 +1,71 @@
|
||||
// Definitions for DACberry400
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
/ {
|
||||
compatible = "brcm,bcm2835";
|
||||
|
||||
fragment@0 {
|
||||
target = <&i2s>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target-path = "/";
|
||||
__overlay__ {
|
||||
codec_1v8_reg: codec-1v8-reg {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "tlv320aic3104_1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@2 {
|
||||
target = <&gpio>;
|
||||
__overlay__ {
|
||||
codec_rst: codec-rst {
|
||||
brcm,pins = <26>;
|
||||
brcm,function = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@3 {
|
||||
target = <&i2c1>;
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
tlv320aic3104@18 {
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x18>;
|
||||
|
||||
compatible = "ti,tlv320aic3x";
|
||||
AVDD-supply = <&vdd_3v3_reg>;
|
||||
DRVDD-supply = <&vdd_3v3_reg>;
|
||||
DVDD-supply = <&codec_1v8_reg>;
|
||||
IOVDD-supply = <&codec_1v8_reg>;
|
||||
|
||||
gpio-controller;
|
||||
reset-gpios = <&gpio 26 1>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@4 {
|
||||
target = <&sound>;
|
||||
__overlay__ {
|
||||
compatible = "osaelectronics,dacberry400";
|
||||
i2s-controller = <&i2s>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
39
arch/arm/boot/dts/overlays/dionaudio-kiwi-overlay.dts
Normal file
39
arch/arm/boot/dts/overlays/dionaudio-kiwi-overlay.dts
Normal file
@ -0,0 +1,39 @@
|
||||
// Definitions for Dion Audio KIWI streamer
|
||||
|
||||
/*
|
||||
* PCM1794 DAC (in hardware mode).
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm2835";
|
||||
|
||||
fragment@0 {
|
||||
target = <&i2s>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target-path = "/";
|
||||
__overlay__ {
|
||||
pcm1794a-codec {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "ti,pcm1794a";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@2 {
|
||||
target = <&sound>;
|
||||
__overlay__ {
|
||||
compatible = "dionaudio,dionaudio-kiwi";
|
||||
i2s-controller = <&i2s>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
151
arch/arm/boot/dts/overlays/gc9a01-overlay.dts
Normal file
151
arch/arm/boot/dts/overlays/gc9a01-overlay.dts
Normal file
@ -0,0 +1,151 @@
|
||||
/*
|
||||
Device Tree overlay for Galaxycore GC9A01A single chip driver
|
||||
for use on SPI TFT LCD, 240x240 65K RGB
|
||||
Based on Galaxycore's GC9A01A datasheet Rev.1.0 (2019/07/02)
|
||||
Copyright (C) 2022, Julianno F. C. Silva (@juliannojungle)
|
||||
|
||||
This program is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU Affero General Public License as published
|
||||
by the Free Software Foundation, either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU Affero General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Affero General Public License
|
||||
along with this program. If not, see <https://www.gnu.org/licenses/agpl-3.0.html>.
|
||||
|
||||
Init sequence partially based on Waveshare team's Arduino LCD_Driver V1.0 (2020/12/09).
|
||||
|
||||
Permission is hereby granted, free of UBYTEge, to any person obtaining a copy
|
||||
of this software and associated documnetation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm2835";
|
||||
|
||||
fragment@0 {
|
||||
target = <&spidev0>;
|
||||
__overlay__ {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target = <&gpio>;
|
||||
__overlay__ {
|
||||
gc9a01_pins: gc9a01_pins {
|
||||
brcm,pins = <25 27>;
|
||||
brcm,function = <1 1>; /* out */
|
||||
brcm,pull = <0 0>; /* none */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@2 {
|
||||
target = <&spi0>;
|
||||
__overlay__ {
|
||||
/* needed to avoid dtc warning */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
gc9a01: gc9a01@0 {
|
||||
compatible = "ilitek,ili9340";
|
||||
reg = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gc9a01_pins>;
|
||||
reset-gpios = <&gpio 27 1>;
|
||||
dc-gpios = <&gpio 25 0>;
|
||||
led-gpios = <&gpio 18 0>;
|
||||
spi-max-frequency = <40000000>;
|
||||
buswidth = <8>;
|
||||
width = <240>;
|
||||
height = <240>;
|
||||
rotate = <0>;
|
||||
fps = <50>;
|
||||
bgr;
|
||||
debug = <0>;
|
||||
init = <
|
||||
0x01000011 /* Sleep mode OFF */
|
||||
0x02000078 /* Delay 120ms */
|
||||
0x010000EF /* Inter register enable 2 */
|
||||
0x010000EB 0x14
|
||||
/* BEGIN set inter_command HIGH */
|
||||
0x010000FE /* Inter register enable 1 */
|
||||
0x010000EF /* Inter register enable 2 */
|
||||
/* END set inter_command HIGH */
|
||||
0x010000EB 0x14
|
||||
0x01000084 0x40
|
||||
0x01000085 0xFF
|
||||
0x01000086 0xFF
|
||||
0x01000087 0xFF
|
||||
0x01000088 0x0A
|
||||
0x01000089 0x21
|
||||
0x0100008A 0x00
|
||||
0x0100008B 0x80
|
||||
0x0100008C 0x01
|
||||
0x0100008D 0x01
|
||||
0x0100008E 0xFF
|
||||
0x0100008F 0xFF
|
||||
0x010000B6 0x00 0x00 /* Display function control */
|
||||
0x01000036 0x08 /* Memory access control */
|
||||
0x0100003A 0x05 /* Pixel format */
|
||||
0x01000090 0x08 0x08 0x08 0x08
|
||||
0x010000BD 0x06
|
||||
0x010000BC 0x00
|
||||
0x010000FF 0x60 0x01 0x04
|
||||
0x010000C3 0x13 /* Voltage regulator 1a */
|
||||
0x010000C4 0x13 /* Voltage regulator 1b */
|
||||
0x010000C9 0x22 /* Voltage regulator 2a */
|
||||
0x010000BE 0x11
|
||||
0x010000E1 0x10 0x0E
|
||||
0x010000DF 0x21 0x0c 0x02
|
||||
0x010000F0 0x45 0x09 0x08 0x08 0x26 0x2A /* Set gamma1 */
|
||||
0x010000F1 0x43 0x70 0x72 0x36 0x37 0x6F /* Set gamma2 */
|
||||
0x010000F2 0x45 0x09 0x08 0x08 0x26 0x2A /* Set gamma3 */
|
||||
0x010000F3 0x43 0x70 0x72 0x36 0x37 0x6F /* Set gamma4 */
|
||||
0x010000ED 0x1B 0x0B
|
||||
0x010000AE 0x77
|
||||
0x010000CD 0x63
|
||||
0x01000070 0x07 0x07 0x04 0x0E 0x0F 0x09 0x07 0x08 0x03
|
||||
0x010000E8 0x34 /* Frame rate */
|
||||
0x01000062 0x18 0x0D 0x71 0xED 0x70 0x70 0x18 0x0F 0x71 0xEF 0x70 0x70
|
||||
0x01000063 0x18 0x11 0x71 0xF1 0x70 0x70 0x18 0x13 0x71 0xF3 0x70 0x70
|
||||
0x01000064 0x28 0x29 0xF1 0x01 0xF1 0x00 0x07
|
||||
0x01000066 0x3C 0x00 0xCD 0x67 0x45 0x45 0x10 0x00 0x00 0x00
|
||||
0x01000067 0x00 0x3C 0x00 0x00 0x00 0x01 0x54 0x10 0x32 0x98
|
||||
0x01000074 0x10 0x85 0x80 0x00 0x00 0x4E 0x00
|
||||
0x01000098 0x3e 0x07
|
||||
0x01000035 /* Tearing effect ON */
|
||||
0x01000021 /* Display inversion ON */
|
||||
0x01000011 /* Sleep mode OFF */
|
||||
0x0200000C /* Delay 12ms */
|
||||
0x01000029 /* Display ON */
|
||||
0x02000014 /* Delay 20ms */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
__overrides__ {
|
||||
speed = <&gc9a01>,"spi-max-frequency:0";
|
||||
rotate = <&gc9a01>,"rotate:0";
|
||||
width = <&gc9a01>,"width:0";
|
||||
height = <&gc9a01>,"height:0";
|
||||
fps = <&gc9a01>,"fps:0";
|
||||
debug = <&gc9a01>,"debug:0";
|
||||
};
|
||||
};
|
27
arch/arm/boot/dts/overlays/gpio-hog-overlay.dts
Normal file
27
arch/arm/boot/dts/overlays/gpio-hog-overlay.dts
Normal file
@ -0,0 +1,27 @@
|
||||
// Configure a "hog" on the specified GPIO
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm2835";
|
||||
|
||||
fragment@0 {
|
||||
target = <&gpio>;
|
||||
__overlay__ {
|
||||
hog: hog@1a {
|
||||
gpio-hog;
|
||||
gpios = <26 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
__overrides__ {
|
||||
gpio = <&hog>,"reg:0",
|
||||
<&hog>,"gpios:0";
|
||||
active_low = <&hog>,"output-high!",
|
||||
<&hog>,"output-low?";
|
||||
};
|
||||
};
|
57
arch/arm/boot/dts/overlays/hifiberry-amp3-overlay.dts
Normal file
57
arch/arm/boot/dts/overlays/hifiberry-amp3-overlay.dts
Normal file
@ -0,0 +1,57 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
// Definitions for HiFiBerry's Amp3
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
#include <dt-bindings/pinctrl/bcm2835.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm2835";
|
||||
|
||||
fragment@0 {
|
||||
target = <&i2s>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target = <&gpio>;
|
||||
__overlay__ {
|
||||
hifiberry_amp3_pins: hifiberry_amp3_pins {
|
||||
brcm,pins = <23 17>;
|
||||
brcm,function = <0 1>;
|
||||
brcm,pull = <2 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@2 {
|
||||
target = <&i2c1>;
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
hifiberry_amp2: ma120x0p@20 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "ma,ma120x0p";
|
||||
reg = <0x20>;
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hifiberry_amp3_pins>;
|
||||
error_gp-gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@3 {
|
||||
target = <&sound>;
|
||||
__overlay__ {
|
||||
compatible = "hifiberry,hifiberry-amp3";
|
||||
i2s-controller = <&i2s>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
108
arch/arm/boot/dts/overlays/i2c-fan-overlay.dts
Normal file
108
arch/arm/boot/dts/overlays/i2c-fan-overlay.dts
Normal file
@ -0,0 +1,108 @@
|
||||
// Definitions for I2C based sensors using the Industrial IO or HWMON interface.
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm2835";
|
||||
|
||||
fragment@0 {
|
||||
target = <&i2cbus>;
|
||||
__dormant__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
emc2301: emc2301@2f {
|
||||
compatible = "microchip,emc2301";
|
||||
reg = <0x2f>;
|
||||
status = "okay";
|
||||
#cooling-cells = <0x02>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
frag100: fragment@100 {
|
||||
target = <&i2c_arm>;
|
||||
i2cbus: __overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@101 {
|
||||
target = <&i2c0if>;
|
||||
__dormant__ {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@102 {
|
||||
target = <&i2c0mux>;
|
||||
__dormant__ {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@103 {
|
||||
target = <&cpu_thermal>;
|
||||
__overlay__ {
|
||||
polling-delay = <2000>; /* milliseconds */
|
||||
};
|
||||
};
|
||||
|
||||
fragment@104 {
|
||||
target = <&thermal_trips>;
|
||||
__overlay__ {
|
||||
fanmid0: fanmid0 {
|
||||
temperature = <50000>;
|
||||
hysteresis = <2000>;
|
||||
type = "active";
|
||||
};
|
||||
fanmax0: fanmax0 {
|
||||
temperature = <75000>;
|
||||
hysteresis = <2000>;
|
||||
type = "active";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@105 {
|
||||
target = <&cooling_maps>;
|
||||
__overlay__ {
|
||||
map0: map0 {
|
||||
trip = <&fanmid0>;
|
||||
cooling-device = <&emc2301 2 6>;
|
||||
};
|
||||
map1: map1 {
|
||||
trip = <&fanmax0>;
|
||||
cooling-device = <&emc2301 7 THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
__overrides__ {
|
||||
i2c0 = <&frag100>,"target:0=",<&i2c0>;
|
||||
i2c_csi_dsi = <&frag100>,"target:0=",<&i2c_csi_dsi>,
|
||||
<0>,"+101+102";
|
||||
i2c3 = <&frag100>, "target?=0",
|
||||
<&frag100>, "target-path=i2c3";
|
||||
i2c4 = <&frag100>, "target?=0",
|
||||
<&frag100>, "target-path=i2c4";
|
||||
i2c5 = <&frag100>, "target?=0",
|
||||
<&frag100>, "target-path=i2c5";
|
||||
i2c6 = <&frag100>, "target?=0",
|
||||
<&frag100>, "target-path=i2c6";
|
||||
addr = <&emc2301>,"reg:0";
|
||||
minpwm = <&emc2301>,"emc2305,pwm-min;0";
|
||||
maxpwm = <&emc2301>,"emc2305,pwm-max;0";
|
||||
midtemp = <&fanmid0>,"temperature:0";
|
||||
midtemp_hyst = <&fanmid0>,"hysteresis:0";
|
||||
maxtemp = <&fanmax0>,"temperature:0";
|
||||
maxtemp_hyst = <&fanmax0>,"hysteresis:0";
|
||||
|
||||
emc2301 = <0>,"+0",
|
||||
<&map0>,"cooling-device:0=",<&emc2301>,
|
||||
<&map1>,"cooling-device:0=",<&emc2301>;
|
||||
};
|
||||
};
|
341
arch/arm/boot/dts/overlays/i2c-sensor-common.dtsi
Normal file
341
arch/arm/boot/dts/overlays/i2c-sensor-common.dtsi
Normal file
@ -0,0 +1,341 @@
|
||||
// Definitions for I2C based sensors using the Industrial IO or HWMON interface.
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm2835";
|
||||
|
||||
fragment@0 {
|
||||
target = <&i2cbus>;
|
||||
__dormant__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
bme280: bme280@76 {
|
||||
compatible = "bosch,bme280";
|
||||
reg = <0x76>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target = <&i2cbus>;
|
||||
__dormant__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
bmp085: bmp085@77 {
|
||||
compatible = "bosch,bmp085";
|
||||
reg = <0x77>;
|
||||
default-oversampling = <3>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@2 {
|
||||
target = <&i2cbus>;
|
||||
__dormant__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
bmp180: bmp180@77 {
|
||||
compatible = "bosch,bmp180";
|
||||
reg = <0x77>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@3 {
|
||||
target = <&i2cbus>;
|
||||
__dormant__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
bmp280: bmp280@76 {
|
||||
compatible = "bosch,bmp280";
|
||||
reg = <0x76>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@4 {
|
||||
target = <&i2cbus>;
|
||||
__dormant__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
htu21: htu21@40 {
|
||||
compatible = "htu21";
|
||||
reg = <0x40>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@5 {
|
||||
target = <&i2cbus>;
|
||||
__dormant__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
lm75: lm75@4f {
|
||||
compatible = "lm75";
|
||||
reg = <0x4f>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@6 {
|
||||
target = <&i2cbus>;
|
||||
__dormant__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
si7020: si7020@40 {
|
||||
compatible = "si7020";
|
||||
reg = <0x40>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@7 {
|
||||
target = <&i2cbus>;
|
||||
__dormant__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
tmp102: tmp102@48 {
|
||||
compatible = "ti,tmp102";
|
||||
reg = <0x48>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@8 {
|
||||
target = <&i2cbus>;
|
||||
__dormant__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
hdc100x: hdc100x@40 {
|
||||
compatible = "hdc100x";
|
||||
reg = <0x40>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@9 {
|
||||
target = <&i2cbus>;
|
||||
__dormant__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
tsl4531: tsl4531@29 {
|
||||
compatible = "tsl4531";
|
||||
reg = <0x29>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@10 {
|
||||
target = <&i2cbus>;
|
||||
__dormant__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
veml6070: veml6070@38 {
|
||||
compatible = "veml6070";
|
||||
reg = <0x38>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@11 {
|
||||
target = <&i2cbus>;
|
||||
__dormant__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
sht3x: sht3x@44 {
|
||||
compatible = "sht3x";
|
||||
reg = <0x44>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@12 {
|
||||
target = <&i2cbus>;
|
||||
__dormant__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
ds1621: ds1621@48 {
|
||||
compatible = "ds1621";
|
||||
reg = <0x48>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@13 {
|
||||
target = <&i2cbus>;
|
||||
__dormant__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
max17040: max17040@36 {
|
||||
compatible = "maxim,max17040";
|
||||
reg = <0x36>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@14 {
|
||||
target = <&i2cbus>;
|
||||
__dormant__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
bme680: bme680@76 {
|
||||
compatible = "bosch,bme680";
|
||||
reg = <0x76>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@15 {
|
||||
target = <&i2cbus>;
|
||||
__dormant__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
sps30: sps30@69 {
|
||||
compatible = "sensirion,sps30";
|
||||
reg = <0x69>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@16 {
|
||||
target = <&i2cbus>;
|
||||
__dormant__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
sgp30: sgp30@58 {
|
||||
compatible = "sensirion,sgp30";
|
||||
reg = <0x58>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@17 {
|
||||
target = <&i2cbus>;
|
||||
__dormant__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
ccs811: ccs811@5b {
|
||||
compatible = "ccs811";
|
||||
reg = <0x5b>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@18 {
|
||||
target = <&i2cbus>;
|
||||
__dormant__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
bh1750: bh1750@23 {
|
||||
compatible = "bh1750";
|
||||
reg = <0x23>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@19 {
|
||||
target = <&i2cbus>;
|
||||
__dormant__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
max30102: max30102@57 {
|
||||
compatible = "maxim,max30102";
|
||||
reg = <0x57>;
|
||||
maxim,red-led-current-microamp = <7000>;
|
||||
maxim,ir-led-current-microamp = <7000>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <4 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
__overrides__ {
|
||||
bme280 = <0>,"+0";
|
||||
bmp085 = <0>,"+1";
|
||||
bmp180 = <0>,"+2";
|
||||
bmp280 = <0>,"+3";
|
||||
htu21 = <0>,"+4";
|
||||
lm75 = <0>,"+5";
|
||||
lm75addr = <&lm75>,"reg:0";
|
||||
si7020 = <0>,"+6";
|
||||
tmp102 = <0>,"+7";
|
||||
hdc100x = <0>,"+8";
|
||||
tsl4531 = <0>,"+9";
|
||||
veml6070 = <0>,"+10";
|
||||
sht3x = <0>,"+11";
|
||||
ds1621 = <0>,"+12";
|
||||
max17040 = <0>,"+13";
|
||||
bme680 = <0>,"+14";
|
||||
sps30 = <0>,"+15";
|
||||
sgp30 = <0>,"+16";
|
||||
ccs811 = <0>, "+17";
|
||||
bh1750 = <0>, "+18";
|
||||
max30102 = <0>,"+19";
|
||||
|
||||
addr = <&bme280>,"reg:0", <&bmp280>,"reg:0", <&tmp102>,"reg:0",
|
||||
<&lm75>,"reg:0", <&hdc100x>,"reg:0", <&sht3x>,"reg:0",
|
||||
<&ds1621>,"reg:0", <&bme680>,"reg:0", <&ccs811>,"reg:0",
|
||||
<&bh1750>,"reg:0";
|
||||
int_pin = <&max30102>, "interrupts:0";
|
||||
};
|
||||
};
|
34
arch/arm/boot/dts/overlays/i2s-dac-overlay.dts
Normal file
34
arch/arm/boot/dts/overlays/i2s-dac-overlay.dts
Normal file
@ -0,0 +1,34 @@
|
||||
// Definitions for RPi DAC
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm2835";
|
||||
|
||||
fragment@0 {
|
||||
target = <&i2s>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target-path = "/";
|
||||
__overlay__ {
|
||||
pcm1794a-codec {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "ti,pcm1794a";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@2 {
|
||||
target = <&sound>;
|
||||
__overlay__ {
|
||||
compatible = "rpi,rpi-dac";
|
||||
i2s-controller = <&i2s>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
27
arch/arm/boot/dts/overlays/imx219.dtsi
Normal file
27
arch/arm/boot/dts/overlays/imx219.dtsi
Normal file
@ -0,0 +1,27 @@
|
||||
// Fragment that configures an imx219
|
||||
|
||||
cam_node: imx219@10 {
|
||||
compatible = "sony,imx219";
|
||||
reg = <0x10>;
|
||||
status = "disabled";
|
||||
|
||||
clocks = <&cam1_clk>;
|
||||
clock-names = "xclk";
|
||||
|
||||
VANA-supply = <&cam1_reg>; /* 2.8v */
|
||||
VDIG-supply = <&cam_dummy_reg>; /* 1.8v */
|
||||
VDDL-supply = <&cam_dummy_reg>; /* 1.2v */
|
||||
|
||||
rotation = <180>;
|
||||
orientation = <2>;
|
||||
|
||||
port {
|
||||
cam_endpoint: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
clock-noncontinuous;
|
||||
link-frequencies =
|
||||
/bits/ 64 <456000000>;
|
||||
};
|
||||
};
|
||||
};
|
131
arch/arm/boot/dts/overlays/imx258-overlay.dts
Normal file
131
arch/arm/boot/dts/overlays/imx258-overlay.dts
Normal file
@ -0,0 +1,131 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
// Definitions for IMX258 camera module on VC I2C bus
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/{
|
||||
compatible = "brcm,bcm2835";
|
||||
|
||||
fragment@0 {
|
||||
target = <&i2c0if>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
clk_frag: fragment@1 {
|
||||
target = <&cam1_clk>;
|
||||
cam_clk: __overlay__ {
|
||||
clock-frequency = <24000000>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@2 {
|
||||
target = <&i2c0mux>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@11 {
|
||||
target = <&cam_endpoint>;
|
||||
__overlay__ {
|
||||
data-lanes = <1 2>;
|
||||
link-frequencies = /bits/ 64 <633600000
|
||||
320000000>;
|
||||
};
|
||||
};
|
||||
|
||||
fragment@12 {
|
||||
target = <&cam_endpoint>;
|
||||
__dormant__ {
|
||||
data-lanes = <1 2 3 4>;
|
||||
link-frequencies =
|
||||
/bits/ 64 <633600000 320000000>;
|
||||
};
|
||||
};
|
||||
|
||||
fragment@13 {
|
||||
target = <&csi_ep>;
|
||||
__overlay__ {
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
|
||||
fragment@14 {
|
||||
target = <&csi_ep>;
|
||||
__dormant__ {
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
|
||||
csi_frag: fragment@101 {
|
||||
target = <&csi1>;
|
||||
csi: __overlay__ {
|
||||
status = "okay";
|
||||
brcm,media-controller;
|
||||
|
||||
port {
|
||||
csi_ep: endpoint {
|
||||
remote-endpoint = <&cam_endpoint>;
|
||||
clock-lanes = <0>;
|
||||
clock-noncontinuous;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
reg_frag: fragment@5 {
|
||||
target = <&cam1_reg>;
|
||||
cam_reg: __overlay__ {
|
||||
regulator-name = "imx258_vana";
|
||||
startup-delay-us = <300000>;
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <2700000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c_frag: fragment@100 {
|
||||
target = <&i2c_csi_dsi>;
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
#include "imx258.dtsi"
|
||||
|
||||
vcm: ad5398@c {
|
||||
compatible = "adi,ad5398";
|
||||
reg = <0x0c>;
|
||||
status = "disabled";
|
||||
VANA-supply = <&cam1_reg>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
__overrides__ {
|
||||
rotation = <&cam_node>,"rotation:0";
|
||||
orientation = <&cam_node>,"orientation:0";
|
||||
media-controller = <&csi>,"brcm,media-controller?";
|
||||
cam0 = <&i2c_frag>, "target:0=",<&i2c_vc>,
|
||||
<&csi_frag>, "target:0=",<&csi0>,
|
||||
<&clk_frag>, "target:0=",<&cam0_clk>,
|
||||
<®_frag>, "target:0=",<&cam0_reg>,
|
||||
<&cam_node>, "clocks:0=",<&cam0_clk>,
|
||||
<&cam_node>, "vana-supply:0=",<&cam0_reg>;
|
||||
vcm = <&vcm>, "status=okay",
|
||||
<&cam_node>,"lens-focus:0=", <&vcm>;
|
||||
4lane = <0>, "-11+12-13+14";
|
||||
};
|
||||
};
|
||||
|
||||
&cam_node {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cam_endpoint {
|
||||
remote-endpoint = <&csi_ep>;
|
||||
};
|
27
arch/arm/boot/dts/overlays/imx258.dtsi
Normal file
27
arch/arm/boot/dts/overlays/imx258.dtsi
Normal file
@ -0,0 +1,27 @@
|
||||
// Fragment that configures a Sony IMX258
|
||||
|
||||
cam_node: imx258@10 {
|
||||
compatible = "sony,imx258";
|
||||
reg = <0x10>;
|
||||
status = "disabled";
|
||||
|
||||
clocks = <&cam1_clk>;
|
||||
clock-names = "xclk";
|
||||
|
||||
vana-supply = <&cam1_reg>; /* 2.8v */
|
||||
vdig-supply = <&cam_dummy_reg>; /* 1.05v */
|
||||
vif-supply = <&cam_dummy_reg>; /* 1.8v */
|
||||
|
||||
rotation = <180>;
|
||||
orientation = <2>;
|
||||
|
||||
port {
|
||||
cam_endpoint: endpoint {
|
||||
clock-lanes = <0>;
|
||||
clock-noncontinuous;
|
||||
link-frequencies =
|
||||
/bits/ 64 <633600000
|
||||
320000000>;
|
||||
};
|
||||
};
|
||||
};
|
24
arch/arm/boot/dts/overlays/imx290_327.dtsi
Normal file
24
arch/arm/boot/dts/overlays/imx290_327.dtsi
Normal file
@ -0,0 +1,24 @@
|
||||
// Fragment to configure and IMX290 / IMX327 / IMX462 image sensor
|
||||
|
||||
cam_node: imx290@1a {
|
||||
compatible = "sony,imx290";
|
||||
reg = <0x1a>;
|
||||
status = "disabled";
|
||||
|
||||
clocks = <&cam1_clk>;
|
||||
clock-names = "xclk";
|
||||
clock-frequency = <37125000>;
|
||||
|
||||
rotation = <0>;
|
||||
orientation = <2>;
|
||||
|
||||
vdda-supply = <&cam1_reg>; /* 2.8v */
|
||||
vdddo-supply = <&cam_dummy_reg>; /* 1.8v */
|
||||
vddd-supply = <&cam_dummy_reg>; /* 1.5v */
|
||||
|
||||
port {
|
||||
cam_endpoint: endpoint {
|
||||
clock-lanes = <0>;
|
||||
};
|
||||
};
|
||||
};
|
103
arch/arm/boot/dts/overlays/imx296-overlay.dts
Normal file
103
arch/arm/boot/dts/overlays/imx296-overlay.dts
Normal file
@ -0,0 +1,103 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
// Definitions for IMX296 camera module on VC I2C bus
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/{
|
||||
compatible = "brcm,bcm2835";
|
||||
|
||||
fragment@0 {
|
||||
target = <&i2c0if>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
clk_frag: fragment@1 {
|
||||
target = <&cam1_clk>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
clock-frequency = <37125000>;
|
||||
};
|
||||
};
|
||||
|
||||
fragment@2 {
|
||||
target = <&i2c0mux>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
reg_frag: fragment@5 {
|
||||
target = <&cam1_reg>;
|
||||
cam_reg: __overlay__ {
|
||||
startup-delay-us = <500000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c_frag: fragment@100 {
|
||||
target = <&i2c_csi_dsi>;
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
imx296: imx296@1a {
|
||||
compatible = "sony,imx296";
|
||||
reg = <0x1a>;
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cam1_clk>;
|
||||
clock-names = "inck";
|
||||
|
||||
avdd-supply = <&cam1_reg>; /* 3.3v */
|
||||
dvdd-supply = <&cam_dummy_reg>; /* 1.8v */
|
||||
ovdd-supply = <&cam_dummy_reg>; /* 1.2v */
|
||||
|
||||
rotation = <180>;
|
||||
orientation = <2>;
|
||||
|
||||
port {
|
||||
imx296_0: endpoint {
|
||||
remote-endpoint = <&csi_ep>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1>;
|
||||
clock-noncontinuous;
|
||||
link-frequencies =
|
||||
/bits/ 64 <594000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
csi_frag: fragment@101 {
|
||||
target = <&csi1>;
|
||||
csi: __overlay__ {
|
||||
status = "okay";
|
||||
brcm,media-controller;
|
||||
|
||||
port {
|
||||
csi_ep: endpoint {
|
||||
remote-endpoint = <&imx296_0>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1>;
|
||||
clock-noncontinuous;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
__overrides__ {
|
||||
rotation = <&imx296>,"rotation:0";
|
||||
orientation = <&imx296>,"orientation:0";
|
||||
media-controller = <&csi>,"brcm,media-controller?";
|
||||
cam0 = <&i2c_frag>, "target:0=",<&i2c_vc>,
|
||||
<&csi_frag>, "target:0=",<&csi0>,
|
||||
<&clk_frag>, "target:0=",<&cam0_clk>,
|
||||
<&imx296>, "clocks:0=",<&cam0_clk>,
|
||||
<&imx296>, "VANA-supply:0=",<&cam0_reg>;
|
||||
};
|
||||
};
|
32
arch/arm/boot/dts/overlays/imx327-overlay.dts
Normal file
32
arch/arm/boot/dts/overlays/imx327-overlay.dts
Normal file
@ -0,0 +1,32 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
// Definitions for IMX327 camera module on VC I2C bus
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "imx290_327-overlay.dtsi"
|
||||
|
||||
/{
|
||||
compatible = "brcm,bcm2835";
|
||||
|
||||
// Fragment numbers deliberately high to avoid conflicts with the
|
||||
// included imx290_327 overlay file.
|
||||
|
||||
fragment@101 {
|
||||
target = <&cam_node>;
|
||||
__overlay__ {
|
||||
compatible = "sony,imx327";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@102 {
|
||||
target = <&cam_node>;
|
||||
__dormant__ {
|
||||
compatible = "sony,imx327-mono";
|
||||
};
|
||||
};
|
||||
|
||||
__overrides__ {
|
||||
mono = <0>, "-101+102";
|
||||
};
|
||||
};
|
32
arch/arm/boot/dts/overlays/imx462-overlay.dts
Normal file
32
arch/arm/boot/dts/overlays/imx462-overlay.dts
Normal file
@ -0,0 +1,32 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
// Definitions for IMX462 camera module on VC I2C bus
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "imx290_327-overlay.dtsi"
|
||||
|
||||
/{
|
||||
compatible = "brcm,bcm2835";
|
||||
|
||||
// Fragment numbers deliberately high to avoid conflicts with the
|
||||
// included imx290_327 overlay file.
|
||||
|
||||
fragment@101 {
|
||||
target = <&cam_node>;
|
||||
__overlay__ {
|
||||
compatible = "sony,imx462";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@102 {
|
||||
target = <&cam_node>;
|
||||
__dormant__ {
|
||||
compatible = "sony,imx462-mono";
|
||||
};
|
||||
};
|
||||
|
||||
__overrides__ {
|
||||
mono = <0>, "-101+102";
|
||||
};
|
||||
};
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user