mirror of
https://github.com/Qortal/Brooklyn.git
synced 2025-02-07 06:44:18 +00:00
a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
29 lines
971 B
Plaintext
29 lines
971 B
Plaintext
Cavium SuperSpeed DWC3 USB SoC controller
|
|
|
|
Required properties:
|
|
- compatible: Should contain "cavium,octeon-7130-usb-uctl"
|
|
|
|
Required child node:
|
|
A child node must exist to represent the core DWC3 IP block. The name of
|
|
the node is not important. The content of the node is defined in dwc3.txt.
|
|
|
|
Example device node:
|
|
|
|
uctl@1180069000000 {
|
|
compatible = "cavium,octeon-7130-usb-uctl";
|
|
reg = <0x00011800 0x69000000 0x00000000 0x00000100>;
|
|
ranges;
|
|
#address-cells = <0x00000002>;
|
|
#size-cells = <0x00000002>;
|
|
refclk-frequency = <0x05f5e100>;
|
|
refclk-type-ss = "dlmc_ref_clk0";
|
|
refclk-type-hs = "dlmc_ref_clk0";
|
|
power = <0x00000002 0x00000002 0x00000001>;
|
|
xhci@1690000000000 {
|
|
compatible = "cavium,octeon-7130-xhci", "snps,dwc3";
|
|
reg = <0x00016900 0x00000000 0x00000010 0x00000000>;
|
|
interrupt-parent = <0x00000010>;
|
|
interrupts = <0x00000009 0x00000004>;
|
|
};
|
|
};
|