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106 lines
3.6 KiB
C
106 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
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*/
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#include <asm/fpu/api.h>
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#include <asm/cpufeature.h>
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#include <asm/processor.h>
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#include <asm/intel-family.h>
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asmlinkage void hchacha20_ssse3(u32 *derived_key, const u8 *nonce,
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const u8 *key);
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asmlinkage void chacha20_ssse3(u8 *out, const u8 *in, const size_t len,
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const u32 key[8], const u32 counter[4]);
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asmlinkage void chacha20_avx2(u8 *out, const u8 *in, const size_t len,
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const u32 key[8], const u32 counter[4]);
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asmlinkage void chacha20_avx512(u8 *out, const u8 *in, const size_t len,
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const u32 key[8], const u32 counter[4]);
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asmlinkage void chacha20_avx512vl(u8 *out, const u8 *in, const size_t len,
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const u32 key[8], const u32 counter[4]);
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static bool chacha20_use_ssse3 __ro_after_init;
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static bool chacha20_use_avx2 __ro_after_init;
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static bool chacha20_use_avx512 __ro_after_init;
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static bool chacha20_use_avx512vl __ro_after_init;
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static bool *const chacha20_nobs[] __initconst = {
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&chacha20_use_ssse3, &chacha20_use_avx2, &chacha20_use_avx512,
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&chacha20_use_avx512vl };
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static void __init chacha20_fpu_init(void)
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{
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chacha20_use_ssse3 = boot_cpu_has(X86_FEATURE_SSSE3);
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chacha20_use_avx2 =
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boot_cpu_has(X86_FEATURE_AVX) &&
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boot_cpu_has(X86_FEATURE_AVX2) &&
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cpu_has_xfeatures(XFEATURE_MASK_SSE | XFEATURE_MASK_YMM, NULL);
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#ifndef COMPAT_CANNOT_USE_AVX512
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chacha20_use_avx512 =
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boot_cpu_has(X86_FEATURE_AVX) &&
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boot_cpu_has(X86_FEATURE_AVX2) &&
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boot_cpu_has(X86_FEATURE_AVX512F) &&
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cpu_has_xfeatures(XFEATURE_MASK_SSE | XFEATURE_MASK_YMM |
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XFEATURE_MASK_AVX512, NULL) &&
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/* Skylake downclocks unacceptably much when using zmm. */
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boot_cpu_data.x86_model != INTEL_FAM6_SKYLAKE_X;
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chacha20_use_avx512vl =
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boot_cpu_has(X86_FEATURE_AVX) &&
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boot_cpu_has(X86_FEATURE_AVX2) &&
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boot_cpu_has(X86_FEATURE_AVX512F) &&
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boot_cpu_has(X86_FEATURE_AVX512VL) &&
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cpu_has_xfeatures(XFEATURE_MASK_SSE | XFEATURE_MASK_YMM |
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XFEATURE_MASK_AVX512, NULL);
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#endif
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}
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static inline bool chacha20_arch(struct chacha20_ctx *ctx, u8 *dst,
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const u8 *src, size_t len,
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simd_context_t *simd_context)
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{
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/* SIMD disables preemption, so relax after processing each page. */
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BUILD_BUG_ON(PAGE_SIZE < CHACHA20_BLOCK_SIZE ||
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PAGE_SIZE % CHACHA20_BLOCK_SIZE);
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if (!IS_ENABLED(CONFIG_AS_SSSE3) || !chacha20_use_ssse3 ||
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len <= CHACHA20_BLOCK_SIZE || !simd_use(simd_context))
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return false;
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for (;;) {
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const size_t bytes = min_t(size_t, len, PAGE_SIZE);
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if (IS_ENABLED(CONFIG_AS_AVX512) && chacha20_use_avx512 &&
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len >= CHACHA20_BLOCK_SIZE * 8)
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chacha20_avx512(dst, src, bytes, ctx->key, ctx->counter);
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else if (IS_ENABLED(CONFIG_AS_AVX512) && chacha20_use_avx512vl &&
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len >= CHACHA20_BLOCK_SIZE * 4)
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chacha20_avx512vl(dst, src, bytes, ctx->key, ctx->counter);
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else if (IS_ENABLED(CONFIG_AS_AVX2) && chacha20_use_avx2 &&
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len >= CHACHA20_BLOCK_SIZE * 4)
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chacha20_avx2(dst, src, bytes, ctx->key, ctx->counter);
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else
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chacha20_ssse3(dst, src, bytes, ctx->key, ctx->counter);
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ctx->counter[0] += (bytes + 63) / 64;
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len -= bytes;
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if (!len)
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break;
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dst += bytes;
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src += bytes;
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simd_relax(simd_context);
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}
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return true;
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}
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static inline bool hchacha20_arch(u32 derived_key[CHACHA20_KEY_WORDS],
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const u8 nonce[HCHACHA20_NONCE_SIZE],
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const u8 key[HCHACHA20_KEY_SIZE],
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simd_context_t *simd_context)
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{
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if (IS_ENABLED(CONFIG_AS_SSSE3) && chacha20_use_ssse3 &&
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simd_use(simd_context)) {
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hchacha20_ssse3(derived_key, nonce, key);
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return true;
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}
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return false;
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}
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