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35 lines
1.2 KiB
C
35 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */
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#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
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#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
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/**
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* @file
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* @defgroup bpmp_clock_ids Clock ID's
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* @{
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*/
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/**
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* @brief controls the EMC clock frequency.
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* @details Doing a clk_set_rate on this clock will select the
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* appropriate clock source, program the source rate and execute a
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* specific sequence to switch to the new clock source for both memory
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* controllers. This can be used to control the balance between memory
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* throughput and memory controller power.
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*/
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#define TEGRA234_CLK_EMC 31U
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/** @brief output of gate CLK_ENB_FUSE */
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#define TEGRA234_CLK_FUSE 40U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
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#define TEGRA234_CLK_SDMMC4 123U
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
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#define TEGRA234_CLK_UARTA 155U
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/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */
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#define TEGRA234_CLK_SDMMC_LEGACY_TM 219U
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/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
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#define TEGRA234_CLK_PLLC4 237U
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/** @brief 32K input clock provided by PMIC */
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#define TEGRA234_CLK_CLK_32K 289U
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#endif
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