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478 lines
13 KiB
C
478 lines
13 KiB
C
/*
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* Copyright 2018 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "gk104.h"
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#include "cgrp.h"
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#include "changk104.h"
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#include "user.h"
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#include <core/client.h>
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#include <core/gpuobj.h>
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#include <subdev/bar.h>
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#include <subdev/fault.h>
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#include <subdev/top.h>
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#include <subdev/timer.h>
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#include <engine/sw.h>
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#include <nvif/class.h>
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static void
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tu102_fifo_runlist_commit(struct gk104_fifo *fifo, int runl,
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struct nvkm_memory *mem, int nr)
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{
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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u64 addr = nvkm_memory_addr(mem);
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/*XXX: target? */
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nvkm_wr32(device, 0x002b00 + (runl * 0x10), lower_32_bits(addr));
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nvkm_wr32(device, 0x002b04 + (runl * 0x10), upper_32_bits(addr));
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nvkm_wr32(device, 0x002b08 + (runl * 0x10), nr);
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/*XXX: how to wait? can you even wait? */
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}
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const struct gk104_fifo_runlist_func
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tu102_fifo_runlist = {
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.size = 16,
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.cgrp = gv100_fifo_runlist_cgrp,
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.chan = gv100_fifo_runlist_chan,
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.commit = tu102_fifo_runlist_commit,
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};
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static const struct nvkm_enum
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tu102_fifo_fault_engine[] = {
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{ 0x01, "DISPLAY" },
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{ 0x03, "PTP" },
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{ 0x06, "PWR_PMU" },
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{ 0x08, "IFB", NULL, NVKM_ENGINE_IFB },
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{ 0x09, "PERF" },
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{ 0x1f, "PHYSICAL" },
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{ 0x20, "HOST0" },
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{ 0x21, "HOST1" },
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{ 0x22, "HOST2" },
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{ 0x23, "HOST3" },
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{ 0x24, "HOST4" },
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{ 0x25, "HOST5" },
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{ 0x26, "HOST6" },
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{ 0x27, "HOST7" },
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{ 0x28, "HOST8" },
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{ 0x29, "HOST9" },
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{ 0x2a, "HOST10" },
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{ 0x2b, "HOST11" },
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{ 0x2c, "HOST12" },
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{ 0x2d, "HOST13" },
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{ 0x2e, "HOST14" },
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{ 0x80, "BAR1", NULL, NVKM_SUBDEV_BAR },
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{ 0xc0, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
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{}
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};
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static void
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tu102_fifo_pbdma_init(struct gk104_fifo *fifo)
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{
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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const u32 mask = (1 << fifo->pbdma_nr) - 1;
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/*XXX: this is a bit of a guess at this point in time. */
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nvkm_mask(device, 0xb65000, 0x80000fff, 0x80000000 | mask);
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}
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static const struct gk104_fifo_pbdma_func
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tu102_fifo_pbdma = {
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.nr = gm200_fifo_pbdma_nr,
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.init = tu102_fifo_pbdma_init,
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.init_timeout = gk208_fifo_pbdma_init_timeout,
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};
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static const struct gk104_fifo_func
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tu102_fifo = {
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.pbdma = &tu102_fifo_pbdma,
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.fault.access = gv100_fifo_fault_access,
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.fault.engine = tu102_fifo_fault_engine,
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.fault.reason = gv100_fifo_fault_reason,
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.fault.hubclient = gv100_fifo_fault_hubclient,
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.fault.gpcclient = gv100_fifo_fault_gpcclient,
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.runlist = &tu102_fifo_runlist,
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.user = {{-1,-1,VOLTA_USERMODE_A }, tu102_fifo_user_new },
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.chan = {{ 0, 0,TURING_CHANNEL_GPFIFO_A}, tu102_fifo_gpfifo_new },
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.cgrp_force = true,
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};
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static void
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tu102_fifo_recover_work(struct work_struct *w)
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{
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struct gk104_fifo *fifo = container_of(w, typeof(*fifo), recover.work);
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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struct nvkm_engine *engine;
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unsigned long flags;
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u32 engm, runm, todo;
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int engn, runl;
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spin_lock_irqsave(&fifo->base.lock, flags);
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runm = fifo->recover.runm;
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engm = fifo->recover.engm;
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fifo->recover.engm = 0;
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fifo->recover.runm = 0;
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spin_unlock_irqrestore(&fifo->base.lock, flags);
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nvkm_mask(device, 0x002630, runm, runm);
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for (todo = engm; engn = __ffs(todo), todo; todo &= ~BIT(engn)) {
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if ((engine = fifo->engine[engn].engine)) {
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nvkm_subdev_fini(&engine->subdev, false);
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WARN_ON(nvkm_subdev_init(&engine->subdev));
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}
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}
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for (todo = runm; runl = __ffs(todo), todo; todo &= ~BIT(runl))
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gk104_fifo_runlist_update(fifo, runl);
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nvkm_mask(device, 0x002630, runm, 0x00000000);
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}
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static void tu102_fifo_recover_engn(struct gk104_fifo *fifo, int engn);
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static void
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tu102_fifo_recover_runl(struct gk104_fifo *fifo, int runl)
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{
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struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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const u32 runm = BIT(runl);
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assert_spin_locked(&fifo->base.lock);
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if (fifo->recover.runm & runm)
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return;
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fifo->recover.runm |= runm;
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/* Block runlist to prevent channel assignment(s) from changing. */
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nvkm_mask(device, 0x002630, runm, runm);
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/* Schedule recovery. */
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nvkm_warn(subdev, "runlist %d: scheduled for recovery\n", runl);
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schedule_work(&fifo->recover.work);
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}
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static struct gk104_fifo_chan *
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tu102_fifo_recover_chid(struct gk104_fifo *fifo, int runl, int chid)
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{
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struct gk104_fifo_chan *chan;
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struct nvkm_fifo_cgrp *cgrp;
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list_for_each_entry(chan, &fifo->runlist[runl].chan, head) {
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if (chan->base.chid == chid) {
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list_del_init(&chan->head);
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return chan;
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}
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}
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list_for_each_entry(cgrp, &fifo->runlist[runl].cgrp, head) {
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if (cgrp->id == chid) {
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chan = list_first_entry(&cgrp->chan, typeof(*chan), head);
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list_del_init(&chan->head);
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if (!--cgrp->chan_nr)
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list_del_init(&cgrp->head);
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return chan;
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}
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}
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return NULL;
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}
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static void
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tu102_fifo_recover_chan(struct nvkm_fifo *base, int chid)
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{
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struct gk104_fifo *fifo = gk104_fifo(base);
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struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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const u32 stat = nvkm_rd32(device, 0x800004 + (chid * 0x08));
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const u32 runl = (stat & 0x000f0000) >> 16;
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const bool used = (stat & 0x00000001);
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unsigned long engn, engm = fifo->runlist[runl].engm;
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struct gk104_fifo_chan *chan;
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assert_spin_locked(&fifo->base.lock);
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if (!used)
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return;
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/* Lookup SW state for channel, and mark it as dead. */
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chan = tu102_fifo_recover_chid(fifo, runl, chid);
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if (chan) {
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chan->killed = true;
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nvkm_fifo_kevent(&fifo->base, chid);
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}
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/* Disable channel. */
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nvkm_wr32(device, 0x800004 + (chid * 0x08), stat | 0x00000800);
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nvkm_warn(subdev, "channel %d: killed\n", chid);
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/* Block channel assignments from changing during recovery. */
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tu102_fifo_recover_runl(fifo, runl);
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/* Schedule recovery for any engines the channel is on. */
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for_each_set_bit(engn, &engm, fifo->engine_nr) {
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struct gk104_fifo_engine_status status;
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gk104_fifo_engine_status(fifo, engn, &status);
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if (!status.chan || status.chan->id != chid)
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continue;
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tu102_fifo_recover_engn(fifo, engn);
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}
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}
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static void
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tu102_fifo_recover_engn(struct gk104_fifo *fifo, int engn)
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{
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struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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const u32 runl = fifo->engine[engn].runl;
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const u32 engm = BIT(engn);
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struct gk104_fifo_engine_status status;
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assert_spin_locked(&fifo->base.lock);
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if (fifo->recover.engm & engm)
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return;
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fifo->recover.engm |= engm;
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/* Block channel assignments from changing during recovery. */
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tu102_fifo_recover_runl(fifo, runl);
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/* Determine which channel (if any) is currently on the engine. */
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gk104_fifo_engine_status(fifo, engn, &status);
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if (status.chan) {
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/* The channel is not longer viable, kill it. */
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tu102_fifo_recover_chan(&fifo->base, status.chan->id);
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}
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/* Preempt the runlist */
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nvkm_wr32(device, 0x2638, BIT(runl));
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/* Schedule recovery. */
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nvkm_warn(subdev, "engine %d: scheduled for recovery\n", engn);
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schedule_work(&fifo->recover.work);
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}
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static void
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tu102_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info)
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{
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struct gk104_fifo *fifo = gk104_fifo(base);
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struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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const struct nvkm_enum *er, *ee, *ec, *ea;
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struct nvkm_engine *engine = NULL;
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struct nvkm_fifo_chan *chan;
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unsigned long flags;
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const char *en = "";
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char ct[8] = "HUB/";
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int engn;
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er = nvkm_enum_find(fifo->func->fault.reason, info->reason);
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ee = nvkm_enum_find(fifo->func->fault.engine, info->engine);
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if (info->hub) {
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ec = nvkm_enum_find(fifo->func->fault.hubclient, info->client);
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} else {
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ec = nvkm_enum_find(fifo->func->fault.gpcclient, info->client);
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snprintf(ct, sizeof(ct), "GPC%d/", info->gpc);
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}
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ea = nvkm_enum_find(fifo->func->fault.access, info->access);
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if (ee && ee->data2) {
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switch (ee->data2) {
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case NVKM_SUBDEV_BAR:
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nvkm_bar_bar1_reset(device);
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break;
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case NVKM_SUBDEV_INSTMEM:
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nvkm_bar_bar2_reset(device);
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break;
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case NVKM_ENGINE_IFB:
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nvkm_mask(device, 0x001718, 0x00000000, 0x00000000);
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break;
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default:
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engine = nvkm_device_engine(device, ee->data2, 0);
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break;
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}
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}
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if (ee == NULL) {
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struct nvkm_subdev *subdev = nvkm_top_fault(device, info->engine);
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if (subdev) {
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if (subdev->func == &nvkm_engine)
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engine = container_of(subdev, typeof(*engine), subdev);
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en = engine->subdev.name;
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}
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} else {
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en = ee->name;
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}
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spin_lock_irqsave(&fifo->base.lock, flags);
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chan = nvkm_fifo_chan_inst_locked(&fifo->base, info->inst);
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nvkm_error(subdev,
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"fault %02x [%s] at %016llx engine %02x [%s] client %02x "
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"[%s%s] reason %02x [%s] on channel %d [%010llx %s]\n",
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info->access, ea ? ea->name : "", info->addr,
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info->engine, ee ? ee->name : en,
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info->client, ct, ec ? ec->name : "",
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info->reason, er ? er->name : "", chan ? chan->chid : -1,
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info->inst, chan ? chan->object.client->name : "unknown");
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/* Kill the channel that caused the fault. */
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if (chan)
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tu102_fifo_recover_chan(&fifo->base, chan->chid);
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/* Channel recovery will probably have already done this for the
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* correct engine(s), but just in case we can't find the channel
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* information...
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*/
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for (engn = 0; engn < fifo->engine_nr && engine; engn++) {
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if (fifo->engine[engn].engine == engine) {
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tu102_fifo_recover_engn(fifo, engn);
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break;
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}
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}
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spin_unlock_irqrestore(&fifo->base.lock, flags);
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}
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static void
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tu102_fifo_intr_ctxsw_timeout(struct gk104_fifo *fifo)
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{
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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unsigned long flags, engm;
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u32 engn;
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spin_lock_irqsave(&fifo->base.lock, flags);
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engm = nvkm_rd32(device, 0x2a30);
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nvkm_wr32(device, 0x2a30, engm);
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for_each_set_bit(engn, &engm, 32)
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tu102_fifo_recover_engn(fifo, engn);
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spin_unlock_irqrestore(&fifo->base.lock, flags);
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}
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static void
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tu102_fifo_intr_sched(struct gk104_fifo *fifo)
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{
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struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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u32 intr = nvkm_rd32(device, 0x00254c);
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u32 code = intr & 0x000000ff;
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nvkm_error(subdev, "SCHED_ERROR %02x\n", code);
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}
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static void
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tu102_fifo_intr(struct nvkm_fifo *base)
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{
|
|
struct gk104_fifo *fifo = gk104_fifo(base);
|
|
struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
|
|
struct nvkm_device *device = subdev->device;
|
|
u32 mask = nvkm_rd32(device, 0x002140);
|
|
u32 stat = nvkm_rd32(device, 0x002100) & mask;
|
|
|
|
if (stat & 0x00000001) {
|
|
gk104_fifo_intr_bind(fifo);
|
|
nvkm_wr32(device, 0x002100, 0x00000001);
|
|
stat &= ~0x00000001;
|
|
}
|
|
|
|
if (stat & 0x00000002) {
|
|
tu102_fifo_intr_ctxsw_timeout(fifo);
|
|
stat &= ~0x00000002;
|
|
}
|
|
|
|
if (stat & 0x00000100) {
|
|
tu102_fifo_intr_sched(fifo);
|
|
nvkm_wr32(device, 0x002100, 0x00000100);
|
|
stat &= ~0x00000100;
|
|
}
|
|
|
|
if (stat & 0x00010000) {
|
|
gk104_fifo_intr_chsw(fifo);
|
|
nvkm_wr32(device, 0x002100, 0x00010000);
|
|
stat &= ~0x00010000;
|
|
}
|
|
|
|
if (stat & 0x20000000) {
|
|
u32 mask = nvkm_rd32(device, 0x0025a0);
|
|
|
|
while (mask) {
|
|
u32 unit = __ffs(mask);
|
|
|
|
gk104_fifo_intr_pbdma_0(fifo, unit);
|
|
gk104_fifo_intr_pbdma_1(fifo, unit);
|
|
nvkm_wr32(device, 0x0025a0, (1 << unit));
|
|
mask &= ~(1 << unit);
|
|
}
|
|
stat &= ~0x20000000;
|
|
}
|
|
|
|
if (stat & 0x40000000) {
|
|
gk104_fifo_intr_runlist(fifo);
|
|
stat &= ~0x40000000;
|
|
}
|
|
|
|
if (stat & 0x80000000) {
|
|
nvkm_wr32(device, 0x002100, 0x80000000);
|
|
gk104_fifo_intr_engine(fifo);
|
|
stat &= ~0x80000000;
|
|
}
|
|
|
|
if (stat) {
|
|
nvkm_error(subdev, "INTR %08x\n", stat);
|
|
nvkm_mask(device, 0x002140, stat, 0x00000000);
|
|
nvkm_wr32(device, 0x002100, stat);
|
|
}
|
|
}
|
|
|
|
static const struct nvkm_fifo_func
|
|
tu102_fifo_ = {
|
|
.dtor = gk104_fifo_dtor,
|
|
.oneinit = gk104_fifo_oneinit,
|
|
.info = gk104_fifo_info,
|
|
.init = gk104_fifo_init,
|
|
.fini = gk104_fifo_fini,
|
|
.intr = tu102_fifo_intr,
|
|
.fault = tu102_fifo_fault,
|
|
.engine_id = gk104_fifo_engine_id,
|
|
.id_engine = gk104_fifo_id_engine,
|
|
.uevent_init = gk104_fifo_uevent_init,
|
|
.uevent_fini = gk104_fifo_uevent_fini,
|
|
.recover_chan = tu102_fifo_recover_chan,
|
|
.class_get = gk104_fifo_class_get,
|
|
.class_new = gk104_fifo_class_new,
|
|
};
|
|
|
|
int
|
|
tu102_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
|
|
struct nvkm_fifo **pfifo)
|
|
{
|
|
struct gk104_fifo *fifo;
|
|
|
|
if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL)))
|
|
return -ENOMEM;
|
|
fifo->func = &tu102_fifo;
|
|
INIT_WORK(&fifo->recover.work, tu102_fifo_recover_work);
|
|
*pfifo = &fifo->base;
|
|
|
|
return nvkm_fifo_ctor(&tu102_fifo_, device, type, inst, 4096, &fifo->base);
|
|
}
|