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Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
79 lines
1.7 KiB
YAML
79 lines
1.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Socionext UniPhier PCIe PHY
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description: |
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This describes the devicetree bindings for PHY interface built into
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PCIe controller implemented on Socionext UniPhier SoCs.
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maintainers:
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- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
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properties:
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compatible:
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enum:
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- socionext,uniphier-pro5-pcie-phy
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- socionext,uniphier-ld20-pcie-phy
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- socionext,uniphier-pxs3-pcie-phy
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- socionext,uniphier-nx1-pcie-phy
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reg:
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maxItems: 1
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"#phy-cells":
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const: 0
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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oneOf:
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- items: # for Pro5
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- const: gio
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- const: link
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- const: link # for others
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resets:
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minItems: 1
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maxItems: 2
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reset-names:
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oneOf:
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- items: # for Pro5
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- const: gio
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- const: link
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- const: link # for others
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socionext,syscon:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: A phandle to system control to set configurations for phy
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required:
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- compatible
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- reg
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- "#phy-cells"
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- clocks
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- clock-names
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- resets
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- reset-names
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additionalProperties: false
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examples:
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- |
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pcie_phy: phy@66038000 {
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compatible = "socionext,uniphier-ld20-pcie-phy";
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reg = <0x66038000 0x4000>;
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#phy-cells = <0>;
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clock-names = "link";
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clocks = <&sys_clk 24>;
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reset-names = "link";
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resets = <&sys_rst 24>;
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socionext,syscon = <&soc_glue>;
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};
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