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273 lines
7.7 KiB
C
273 lines
7.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Marvell OcteonTx2 RPM driver
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*
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* Copyright (C) 2020 Marvell.
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*
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*/
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#include "cgx.h"
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#include "lmac_common.h"
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static struct mac_ops rpm_mac_ops = {
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.name = "rpm",
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.csr_offset = 0x4e00,
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.lmac_offset = 20,
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.int_register = RPMX_CMRX_SW_INT,
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.int_set_reg = RPMX_CMRX_SW_INT_ENA_W1S,
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.irq_offset = 1,
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.int_ena_bit = BIT_ULL(0),
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.lmac_fwi = RPM_LMAC_FWI,
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.non_contiguous_serdes_lane = true,
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.rx_stats_cnt = 43,
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.tx_stats_cnt = 34,
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.get_nr_lmacs = rpm_get_nr_lmacs,
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.get_lmac_type = rpm_get_lmac_type,
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.mac_lmac_intl_lbk = rpm_lmac_internal_loopback,
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.mac_get_rx_stats = rpm_get_rx_stats,
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.mac_get_tx_stats = rpm_get_tx_stats,
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.mac_enadis_rx_pause_fwding = rpm_lmac_enadis_rx_pause_fwding,
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.mac_get_pause_frm_status = rpm_lmac_get_pause_frm_status,
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.mac_enadis_pause_frm = rpm_lmac_enadis_pause_frm,
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.mac_pause_frm_config = rpm_lmac_pause_frm_config,
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};
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struct mac_ops *rpm_get_mac_ops(void)
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{
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return &rpm_mac_ops;
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}
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static void rpm_write(rpm_t *rpm, u64 lmac, u64 offset, u64 val)
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{
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cgx_write(rpm, lmac, offset, val);
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}
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static u64 rpm_read(rpm_t *rpm, u64 lmac, u64 offset)
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{
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return cgx_read(rpm, lmac, offset);
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}
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int rpm_get_nr_lmacs(void *rpmd)
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{
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rpm_t *rpm = rpmd;
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return hweight8(rpm_read(rpm, 0, CGXX_CMRX_RX_LMACS) & 0xFULL);
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}
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void rpm_lmac_enadis_rx_pause_fwding(void *rpmd, int lmac_id, bool enable)
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{
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rpm_t *rpm = rpmd;
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u64 cfg;
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if (!rpm)
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return;
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if (enable) {
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cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
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cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE;
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rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
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} else {
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cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
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cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE;
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rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
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}
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}
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int rpm_lmac_get_pause_frm_status(void *rpmd, int lmac_id,
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u8 *tx_pause, u8 *rx_pause)
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{
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rpm_t *rpm = rpmd;
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u64 cfg;
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if (!is_lmac_valid(rpm, lmac_id))
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return -ENODEV;
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cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
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*rx_pause = !(cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE);
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cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
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*tx_pause = !(cfg & RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE);
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return 0;
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}
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int rpm_lmac_enadis_pause_frm(void *rpmd, int lmac_id, u8 tx_pause,
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u8 rx_pause)
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{
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rpm_t *rpm = rpmd;
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u64 cfg;
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if (!is_lmac_valid(rpm, lmac_id))
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return -ENODEV;
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cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
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cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE;
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cfg |= rx_pause ? 0x0 : RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE;
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cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE;
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cfg |= rx_pause ? 0x0 : RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE;
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rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
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cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
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cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE;
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cfg |= tx_pause ? 0x0 : RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE;
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rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
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cfg = rpm_read(rpm, 0, RPMX_CMR_RX_OVR_BP);
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if (tx_pause) {
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cfg &= ~RPMX_CMR_RX_OVR_BP_EN(lmac_id);
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} else {
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cfg |= RPMX_CMR_RX_OVR_BP_EN(lmac_id);
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cfg &= ~RPMX_CMR_RX_OVR_BP_BP(lmac_id);
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}
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rpm_write(rpm, 0, RPMX_CMR_RX_OVR_BP, cfg);
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return 0;
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}
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void rpm_lmac_pause_frm_config(void *rpmd, int lmac_id, bool enable)
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{
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rpm_t *rpm = rpmd;
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u64 cfg;
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if (enable) {
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/* Enable 802.3 pause frame mode */
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cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
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cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_PFC_MODE;
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rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
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/* Enable receive pause frames */
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cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
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cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE;
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rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
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/* Enable forward pause to TX block */
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cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
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cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE;
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rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
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/* Enable pause frames transmission */
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cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
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cfg &= ~RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE;
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rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
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/* Set pause time and interval */
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cfg = rpm_read(rpm, lmac_id,
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RPMX_MTI_MAC100X_CL01_PAUSE_QUANTA);
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cfg &= ~0xFFFFULL;
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rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_CL01_PAUSE_QUANTA,
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cfg | RPM_DEFAULT_PAUSE_TIME);
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/* Set pause interval as the hardware default is too short */
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cfg = rpm_read(rpm, lmac_id,
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RPMX_MTI_MAC100X_CL01_QUANTA_THRESH);
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cfg &= ~0xFFFFULL;
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rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_CL01_QUANTA_THRESH,
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cfg | (RPM_DEFAULT_PAUSE_TIME / 2));
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} else {
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/* ALL pause frames received are completely ignored */
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cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
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cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_RX_P_DISABLE;
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rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
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/* Disable forward pause to TX block */
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cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
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cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_PAUSE_IGNORE;
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rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
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/* Disable pause frames transmission */
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cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG);
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cfg |= RPMX_MTI_MAC100X_COMMAND_CONFIG_TX_P_DISABLE;
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rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg);
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}
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}
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int rpm_get_rx_stats(void *rpmd, int lmac_id, int idx, u64 *rx_stat)
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{
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rpm_t *rpm = rpmd;
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u64 val_lo, val_hi;
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if (!rpm || lmac_id >= rpm->lmac_count)
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return -ENODEV;
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mutex_lock(&rpm->lock);
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/* Update idx to point per lmac Rx statistics page */
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idx += lmac_id * rpm->mac_ops->rx_stats_cnt;
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/* Read lower 32 bits of counter */
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val_lo = rpm_read(rpm, 0, RPMX_MTI_STAT_RX_STAT_PAGES_COUNTERX +
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(idx * 8));
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/* upon read of lower 32 bits, higher 32 bits are written
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* to RPMX_MTI_STAT_DATA_HI_CDC
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*/
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val_hi = rpm_read(rpm, 0, RPMX_MTI_STAT_DATA_HI_CDC);
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*rx_stat = (val_hi << 32 | val_lo);
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mutex_unlock(&rpm->lock);
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return 0;
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}
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int rpm_get_tx_stats(void *rpmd, int lmac_id, int idx, u64 *tx_stat)
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{
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rpm_t *rpm = rpmd;
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u64 val_lo, val_hi;
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if (!rpm || lmac_id >= rpm->lmac_count)
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return -ENODEV;
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mutex_lock(&rpm->lock);
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/* Update idx to point per lmac Tx statistics page */
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idx += lmac_id * rpm->mac_ops->tx_stats_cnt;
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val_lo = rpm_read(rpm, 0, RPMX_MTI_STAT_TX_STAT_PAGES_COUNTERX +
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(idx * 8));
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val_hi = rpm_read(rpm, 0, RPMX_MTI_STAT_DATA_HI_CDC);
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*tx_stat = (val_hi << 32 | val_lo);
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mutex_unlock(&rpm->lock);
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return 0;
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}
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u8 rpm_get_lmac_type(void *rpmd, int lmac_id)
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{
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rpm_t *rpm = rpmd;
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u64 req = 0, resp;
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int err;
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req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_LINK_STS, req);
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err = cgx_fwi_cmd_generic(req, &resp, rpm, 0);
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if (!err)
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return FIELD_GET(RESP_LINKSTAT_LMAC_TYPE, resp);
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return err;
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}
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int rpm_lmac_internal_loopback(void *rpmd, int lmac_id, bool enable)
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{
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rpm_t *rpm = rpmd;
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u8 lmac_type;
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u64 cfg;
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if (!rpm || lmac_id >= rpm->lmac_count)
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return -ENODEV;
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lmac_type = rpm->mac_ops->get_lmac_type(rpm, lmac_id);
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if (lmac_type == LMAC_MODE_100G_R) {
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cfg = rpm_read(rpm, lmac_id, RPMX_MTI_PCS100X_CONTROL1);
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if (enable)
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cfg |= RPMX_MTI_PCS_LBK;
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else
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cfg &= ~RPMX_MTI_PCS_LBK;
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rpm_write(rpm, lmac_id, RPMX_MTI_PCS100X_CONTROL1, cfg);
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} else {
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cfg = rpm_read(rpm, lmac_id, RPMX_MTI_LPCSX_CONTROL1);
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if (enable)
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cfg |= RPMX_MTI_PCS_LBK;
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else
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cfg &= ~RPMX_MTI_PCS_LBK;
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rpm_write(rpm, lmac_id, RPMX_MTI_LPCSX_CONTROL1, cfg);
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}
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return 0;
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}
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