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2a709f28fa
* 0day explit mitigation * Memory corruption prevention * Privilege escalation prevention * Buffer over flow prevention * File System corruption defense * Thread escape prevention This may very well be the most intensive inclusion to BrooklynR. This will not be part of an x86 suite nor it will be released as tool kit. The security core toolkit will remain part of kernel base.
118 lines
3.6 KiB
C
118 lines
3.6 KiB
C
/*
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* Wireless Host Controller Interface for Ultra-Wide-Band and Wireless USB
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*
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* Copyright (C) 2005-2006 Intel Corporation
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* Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version
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* 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*
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*
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*
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* References:
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* [WHCI] Wireless Host Controller Interface Specification for
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* Certified Wireless Universal Serial Bus, revision 0.95.
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*/
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#ifndef _LINUX_UWB_WHCI_H_
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#define _LINUX_UWB_WHCI_H_
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#include <linux/pci.h>
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/*
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* UWB interface capability registers (offsets from UWBBASE)
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*
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* [WHCI] section 2.2
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*/
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#define UWBCAPINFO 0x00 /* == UWBCAPDATA(0) */
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# define UWBCAPINFO_TO_N_CAPS(c) (((c) >> 0) & 0xFull)
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#define UWBCAPDATA(n) (8*(n))
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# define UWBCAPDATA_TO_VERSION(c) (((c) >> 32) & 0xFFFFull)
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# define UWBCAPDATA_TO_OFFSET(c) (((c) >> 18) & 0x3FFFull)
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# define UWBCAPDATA_TO_BAR(c) (((c) >> 16) & 0x3ull)
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# define UWBCAPDATA_TO_SIZE(c) ((((c) >> 8) & 0xFFull) * sizeof(u32))
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# define UWBCAPDATA_TO_CAP_ID(c) (((c) >> 0) & 0xFFull)
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/* Size of the WHCI capability data (including the RC capability) for
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a device with n capabilities. */
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#define UWBCAPDATA_SIZE(n) (8 + 8*(n))
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/*
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* URC registers (offsets from URCBASE)
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*
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* [WHCI] section 2.3
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*/
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#define URCCMD 0x00
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# define URCCMD_RESET (1 << 31) /* UMC Hardware reset */
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# define URCCMD_RS (1 << 30) /* Run/Stop */
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# define URCCMD_EARV (1 << 29) /* Event Address Register Valid */
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# define URCCMD_ACTIVE (1 << 15) /* Command is active */
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# define URCCMD_IWR (1 << 14) /* Interrupt When Ready */
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# define URCCMD_SIZE_MASK 0x00000fff /* Command size mask */
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#define URCSTS 0x04
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# define URCSTS_EPS (1 << 17) /* Event Processing Status */
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# define URCSTS_HALTED (1 << 16) /* RC halted */
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# define URCSTS_HSE (1 << 10) /* Host System Error...fried */
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# define URCSTS_ER (1 << 9) /* Event Ready */
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# define URCSTS_RCI (1 << 8) /* Ready for Command Interrupt */
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# define URCSTS_INT_MASK 0x00000700 /* URC interrupt sources */
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# define URCSTS_ISI 0x000000ff /* Interrupt Source Identification */
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#define URCINTR 0x08
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# define URCINTR_EN_ALL 0x000007ff /* Enable all interrupt sources */
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#define URCCMDADDR 0x10
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#define URCEVTADDR 0x18
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# define URCEVTADDR_OFFSET_MASK 0xfff /* Event pointer offset mask */
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/** Write 32 bit @value to little endian register at @addr */
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static inline
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void le_writel(u32 value, void __iomem *addr)
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{
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iowrite32(value, addr);
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}
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/** Read from 32 bit little endian register at @addr */
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static inline
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u32 le_readl(void __iomem *addr)
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{
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return ioread32(addr);
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}
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/** Write 64 bit @value to little endian register at @addr */
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static inline
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void le_writeq(u64 value, void __iomem *addr)
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{
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iowrite32(value, addr);
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iowrite32(value >> 32, addr + 4);
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}
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/** Read from 64 bit little endian register at @addr */
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static inline
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u64 le_readq(void __iomem *addr)
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{
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u64 value;
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value = ioread32(addr);
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value |= (u64)ioread32(addr + 4) << 32;
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return value;
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}
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extern int whci_wait_for(struct device *dev, u32 __iomem *reg,
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u32 mask, u32 result,
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unsigned long max_ms, const char *tag);
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#endif /* #ifndef _LINUX_UWB_WHCI_H_ */
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