mirror of
https://github.com/Qortal/Brooklyn.git
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117 lines
3.5 KiB
C
117 lines
3.5 KiB
C
/*
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* Copyright 2018 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "gk104.h"
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#include "cgrp.h"
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#include "changk104.h"
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#include "user.h"
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#include <core/gpuobj.h>
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#include <nvif/class.h>
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static void
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tu102_fifo_runlist_commit(struct gk104_fifo *fifo, int runl,
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struct nvkm_memory *mem, int nr)
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{
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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u64 addr = nvkm_memory_addr(mem);
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/*XXX: target? */
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nvkm_wr32(device, 0x002b00 + (runl * 0x10), lower_32_bits(addr));
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nvkm_wr32(device, 0x002b04 + (runl * 0x10), upper_32_bits(addr));
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nvkm_wr32(device, 0x002b08 + (runl * 0x10), nr);
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/*XXX: how to wait? can you even wait? */
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}
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const struct gk104_fifo_runlist_func
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tu102_fifo_runlist = {
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.size = 16,
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.cgrp = gv100_fifo_runlist_cgrp,
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.chan = gv100_fifo_runlist_chan,
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.commit = tu102_fifo_runlist_commit,
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};
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static const struct nvkm_enum
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tu102_fifo_fault_engine[] = {
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{ 0x01, "DISPLAY" },
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{ 0x03, "PTP" },
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{ 0x06, "PWR_PMU" },
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{ 0x08, "IFB", NULL, NVKM_ENGINE_IFB },
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{ 0x09, "PERF" },
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{ 0x1f, "PHYSICAL" },
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{ 0x20, "HOST0" },
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{ 0x21, "HOST1" },
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{ 0x22, "HOST2" },
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{ 0x23, "HOST3" },
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{ 0x24, "HOST4" },
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{ 0x25, "HOST5" },
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{ 0x26, "HOST6" },
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{ 0x27, "HOST7" },
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{ 0x28, "HOST8" },
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{ 0x29, "HOST9" },
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{ 0x2a, "HOST10" },
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{ 0x2b, "HOST11" },
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{ 0x2c, "HOST12" },
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{ 0x2d, "HOST13" },
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{ 0x2e, "HOST14" },
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{ 0x80, "BAR1", NULL, NVKM_SUBDEV_BAR },
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{ 0xc0, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
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{}
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};
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static void
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tu102_fifo_pbdma_init(struct gk104_fifo *fifo)
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{
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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const u32 mask = (1 << fifo->pbdma_nr) - 1;
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/*XXX: this is a bit of a guess at this point in time. */
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nvkm_mask(device, 0xb65000, 0x80000fff, 0x80000000 | mask);
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}
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static const struct gk104_fifo_pbdma_func
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tu102_fifo_pbdma = {
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.nr = gm200_fifo_pbdma_nr,
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.init = tu102_fifo_pbdma_init,
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.init_timeout = gk208_fifo_pbdma_init_timeout,
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};
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static const struct gk104_fifo_func
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tu102_fifo = {
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.pbdma = &tu102_fifo_pbdma,
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.fault.access = gv100_fifo_fault_access,
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.fault.engine = tu102_fifo_fault_engine,
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.fault.reason = gv100_fifo_fault_reason,
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.fault.hubclient = gv100_fifo_fault_hubclient,
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.fault.gpcclient = gv100_fifo_fault_gpcclient,
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.runlist = &tu102_fifo_runlist,
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.user = {{-1,-1,VOLTA_USERMODE_A }, tu102_fifo_user_new },
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.chan = {{ 0, 0,TURING_CHANNEL_GPFIFO_A}, tu102_fifo_gpfifo_new },
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.cgrp_force = true,
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};
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int
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tu102_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
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{
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return gk104_fifo_new_(&tu102_fifo, device, index, 4096, pfifo);
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}
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