mirror of
https://github.com/Qortal/Brooklyn.git
synced 2025-02-19 13:45:54 +00:00
a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
91 lines
2.7 KiB
JSON
91 lines
2.7 KiB
JSON
[
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{
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"BriefDescription": "BACLEARS asserted.",
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"Counter": "0,1",
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"EventCode": "0xE6",
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"EventName": "BACLEARS.ANY",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Cycles during which instruction fetches are stalled.",
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"Counter": "0,1",
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"EventCode": "0x86",
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"EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Decode stall due to IQ full",
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"Counter": "0,1",
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"EventCode": "0x87",
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"EventName": "DECODE_STALL.IQ_FULL",
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"SampleAfterValue": "2000000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Decode stall due to PFB empty",
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"Counter": "0,1",
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"EventCode": "0x87",
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"EventName": "DECODE_STALL.PFB_EMPTY",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Instruction fetches.",
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"Counter": "0,1",
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"EventCode": "0x80",
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"EventName": "ICACHE.ACCESSES",
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"SampleAfterValue": "200000",
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"UMask": "0x3"
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},
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{
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"BriefDescription": "Icache hit",
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"Counter": "0,1",
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"EventCode": "0x80",
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"EventName": "ICACHE.HIT",
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"SampleAfterValue": "200000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Icache miss",
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"Counter": "0,1",
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"EventCode": "0x80",
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"EventName": "ICACHE.MISSES",
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"SampleAfterValue": "200000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "All Instructions decoded",
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"Counter": "0,1",
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"EventCode": "0xAA",
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"EventName": "MACRO_INSTS.ALL_DECODED",
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"SampleAfterValue": "2000000",
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"UMask": "0x3"
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},
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{
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"BriefDescription": "CISC macro instructions decoded",
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"Counter": "0,1",
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"EventCode": "0xAA",
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"EventName": "MACRO_INSTS.CISC_DECODED",
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"SampleAfterValue": "2000000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Non-CISC nacro instructions decoded",
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"Counter": "0,1",
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"EventCode": "0xAA",
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"EventName": "MACRO_INSTS.NON_CISC_DECODED",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.",
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"Counter": "0,1",
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"CounterMask": "1",
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"EventCode": "0xA9",
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"EventName": "UOPS.MS_CYCLES",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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}
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] |