mirror of
https://github.com/Qortal/Brooklyn.git
synced 2025-02-19 13:45:54 +00:00
a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
154 lines
4.6 KiB
JSON
154 lines
4.6 KiB
JSON
[
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{
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"BriefDescription": "Nonzero segbase 1 bubble",
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"Counter": "0,1",
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"EventCode": "0x5",
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"EventName": "MISALIGN_MEM_REF.BUBBLE",
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"SampleAfterValue": "200000",
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"UMask": "0x97"
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},
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{
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"BriefDescription": "Nonzero segbase load 1 bubble",
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"Counter": "0,1",
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"EventCode": "0x5",
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"EventName": "MISALIGN_MEM_REF.LD_BUBBLE",
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"SampleAfterValue": "200000",
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"UMask": "0x91"
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},
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{
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"BriefDescription": "Load splits",
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"Counter": "0,1",
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"EventCode": "0x5",
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"EventName": "MISALIGN_MEM_REF.LD_SPLIT",
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"SampleAfterValue": "200000",
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"UMask": "0x9"
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},
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{
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"BriefDescription": "Load splits (At Retirement)",
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"Counter": "0,1",
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"EventCode": "0x5",
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"EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR",
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"SampleAfterValue": "200000",
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"UMask": "0x89"
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},
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{
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"BriefDescription": "Nonzero segbase ld-op-st 1 bubble",
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"Counter": "0,1",
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"EventCode": "0x5",
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"EventName": "MISALIGN_MEM_REF.RMW_BUBBLE",
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"SampleAfterValue": "200000",
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"UMask": "0x94"
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},
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{
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"BriefDescription": "ld-op-st splits",
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"Counter": "0,1",
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"EventCode": "0x5",
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"EventName": "MISALIGN_MEM_REF.RMW_SPLIT",
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"SampleAfterValue": "200000",
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"UMask": "0x8c"
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},
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{
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"BriefDescription": "Memory references that cross an 8-byte boundary.",
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"Counter": "0,1",
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"EventCode": "0x5",
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"EventName": "MISALIGN_MEM_REF.SPLIT",
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"SampleAfterValue": "200000",
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"UMask": "0xf"
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},
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{
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"BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)",
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"Counter": "0,1",
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"EventCode": "0x5",
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"EventName": "MISALIGN_MEM_REF.SPLIT.AR",
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"SampleAfterValue": "200000",
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"UMask": "0x8f"
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},
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{
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"BriefDescription": "Nonzero segbase store 1 bubble",
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"Counter": "0,1",
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"EventCode": "0x5",
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"EventName": "MISALIGN_MEM_REF.ST_BUBBLE",
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"SampleAfterValue": "200000",
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"UMask": "0x92"
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},
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{
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"BriefDescription": "Store splits",
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"Counter": "0,1",
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"EventCode": "0x5",
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"EventName": "MISALIGN_MEM_REF.ST_SPLIT",
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"SampleAfterValue": "200000",
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"UMask": "0xa"
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},
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{
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"BriefDescription": "Store splits (Ar Retirement)",
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"Counter": "0,1",
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"EventCode": "0x5",
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"EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR",
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"SampleAfterValue": "200000",
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"UMask": "0x8a"
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},
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{
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"BriefDescription": "L1 hardware prefetch request",
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"Counter": "0,1",
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"EventCode": "0x7",
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"EventName": "PREFETCH.HW_PREFETCH",
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"SampleAfterValue": "2000000",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed",
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"Counter": "0,1",
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"EventCode": "0x7",
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"EventName": "PREFETCH.PREFETCHNTA",
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"SampleAfterValue": "200000",
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"UMask": "0x88"
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},
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{
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"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.",
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"Counter": "0,1",
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"EventCode": "0x7",
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"EventName": "PREFETCH.PREFETCHT0",
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"SampleAfterValue": "200000",
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"UMask": "0x81"
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},
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{
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"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.",
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"Counter": "0,1",
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"EventCode": "0x7",
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"EventName": "PREFETCH.PREFETCHT1",
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"SampleAfterValue": "200000",
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"UMask": "0x82"
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},
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{
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"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.",
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"Counter": "0,1",
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"EventCode": "0x7",
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"EventName": "PREFETCH.PREFETCHT2",
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"SampleAfterValue": "200000",
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"UMask": "0x84"
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},
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{
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"BriefDescription": "Any Software prefetch",
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"Counter": "0,1",
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"EventCode": "0x7",
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"EventName": "PREFETCH.SOFTWARE_PREFETCH",
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"SampleAfterValue": "200000",
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"UMask": "0xf"
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},
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{
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"BriefDescription": "Any Software prefetch",
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"Counter": "0,1",
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"EventCode": "0x7",
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"EventName": "PREFETCH.SOFTWARE_PREFETCH.AR",
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"SampleAfterValue": "200000",
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"UMask": "0x8f"
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},
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{
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"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed",
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"Counter": "0,1",
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"EventCode": "0x7",
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"EventName": "PREFETCH.SW_L2",
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"SampleAfterValue": "200000",
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"UMask": "0x86"
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}
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] |