mirror of
https://github.com/Qortal/Brooklyn.git
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a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
124 lines
3.5 KiB
JSON
124 lines
3.5 KiB
JSON
[
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{
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"BriefDescription": "Memory accesses that missed the DTLB.",
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"Counter": "0,1",
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"EventCode": "0x8",
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"EventName": "DATA_TLB_MISSES.DTLB_MISS",
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"SampleAfterValue": "200000",
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"UMask": "0x7"
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},
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{
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"BriefDescription": "DTLB misses due to load operations.",
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"Counter": "0,1",
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"EventCode": "0x8",
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"EventName": "DATA_TLB_MISSES.DTLB_MISS_LD",
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"SampleAfterValue": "200000",
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"UMask": "0x5"
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},
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{
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"BriefDescription": "DTLB misses due to store operations.",
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"Counter": "0,1",
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"EventCode": "0x8",
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"EventName": "DATA_TLB_MISSES.DTLB_MISS_ST",
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"SampleAfterValue": "200000",
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"UMask": "0x6"
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},
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{
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"BriefDescription": "L0 DTLB misses due to load operations.",
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"Counter": "0,1",
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"EventCode": "0x8",
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"EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD",
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"SampleAfterValue": "200000",
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"UMask": "0x9"
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},
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{
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"BriefDescription": "L0 DTLB misses due to store operations",
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"Counter": "0,1",
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"EventCode": "0x8",
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"EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST",
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"SampleAfterValue": "200000",
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"UMask": "0xa"
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},
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{
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"BriefDescription": "ITLB flushes.",
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"Counter": "0,1",
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"EventCode": "0x82",
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"EventName": "ITLB.FLUSH",
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"SampleAfterValue": "200000",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "ITLB hits.",
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"Counter": "0,1",
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"EventCode": "0x82",
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"EventName": "ITLB.HIT",
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"SampleAfterValue": "200000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "ITLB misses.",
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"Counter": "0,1",
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"EventCode": "0x82",
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"EventName": "ITLB.MISSES",
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"PEBS": "2",
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"SampleAfterValue": "200000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Retired loads that miss the DTLB (precise event).",
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"Counter": "0,1",
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"EventCode": "0xCB",
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"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
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"PEBS": "1",
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"SampleAfterValue": "200000",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Duration of page-walks in core cycles",
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"Counter": "0,1",
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"EventCode": "0xC",
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"EventName": "PAGE_WALKS.CYCLES",
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"SampleAfterValue": "2000000",
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"UMask": "0x3"
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},
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{
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"BriefDescription": "Duration of D-side only page walks",
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"Counter": "0,1",
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"EventCode": "0xC",
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"EventName": "PAGE_WALKS.D_SIDE_CYCLES",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Number of D-side only page walks",
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"Counter": "0,1",
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"EventCode": "0xC",
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"EventName": "PAGE_WALKS.D_SIDE_WALKS",
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"SampleAfterValue": "200000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Duration of I-Side page walks",
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"Counter": "0,1",
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"EventCode": "0xC",
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"EventName": "PAGE_WALKS.I_SIDE_CYCLES",
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"SampleAfterValue": "2000000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Number of I-Side page walks",
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"Counter": "0,1",
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"EventCode": "0xC",
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"EventName": "PAGE_WALKS.I_SIDE_WALKS",
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"SampleAfterValue": "200000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Number of page-walks executed.",
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"Counter": "0,1",
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"EventCode": "0xC",
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"EventName": "PAGE_WALKS.WALKS",
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"SampleAfterValue": "200000",
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"UMask": "0x3"
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}
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] |