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39 lines
1.1 KiB
Verilog
39 lines
1.1 KiB
Verilog
`include "settings.h"
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module Condition_Check
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(
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input [3:0] condition,
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input [3:0] status_register,
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output reg condition_state
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);
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wire Z = status_register[3];
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wire C = status_register[2];
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wire N = status_register[1];
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wire V = status_register[0];
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parameter[3:0] EQ = 4'd0, NE = 4'd1, CS_HS = 4'd2, CC_LO = 4'd3, MI = 4'd4,
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PL = 4'd5, VS = 4'd6, VC = 4'd7, HI = 4'd8, LS = 4'd9, GE = 4'd10, LT = 4'd11,
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GT = 4'd12, LE = 4'd13, AL = 4'd14;
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always @*
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case(condition)
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EQ: condition_state = Z;
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NE: condition_state = ~Z;
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CS_HS: condition_state = C;
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CC_LO: condition_state = ~C;
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MI: condition_state = N;
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PL: condition_state = ~N;
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VS: condition_state = V;
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VC: condition_state = ~V;
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HI: condition_state = C & ~Z;
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LS: condition_state = ~C & Z;
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GE: condition_state = (N & V) | (~N & ~V);
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LT: condition_state = (N & ~V) | (~N & V);
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GT: condition_state = ~Z & ((N & V) | (~N & ~V));
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LE: condition_state = Z & ((N & ~V) | (~N & V));
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AL: condition_state = 1'b1;
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endcase
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endmodule
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