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82 lines
2.5 KiB
Verilog
82 lines
2.5 KiB
Verilog
`include "settings.h"
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module ID_Reg
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(
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input clk,
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input rst,
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input flush,
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input [`WORD_WIDTH-1:0] pc_in,
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input [`WORD_WIDTH-1:0] instruction_in,
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input [`REG_FILE_DEPTH-1:0] reg_file_dst_in,
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input [`WORD_WIDTH-1:0] val_Rn_in, val_Rm_in,
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input [`SIGNED_IMM_WIDTH-1:0] signed_immediate_in,
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input [`SHIFTER_OPERAND_WIDTH-1:0] shifter_operand_in,
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input [3:0] EX_command_in,
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input [3:0] status_register_in,
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input mem_read_in, mem_write_in,
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WB_en_in,
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Imm_in,
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B_in,
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SR_update_in,
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input [`REG_FILE_DEPTH-1:0] reg_file_src1_in,
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input [`REG_FILE_DEPTH-1:0] reg_file_src2_in,
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output reg [`WORD_WIDTH-1:0] pc,
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output reg [`WORD_WIDTH-1:0] instruction,
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output reg [`REG_FILE_DEPTH-1:0] reg_file_dst_out,
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output reg [`WORD_WIDTH-1:0] val_Rn_out, val_Rm_out,
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output reg [`SIGNED_IMM_WIDTH-1:0] signed_immediate_out,
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output reg [`SHIFTER_OPERAND_WIDTH-1:0] shifter_operand_out,
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output reg [3:0] EX_command_out,
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output reg [3:0] status_register_out,
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output reg mem_read_out, mem_write_out,
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WB_en_out,
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Imm_out,
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B_out,
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SR_update_out,
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output reg [`REG_FILE_DEPTH-1:0] reg_file_src1_out,
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output reg [`REG_FILE_DEPTH-1:0] reg_file_src2_out
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);
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always @(posedge clk, posedge rst) begin
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if (rst || flush) begin
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pc <= 0;
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instruction <= 0;
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reg_file_dst_out <= 0;
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val_Rn_out <= 0;
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val_Rm_out <=0;
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signed_immediate_out <= 0;
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shifter_operand_out <= 0;
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EX_command_out <= 0;
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status_register_out <= 0;
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mem_read_out <= 0;
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mem_write_out <= 0;
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WB_en_out <= 0;
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Imm_out <= 0;
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B_out <= 0;
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SR_update_out <= 0;
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reg_file_src1_out <= 0;
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reg_file_src2_out <= 0;
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end
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else begin
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pc <= pc_in;
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instruction <= instruction_in;
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reg_file_dst_out <= reg_file_dst_in;
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val_Rn_out <= val_Rn_in;
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val_Rm_out <= val_Rm_in;
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signed_immediate_out <= signed_immediate_in;
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shifter_operand_out <= shifter_operand_in;
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EX_command_out <= EX_command_in;
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status_register_out <= status_register_in;
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mem_read_out <= mem_read_in;
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mem_write_out <= mem_write_in;
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WB_en_out <= WB_en_in;
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Imm_out <= Imm_in;
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B_out <= B_in;
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SR_update_out <= SR_update_in;
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reg_file_src1_out <= reg_file_src1_in;
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reg_file_src2_out <= reg_file_src2_in;
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end
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end
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endmodule
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