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24 lines
415 B
Verilog
24 lines
415 B
Verilog
`include "settings.h"
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module PC
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(
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input clk,
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input rst,
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input freeze,
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input [`WORD_WIDTH-1:0] pc_in,
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output reg [`WORD_WIDTH-1:0] pc
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);
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always @(posedge clk or posedge rst) begin
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if(rst) begin
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pc <= 0;
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end
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else if(~freeze) begin
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pc <= pc_in;
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end
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else begin
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pc <= pc;
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end
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end
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endmodule |