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41 lines
1.2 KiB
C
41 lines
1.2 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2015 Intel Corporation
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*/
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#ifndef INTEL_MOCS_H
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#define INTEL_MOCS_H
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/**
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* DOC: Memory Objects Control State (MOCS)
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*
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* Motivation:
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* In previous Gens the MOCS settings was a value that was set by user land as
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* part of the batch. In Gen9 this has changed to be a single table (per ring)
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* that all batches now reference by index instead of programming the MOCS
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* directly.
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*
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* The one wrinkle in this is that only PART of the MOCS tables are included
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* in context (The GFX_MOCS_0 - GFX_MOCS_64 and the LNCFCMOCS0 - LNCFCMOCS32
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* registers). The rest are not (the settings for the other rings).
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*
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* This table needs to be set at system start-up because the way the table
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* interacts with the contexts and the GmmLib interface.
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*
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*
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* Implementation:
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*
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* The tables (one per supported platform) are defined in intel_mocs.c
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* and are programmed in the first batch after the context is loaded
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* (with the hardware workarounds). This will then let the usual
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* context handling keep the MOCS in step.
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*/
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struct intel_engine_cs;
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struct intel_gt;
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void intel_mocs_init(struct intel_gt *gt);
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void intel_mocs_init_engine(struct intel_engine_cs *engine);
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#endif
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