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176 lines
6.5 KiB
C
176 lines
6.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Stuff for AMCC S5933 PCI Controller
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*
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* Author: Michal Dobes <dobes@tesnet.cz>
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*
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* Inspirated from general-purpose AMCC S5933 PCI Matchmaker driver
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* made by Andrea Cisternino <acister@pcape1.pi.infn.it>
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* and as result of espionage from MITE code made by David A. Schleef.
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* Thanks to AMCC for their on-line documentation and bus master DMA
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* example.
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*/
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#ifndef _AMCC_S5933_H_
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#define _AMCC_S5933_H_
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/****************************************************************************/
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/* AMCC Operation Register Offsets - PCI */
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/****************************************************************************/
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#define AMCC_OP_REG_OMB1 0x00
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#define AMCC_OP_REG_OMB2 0x04
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#define AMCC_OP_REG_OMB3 0x08
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#define AMCC_OP_REG_OMB4 0x0c
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#define AMCC_OP_REG_IMB1 0x10
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#define AMCC_OP_REG_IMB2 0x14
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#define AMCC_OP_REG_IMB3 0x18
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#define AMCC_OP_REG_IMB4 0x1c
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#define AMCC_OP_REG_FIFO 0x20
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#define AMCC_OP_REG_MWAR 0x24
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#define AMCC_OP_REG_MWTC 0x28
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#define AMCC_OP_REG_MRAR 0x2c
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#define AMCC_OP_REG_MRTC 0x30
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#define AMCC_OP_REG_MBEF 0x34
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#define AMCC_OP_REG_INTCSR 0x38
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#define AMCC_OP_REG_INTCSR_SRC (AMCC_OP_REG_INTCSR + 2) /* INT source */
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#define AMCC_OP_REG_INTCSR_FEC (AMCC_OP_REG_INTCSR + 3) /* FIFO ctrl */
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#define AMCC_OP_REG_MCSR 0x3c
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#define AMCC_OP_REG_MCSR_NVDATA (AMCC_OP_REG_MCSR + 2) /* Data in byte 2 */
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#define AMCC_OP_REG_MCSR_NVCMD (AMCC_OP_REG_MCSR + 3) /* Command in byte 3 */
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#define AMCC_FIFO_DEPTH_DWORD 8
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#define AMCC_FIFO_DEPTH_BYTES (8 * sizeof(u32))
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/****************************************************************************/
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/* AMCC - PCI Interrupt Control/Status Register */
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/****************************************************************************/
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#define INTCSR_OUTBOX_BYTE(x) ((x) & 0x3)
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#define INTCSR_OUTBOX_SELECT(x) (((x) & 0x3) << 2)
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#define INTCSR_OUTBOX_EMPTY_INT 0x10 /* enable outbox empty interrupt */
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#define INTCSR_INBOX_BYTE(x) (((x) & 0x3) << 8)
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#define INTCSR_INBOX_SELECT(x) (((x) & 0x3) << 10)
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#define INTCSR_INBOX_FULL_INT 0x1000 /* enable inbox full interrupt */
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/* read, or write clear inbox full interrupt */
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#define INTCSR_INBOX_INTR_STATUS 0x20000
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/* read only, interrupt asserted */
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#define INTCSR_INTR_ASSERTED 0x800000
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/****************************************************************************/
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/* AMCC - PCI non-volatile ram command register (byte 3 of AMCC_OP_REG_MCSR) */
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/****************************************************************************/
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#define MCSR_NV_LOAD_LOW_ADDR 0x0
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#define MCSR_NV_LOAD_HIGH_ADDR 0x20
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#define MCSR_NV_WRITE 0x40
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#define MCSR_NV_READ 0x60
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#define MCSR_NV_MASK 0x60
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#define MCSR_NV_ENABLE 0x80
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#define MCSR_NV_BUSY MCSR_NV_ENABLE
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/****************************************************************************/
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/* AMCC Operation Registers Size - PCI */
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/****************************************************************************/
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#define AMCC_OP_REG_SIZE 64 /* in bytes */
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/****************************************************************************/
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/* AMCC Operation Register Offsets - Add-on */
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/****************************************************************************/
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#define AMCC_OP_REG_AIMB1 0x00
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#define AMCC_OP_REG_AIMB2 0x04
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#define AMCC_OP_REG_AIMB3 0x08
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#define AMCC_OP_REG_AIMB4 0x0c
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#define AMCC_OP_REG_AOMB1 0x10
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#define AMCC_OP_REG_AOMB2 0x14
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#define AMCC_OP_REG_AOMB3 0x18
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#define AMCC_OP_REG_AOMB4 0x1c
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#define AMCC_OP_REG_AFIFO 0x20
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#define AMCC_OP_REG_AMWAR 0x24
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#define AMCC_OP_REG_APTA 0x28
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#define AMCC_OP_REG_APTD 0x2c
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#define AMCC_OP_REG_AMRAR 0x30
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#define AMCC_OP_REG_AMBEF 0x34
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#define AMCC_OP_REG_AINT 0x38
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#define AMCC_OP_REG_AGCSTS 0x3c
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#define AMCC_OP_REG_AMWTC 0x58
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#define AMCC_OP_REG_AMRTC 0x5c
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/****************************************************************************/
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/* AMCC - Add-on General Control/Status Register */
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/****************************************************************************/
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#define AGCSTS_CONTROL_MASK 0xfffff000
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#define AGCSTS_NV_ACC_MASK 0xe0000000
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#define AGCSTS_RESET_MASK 0x0e000000
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#define AGCSTS_NV_DA_MASK 0x00ff0000
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#define AGCSTS_BIST_MASK 0x0000f000
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#define AGCSTS_STATUS_MASK 0x000000ff
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#define AGCSTS_TCZERO_MASK 0x000000c0
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#define AGCSTS_FIFO_ST_MASK 0x0000003f
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#define AGCSTS_TC_ENABLE 0x10000000
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#define AGCSTS_RESET_MBFLAGS 0x08000000
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#define AGCSTS_RESET_P2A_FIFO 0x04000000
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#define AGCSTS_RESET_A2P_FIFO 0x02000000
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#define AGCSTS_RESET_FIFOS (AGCSTS_RESET_A2P_FIFO | AGCSTS_RESET_P2A_FIFO)
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#define AGCSTS_A2P_TCOUNT 0x00000080
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#define AGCSTS_P2A_TCOUNT 0x00000040
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#define AGCSTS_FS_P2A_EMPTY 0x00000020
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#define AGCSTS_FS_P2A_HALF 0x00000010
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#define AGCSTS_FS_P2A_FULL 0x00000008
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#define AGCSTS_FS_A2P_EMPTY 0x00000004
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#define AGCSTS_FS_A2P_HALF 0x00000002
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#define AGCSTS_FS_A2P_FULL 0x00000001
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/****************************************************************************/
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/* AMCC - Add-on Interrupt Control/Status Register */
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/****************************************************************************/
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#define AINT_INT_MASK 0x00ff0000
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#define AINT_SEL_MASK 0x0000ffff
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#define AINT_IS_ENSEL_MASK 0x00001f1f
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#define AINT_INT_ASSERTED 0x00800000
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#define AINT_BM_ERROR 0x00200000
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#define AINT_BIST_INT 0x00100000
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#define AINT_RT_COMPLETE 0x00080000
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#define AINT_WT_COMPLETE 0x00040000
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#define AINT_OUT_MB_INT 0x00020000
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#define AINT_IN_MB_INT 0x00010000
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#define AINT_READ_COMPL 0x00008000
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#define AINT_WRITE_COMPL 0x00004000
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#define AINT_OMB_ENABLE 0x00001000
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#define AINT_OMB_SELECT 0x00000c00
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#define AINT_OMB_BYTE 0x00000300
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#define AINT_IMB_ENABLE 0x00000010
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#define AINT_IMB_SELECT 0x0000000c
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#define AINT_IMB_BYTE 0x00000003
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/* these are bits from various different registers, needs cleanup XXX */
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/* Enable Bus Mastering */
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#define EN_A2P_TRANSFERS 0x00000400
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/* FIFO Flag Reset */
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#define RESET_A2P_FLAGS 0x04000000L
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/* FIFO Relative Priority */
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#define A2P_HI_PRIORITY 0x00000100L
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/* Identify Interrupt Sources */
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#define ANY_S593X_INT 0x00800000L
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#define READ_TC_INT 0x00080000L
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#define WRITE_TC_INT 0x00040000L
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#define IN_MB_INT 0x00020000L
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#define MASTER_ABORT_INT 0x00100000L
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#define TARGET_ABORT_INT 0x00200000L
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#define BUS_MASTER_INT 0x00200000L
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#endif
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