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2a709f28fa
* 0day explit mitigation * Memory corruption prevention * Privilege escalation prevention * Buffer over flow prevention * File System corruption defense * Thread escape prevention This may very well be the most intensive inclusion to BrooklynR. This will not be part of an x86 suite nor it will be released as tool kit. The security core toolkit will remain part of kernel base.
533 lines
18 KiB
C
533 lines
18 KiB
C
/*
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* max77693-private.h - Voltage regulator driver for the Maxim 77693
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*
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* Copyright (C) 2012 Samsung Electrnoics
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* SangYoung Son <hello.son@samsung.com>
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*
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* This program is not provided / owned by Maxim Integrated Products.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __LINUX_MFD_MAX77693_PRIV_H
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#define __LINUX_MFD_MAX77693_PRIV_H
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#include <linux/i2c.h>
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#define MAX77693_REG_INVALID (0xff)
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/* Slave addr = 0xCC: PMIC, Charger, Flash LED */
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enum max77693_pmic_reg {
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MAX77693_LED_REG_IFLASH1 = 0x00,
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MAX77693_LED_REG_IFLASH2 = 0x01,
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MAX77693_LED_REG_ITORCH = 0x02,
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MAX77693_LED_REG_ITORCHTIMER = 0x03,
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MAX77693_LED_REG_FLASH_TIMER = 0x04,
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MAX77693_LED_REG_FLASH_EN = 0x05,
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MAX77693_LED_REG_MAX_FLASH1 = 0x06,
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MAX77693_LED_REG_MAX_FLASH2 = 0x07,
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MAX77693_LED_REG_MAX_FLASH3 = 0x08,
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MAX77693_LED_REG_MAX_FLASH4 = 0x09,
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MAX77693_LED_REG_VOUT_CNTL = 0x0A,
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MAX77693_LED_REG_VOUT_FLASH1 = 0x0B,
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MAX77693_LED_REG_VOUT_FLASH2 = 0x0C,
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MAX77693_LED_REG_FLASH_INT = 0x0E,
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MAX77693_LED_REG_FLASH_INT_MASK = 0x0F,
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MAX77693_LED_REG_FLASH_STATUS = 0x10,
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MAX77693_PMIC_REG_PMIC_ID1 = 0x20,
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MAX77693_PMIC_REG_PMIC_ID2 = 0x21,
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MAX77693_PMIC_REG_INTSRC = 0x22,
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MAX77693_PMIC_REG_INTSRC_MASK = 0x23,
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MAX77693_PMIC_REG_TOPSYS_INT = 0x24,
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MAX77693_PMIC_REG_TOPSYS_INT_MASK = 0x26,
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MAX77693_PMIC_REG_TOPSYS_STAT = 0x28,
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MAX77693_PMIC_REG_MAINCTRL1 = 0x2A,
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MAX77693_PMIC_REG_LSCNFG = 0x2B,
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MAX77693_CHG_REG_CHG_INT = 0xB0,
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MAX77693_CHG_REG_CHG_INT_MASK = 0xB1,
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MAX77693_CHG_REG_CHG_INT_OK = 0xB2,
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MAX77693_CHG_REG_CHG_DETAILS_00 = 0xB3,
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MAX77693_CHG_REG_CHG_DETAILS_01 = 0xB4,
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MAX77693_CHG_REG_CHG_DETAILS_02 = 0xB5,
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MAX77693_CHG_REG_CHG_DETAILS_03 = 0xB6,
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MAX77693_CHG_REG_CHG_CNFG_00 = 0xB7,
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MAX77693_CHG_REG_CHG_CNFG_01 = 0xB8,
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MAX77693_CHG_REG_CHG_CNFG_02 = 0xB9,
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MAX77693_CHG_REG_CHG_CNFG_03 = 0xBA,
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MAX77693_CHG_REG_CHG_CNFG_04 = 0xBB,
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MAX77693_CHG_REG_CHG_CNFG_05 = 0xBC,
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MAX77693_CHG_REG_CHG_CNFG_06 = 0xBD,
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MAX77693_CHG_REG_CHG_CNFG_07 = 0xBE,
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MAX77693_CHG_REG_CHG_CNFG_08 = 0xBF,
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MAX77693_CHG_REG_CHG_CNFG_09 = 0xC0,
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MAX77693_CHG_REG_CHG_CNFG_10 = 0xC1,
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MAX77693_CHG_REG_CHG_CNFG_11 = 0xC2,
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MAX77693_CHG_REG_CHG_CNFG_12 = 0xC3,
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MAX77693_CHG_REG_CHG_CNFG_13 = 0xC4,
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MAX77693_CHG_REG_CHG_CNFG_14 = 0xC5,
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MAX77693_CHG_REG_SAFEOUT_CTRL = 0xC6,
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MAX77693_PMIC_REG_END,
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};
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/* MAX77693 ITORCH register */
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#define TORCH_IOUT1_SHIFT 0
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#define TORCH_IOUT2_SHIFT 4
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#define TORCH_IOUT_MASK(x) (0xf << (x))
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#define TORCH_IOUT_MIN 15625
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#define TORCH_IOUT_MAX 250000
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#define TORCH_IOUT_STEP 15625
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/* MAX77693 IFLASH1 and IFLASH2 registers */
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#define FLASH_IOUT_MIN 15625
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#define FLASH_IOUT_MAX_1LED 1000000
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#define FLASH_IOUT_MAX_2LEDS 625000
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#define FLASH_IOUT_STEP 15625
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/* MAX77693 TORCH_TIMER register */
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#define TORCH_TMR_NO_TIMER 0x40
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#define TORCH_TIMEOUT_MIN 262000
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#define TORCH_TIMEOUT_MAX 15728000
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/* MAX77693 FLASH_TIMER register */
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#define FLASH_TMR_LEVEL 0x80
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#define FLASH_TIMEOUT_MIN 62500
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#define FLASH_TIMEOUT_MAX 1000000
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#define FLASH_TIMEOUT_STEP 62500
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/* MAX77693 FLASH_EN register */
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#define FLASH_EN_OFF 0x0
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#define FLASH_EN_FLASH 0x1
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#define FLASH_EN_TORCH 0x2
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#define FLASH_EN_ON 0x3
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#define FLASH_EN_SHIFT(x) (6 - (x) * 2)
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#define TORCH_EN_SHIFT(x) (2 - (x) * 2)
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/* MAX77693 MAX_FLASH1 register */
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#define MAX_FLASH1_MAX_FL_EN 0x80
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#define MAX_FLASH1_VSYS_MIN 2400
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#define MAX_FLASH1_VSYS_MAX 3400
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#define MAX_FLASH1_VSYS_STEP 33
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/* MAX77693 VOUT_CNTL register */
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#define FLASH_BOOST_FIXED 0x04
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#define FLASH_BOOST_LEDNUM_2 0x80
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/* MAX77693 VOUT_FLASH1 register */
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#define FLASH_VOUT_MIN 3300
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#define FLASH_VOUT_MAX 5500
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#define FLASH_VOUT_STEP 25
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#define FLASH_VOUT_RMIN 0x0c
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/* MAX77693 FLASH_STATUS register */
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#define FLASH_STATUS_FLASH_ON BIT(3)
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#define FLASH_STATUS_TORCH_ON BIT(2)
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/* MAX77693 FLASH_INT register */
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#define FLASH_INT_FLED2_OPEN BIT(0)
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#define FLASH_INT_FLED2_SHORT BIT(1)
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#define FLASH_INT_FLED1_OPEN BIT(2)
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#define FLASH_INT_FLED1_SHORT BIT(3)
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#define FLASH_INT_OVER_CURRENT BIT(4)
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/* Fast charge timer in in hours */
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#define DEFAULT_FAST_CHARGE_TIMER 4
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/* microamps */
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#define DEFAULT_TOP_OFF_THRESHOLD_CURRENT 150000
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/* minutes */
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#define DEFAULT_TOP_OFF_TIMER 30
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/* microvolts */
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#define DEFAULT_CONSTANT_VOLT 4200000
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/* microvolts */
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#define DEFAULT_MIN_SYSTEM_VOLT 3600000
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/* celsius */
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#define DEFAULT_THERMAL_REGULATION_TEMP 100
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/* microamps */
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#define DEFAULT_BATTERY_OVERCURRENT 3500000
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/* microvolts */
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#define DEFAULT_CHARGER_INPUT_THRESHOLD_VOLT 4300000
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/* MAX77693_CHG_REG_CHG_INT_OK register */
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#define CHG_INT_OK_BYP_SHIFT 0
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#define CHG_INT_OK_BAT_SHIFT 3
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#define CHG_INT_OK_CHG_SHIFT 4
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#define CHG_INT_OK_CHGIN_SHIFT 6
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#define CHG_INT_OK_DETBAT_SHIFT 7
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#define CHG_INT_OK_BYP_MASK BIT(CHG_INT_OK_BYP_SHIFT)
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#define CHG_INT_OK_BAT_MASK BIT(CHG_INT_OK_BAT_SHIFT)
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#define CHG_INT_OK_CHG_MASK BIT(CHG_INT_OK_CHG_SHIFT)
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#define CHG_INT_OK_CHGIN_MASK BIT(CHG_INT_OK_CHGIN_SHIFT)
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#define CHG_INT_OK_DETBAT_MASK BIT(CHG_INT_OK_DETBAT_SHIFT)
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/* MAX77693_CHG_REG_CHG_DETAILS_00 register */
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#define CHG_DETAILS_00_CHGIN_SHIFT 5
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#define CHG_DETAILS_00_CHGIN_MASK (0x3 << CHG_DETAILS_00_CHGIN_SHIFT)
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/* MAX77693_CHG_REG_CHG_DETAILS_01 register */
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#define CHG_DETAILS_01_CHG_SHIFT 0
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#define CHG_DETAILS_01_BAT_SHIFT 4
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#define CHG_DETAILS_01_TREG_SHIFT 7
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#define CHG_DETAILS_01_CHG_MASK (0xf << CHG_DETAILS_01_CHG_SHIFT)
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#define CHG_DETAILS_01_BAT_MASK (0x7 << CHG_DETAILS_01_BAT_SHIFT)
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#define CHG_DETAILS_01_TREG_MASK BIT(7)
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/* MAX77693_CHG_REG_CHG_DETAILS_01/CHG field */
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enum max77693_charger_charging_state {
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MAX77693_CHARGING_PREQUALIFICATION = 0x0,
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MAX77693_CHARGING_FAST_CONST_CURRENT,
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MAX77693_CHARGING_FAST_CONST_VOLTAGE,
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MAX77693_CHARGING_TOP_OFF,
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MAX77693_CHARGING_DONE,
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MAX77693_CHARGING_HIGH_TEMP,
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MAX77693_CHARGING_TIMER_EXPIRED,
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MAX77693_CHARGING_THERMISTOR_SUSPEND,
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MAX77693_CHARGING_OFF,
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MAX77693_CHARGING_RESERVED,
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MAX77693_CHARGING_OVER_TEMP,
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MAX77693_CHARGING_WATCHDOG_EXPIRED,
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};
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/* MAX77693_CHG_REG_CHG_DETAILS_01/BAT field */
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enum max77693_charger_battery_state {
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MAX77693_BATTERY_NOBAT = 0x0,
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/* Dead-battery or low-battery prequalification */
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MAX77693_BATTERY_PREQUALIFICATION,
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MAX77693_BATTERY_TIMER_EXPIRED,
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MAX77693_BATTERY_GOOD,
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MAX77693_BATTERY_LOWVOLTAGE,
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MAX77693_BATTERY_OVERVOLTAGE,
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MAX77693_BATTERY_OVERCURRENT,
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MAX77693_BATTERY_RESERVED,
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};
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/* MAX77693_CHG_REG_CHG_DETAILS_02 register */
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#define CHG_DETAILS_02_BYP_SHIFT 0
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#define CHG_DETAILS_02_BYP_MASK (0xf << CHG_DETAILS_02_BYP_SHIFT)
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/* MAX77693 CHG_CNFG_00 register */
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#define CHG_CNFG_00_CHG_MASK 0x1
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#define CHG_CNFG_00_BUCK_MASK 0x4
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/* MAX77693_CHG_REG_CHG_CNFG_01 register */
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#define CHG_CNFG_01_FCHGTIME_SHIFT 0
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#define CHG_CNFG_01_CHGRSTRT_SHIFT 4
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#define CHG_CNFG_01_PQEN_SHIFT 7
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#define CHG_CNFG_01_FCHGTIME_MASK (0x7 << CHG_CNFG_01_FCHGTIME_SHIFT)
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#define CHG_CNFG_01_CHGRSTRT_MASK (0x3 << CHG_CNFG_01_CHGRSTRT_SHIFT)
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#define CHG_CNFG_01_PQEN_MAKS BIT(CHG_CNFG_01_PQEN_SHIFT)
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/* MAX77693_CHG_REG_CHG_CNFG_03 register */
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#define CHG_CNFG_03_TOITH_SHIFT 0
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#define CHG_CNFG_03_TOTIME_SHIFT 3
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#define CHG_CNFG_03_TOITH_MASK (0x7 << CHG_CNFG_03_TOITH_SHIFT)
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#define CHG_CNFG_03_TOTIME_MASK (0x7 << CHG_CNFG_03_TOTIME_SHIFT)
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/* MAX77693_CHG_REG_CHG_CNFG_04 register */
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#define CHG_CNFG_04_CHGCVPRM_SHIFT 0
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#define CHG_CNFG_04_MINVSYS_SHIFT 5
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#define CHG_CNFG_04_CHGCVPRM_MASK (0x1f << CHG_CNFG_04_CHGCVPRM_SHIFT)
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#define CHG_CNFG_04_MINVSYS_MASK (0x7 << CHG_CNFG_04_MINVSYS_SHIFT)
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/* MAX77693_CHG_REG_CHG_CNFG_06 register */
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#define CHG_CNFG_06_CHGPROT_SHIFT 2
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#define CHG_CNFG_06_CHGPROT_MASK (0x3 << CHG_CNFG_06_CHGPROT_SHIFT)
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/* MAX77693_CHG_REG_CHG_CNFG_07 register */
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#define CHG_CNFG_07_REGTEMP_SHIFT 5
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#define CHG_CNFG_07_REGTEMP_MASK (0x3 << CHG_CNFG_07_REGTEMP_SHIFT)
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/* MAX77693_CHG_REG_CHG_CNFG_12 register */
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#define CHG_CNFG_12_B2SOVRC_SHIFT 0
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#define CHG_CNFG_12_VCHGINREG_SHIFT 3
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#define CHG_CNFG_12_B2SOVRC_MASK (0x7 << CHG_CNFG_12_B2SOVRC_SHIFT)
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#define CHG_CNFG_12_VCHGINREG_MASK (0x3 << CHG_CNFG_12_VCHGINREG_SHIFT)
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/* MAX77693 CHG_CNFG_09 Register */
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#define CHG_CNFG_09_CHGIN_ILIM_MASK 0x7F
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/* MAX77693 CHG_CTRL Register */
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#define SAFEOUT_CTRL_SAFEOUT1_MASK 0x3
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#define SAFEOUT_CTRL_SAFEOUT2_MASK 0xC
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#define SAFEOUT_CTRL_ENSAFEOUT1_MASK 0x40
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#define SAFEOUT_CTRL_ENSAFEOUT2_MASK 0x80
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/* Slave addr = 0x4A: MUIC */
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enum max77693_muic_reg {
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MAX77693_MUIC_REG_ID = 0x00,
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MAX77693_MUIC_REG_INT1 = 0x01,
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MAX77693_MUIC_REG_INT2 = 0x02,
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MAX77693_MUIC_REG_INT3 = 0x03,
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MAX77693_MUIC_REG_STATUS1 = 0x04,
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MAX77693_MUIC_REG_STATUS2 = 0x05,
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MAX77693_MUIC_REG_STATUS3 = 0x06,
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MAX77693_MUIC_REG_INTMASK1 = 0x07,
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MAX77693_MUIC_REG_INTMASK2 = 0x08,
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MAX77693_MUIC_REG_INTMASK3 = 0x09,
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MAX77693_MUIC_REG_CDETCTRL1 = 0x0A,
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MAX77693_MUIC_REG_CDETCTRL2 = 0x0B,
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MAX77693_MUIC_REG_CTRL1 = 0x0C,
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MAX77693_MUIC_REG_CTRL2 = 0x0D,
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MAX77693_MUIC_REG_CTRL3 = 0x0E,
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MAX77693_MUIC_REG_END,
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};
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/* MAX77693 INTMASK1~2 Register */
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#define INTMASK1_ADC1K_SHIFT 3
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#define INTMASK1_ADCERR_SHIFT 2
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#define INTMASK1_ADCLOW_SHIFT 1
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#define INTMASK1_ADC_SHIFT 0
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#define INTMASK1_ADC1K_MASK (1 << INTMASK1_ADC1K_SHIFT)
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#define INTMASK1_ADCERR_MASK (1 << INTMASK1_ADCERR_SHIFT)
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#define INTMASK1_ADCLOW_MASK (1 << INTMASK1_ADCLOW_SHIFT)
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#define INTMASK1_ADC_MASK (1 << INTMASK1_ADC_SHIFT)
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#define INTMASK2_VIDRM_SHIFT 5
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#define INTMASK2_VBVOLT_SHIFT 4
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#define INTMASK2_DXOVP_SHIFT 3
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#define INTMASK2_DCDTMR_SHIFT 2
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#define INTMASK2_CHGDETRUN_SHIFT 1
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#define INTMASK2_CHGTYP_SHIFT 0
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#define INTMASK2_VIDRM_MASK (1 << INTMASK2_VIDRM_SHIFT)
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#define INTMASK2_VBVOLT_MASK (1 << INTMASK2_VBVOLT_SHIFT)
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#define INTMASK2_DXOVP_MASK (1 << INTMASK2_DXOVP_SHIFT)
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#define INTMASK2_DCDTMR_MASK (1 << INTMASK2_DCDTMR_SHIFT)
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#define INTMASK2_CHGDETRUN_MASK (1 << INTMASK2_CHGDETRUN_SHIFT)
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#define INTMASK2_CHGTYP_MASK (1 << INTMASK2_CHGTYP_SHIFT)
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/* MAX77693 MUIC - STATUS1~3 Register */
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#define MAX77693_STATUS1_ADC_SHIFT 0
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#define MAX77693_STATUS1_ADCLOW_SHIFT 5
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#define MAX77693_STATUS1_ADCERR_SHIFT 6
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#define MAX77693_STATUS1_ADC1K_SHIFT 7
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#define MAX77693_STATUS1_ADC_MASK (0x1f << MAX77693_STATUS1_ADC_SHIFT)
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#define MAX77693_STATUS1_ADCLOW_MASK BIT(MAX77693_STATUS1_ADCLOW_SHIFT)
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#define MAX77693_STATUS1_ADCERR_MASK BIT(MAX77693_STATUS1_ADCERR_SHIFT)
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#define MAX77693_STATUS1_ADC1K_MASK BIT(MAX77693_STATUS1_ADC1K_SHIFT)
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#define MAX77693_STATUS2_CHGTYP_SHIFT 0
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#define MAX77693_STATUS2_CHGDETRUN_SHIFT 3
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#define MAX77693_STATUS2_DCDTMR_SHIFT 4
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#define MAX77693_STATUS2_DXOVP_SHIFT 5
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#define MAX77693_STATUS2_VBVOLT_SHIFT 6
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#define MAX77693_STATUS2_VIDRM_SHIFT 7
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#define MAX77693_STATUS2_CHGTYP_MASK (0x7 << MAX77693_STATUS2_CHGTYP_SHIFT)
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#define MAX77693_STATUS2_CHGDETRUN_MASK BIT(MAX77693_STATUS2_CHGDETRUN_SHIFT)
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#define MAX77693_STATUS2_DCDTMR_MASK BIT(MAX77693_STATUS2_DCDTMR_SHIFT)
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#define MAX77693_STATUS2_DXOVP_MASK BIT(MAX77693_STATUS2_DXOVP_SHIFT)
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#define MAX77693_STATUS2_VBVOLT_MASK BIT(MAX77693_STATUS2_VBVOLT_SHIFT)
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#define MAX77693_STATUS2_VIDRM_MASK BIT(MAX77693_STATUS2_VIDRM_SHIFT)
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#define MAX77693_STATUS3_OVP_SHIFT 2
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#define MAX77693_STATUS3_OVP_MASK BIT(MAX77693_STATUS3_OVP_SHIFT)
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/* MAX77693 CDETCTRL1~2 register */
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#define CDETCTRL1_CHGDETEN_SHIFT (0)
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#define CDETCTRL1_CHGTYPMAN_SHIFT (1)
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#define CDETCTRL1_DCDEN_SHIFT (2)
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#define CDETCTRL1_DCD2SCT_SHIFT (3)
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#define CDETCTRL1_CDDELAY_SHIFT (4)
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#define CDETCTRL1_DCDCPL_SHIFT (5)
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#define CDETCTRL1_CDPDET_SHIFT (7)
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#define CDETCTRL1_CHGDETEN_MASK (0x1 << CDETCTRL1_CHGDETEN_SHIFT)
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#define CDETCTRL1_CHGTYPMAN_MASK (0x1 << CDETCTRL1_CHGTYPMAN_SHIFT)
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#define CDETCTRL1_DCDEN_MASK (0x1 << CDETCTRL1_DCDEN_SHIFT)
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#define CDETCTRL1_DCD2SCT_MASK (0x1 << CDETCTRL1_DCD2SCT_SHIFT)
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#define CDETCTRL1_CDDELAY_MASK (0x1 << CDETCTRL1_CDDELAY_SHIFT)
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#define CDETCTRL1_DCDCPL_MASK (0x1 << CDETCTRL1_DCDCPL_SHIFT)
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#define CDETCTRL1_CDPDET_MASK (0x1 << CDETCTRL1_CDPDET_SHIFT)
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#define CDETCTRL2_VIDRMEN_SHIFT (1)
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#define CDETCTRL2_DXOVPEN_SHIFT (3)
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#define CDETCTRL2_VIDRMEN_MASK (0x1 << CDETCTRL2_VIDRMEN_SHIFT)
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#define CDETCTRL2_DXOVPEN_MASK (0x1 << CDETCTRL2_DXOVPEN_SHIFT)
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/* MAX77693 MUIC - CONTROL1~3 register */
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#define COMN1SW_SHIFT (0)
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#define COMP2SW_SHIFT (3)
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#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
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#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
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#define COMP_SW_MASK (COMP2SW_MASK | COMN1SW_MASK)
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#define MAX77693_CONTROL1_SW_USB ((1 << COMP2SW_SHIFT) \
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| (1 << COMN1SW_SHIFT))
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#define MAX77693_CONTROL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \
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| (2 << COMN1SW_SHIFT))
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#define MAX77693_CONTROL1_SW_UART ((3 << COMP2SW_SHIFT) \
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| (3 << COMN1SW_SHIFT))
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#define MAX77693_CONTROL1_SW_OPEN ((0 << COMP2SW_SHIFT) \
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| (0 << COMN1SW_SHIFT))
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#define MAX77693_CONTROL2_LOWPWR_SHIFT 0
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#define MAX77693_CONTROL2_ADCEN_SHIFT 1
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#define MAX77693_CONTROL2_CPEN_SHIFT 2
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#define MAX77693_CONTROL2_SFOUTASRT_SHIFT 3
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#define MAX77693_CONTROL2_SFOUTORD_SHIFT 4
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#define MAX77693_CONTROL2_ACCDET_SHIFT 5
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#define MAX77693_CONTROL2_USBCPINT_SHIFT 6
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#define MAX77693_CONTROL2_RCPS_SHIFT 7
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#define MAX77693_CONTROL2_LOWPWR_MASK BIT(MAX77693_CONTROL2_LOWPWR_SHIFT)
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#define MAX77693_CONTROL2_ADCEN_MASK BIT(MAX77693_CONTROL2_ADCEN_SHIFT)
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#define MAX77693_CONTROL2_CPEN_MASK BIT(MAX77693_CONTROL2_CPEN_SHIFT)
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#define MAX77693_CONTROL2_SFOUTASRT_MASK BIT(MAX77693_CONTROL2_SFOUTASRT_SHIFT)
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#define MAX77693_CONTROL2_SFOUTORD_MASK BIT(MAX77693_CONTROL2_SFOUTORD_SHIFT)
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#define MAX77693_CONTROL2_ACCDET_MASK BIT(MAX77693_CONTROL2_ACCDET_SHIFT)
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#define MAX77693_CONTROL2_USBCPINT_MASK BIT(MAX77693_CONTROL2_USBCPINT_SHIFT)
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#define MAX77693_CONTROL2_RCPS_MASK BIT(MAX77693_CONTROL2_RCPS_SHIFT)
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#define MAX77693_CONTROL3_JIGSET_SHIFT 0
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#define MAX77693_CONTROL3_BTLDSET_SHIFT 2
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#define MAX77693_CONTROL3_ADCDBSET_SHIFT 4
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#define MAX77693_CONTROL3_JIGSET_MASK (0x3 << MAX77693_CONTROL3_JIGSET_SHIFT)
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#define MAX77693_CONTROL3_BTLDSET_MASK (0x3 << MAX77693_CONTROL3_BTLDSET_SHIFT)
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#define MAX77693_CONTROL3_ADCDBSET_MASK (0x3 << MAX77693_CONTROL3_ADCDBSET_SHIFT)
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/* Slave addr = 0x90: Haptic */
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enum max77693_haptic_reg {
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MAX77693_HAPTIC_REG_STATUS = 0x00,
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MAX77693_HAPTIC_REG_CONFIG1 = 0x01,
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MAX77693_HAPTIC_REG_CONFIG2 = 0x02,
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MAX77693_HAPTIC_REG_CONFIG_CHNL = 0x03,
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MAX77693_HAPTIC_REG_CONFG_CYC1 = 0x04,
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MAX77693_HAPTIC_REG_CONFG_CYC2 = 0x05,
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MAX77693_HAPTIC_REG_CONFIG_PER1 = 0x06,
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MAX77693_HAPTIC_REG_CONFIG_PER2 = 0x07,
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MAX77693_HAPTIC_REG_CONFIG_PER3 = 0x08,
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MAX77693_HAPTIC_REG_CONFIG_PER4 = 0x09,
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MAX77693_HAPTIC_REG_CONFIG_DUTY1 = 0x0A,
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MAX77693_HAPTIC_REG_CONFIG_DUTY2 = 0x0B,
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MAX77693_HAPTIC_REG_CONFIG_PWM1 = 0x0C,
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MAX77693_HAPTIC_REG_CONFIG_PWM2 = 0x0D,
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MAX77693_HAPTIC_REG_CONFIG_PWM3 = 0x0E,
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MAX77693_HAPTIC_REG_CONFIG_PWM4 = 0x0F,
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MAX77693_HAPTIC_REG_REV = 0x10,
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MAX77693_HAPTIC_REG_END,
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};
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/* max77693-pmic LSCNFG configuraton register */
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#define MAX77693_PMIC_LOW_SYS_MASK 0x80
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#define MAX77693_PMIC_LOW_SYS_SHIFT 7
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|
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/* max77693-haptic configuration register */
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#define MAX77693_CONFIG2_MODE 7
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#define MAX77693_CONFIG2_MEN 6
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#define MAX77693_CONFIG2_HTYP 5
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enum max77693_irq_source {
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LED_INT = 0,
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TOPSYS_INT,
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CHG_INT,
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MUIC_INT1,
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MUIC_INT2,
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MUIC_INT3,
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MAX77693_IRQ_GROUP_NR,
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};
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#define SRC_IRQ_CHARGER BIT(0)
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#define SRC_IRQ_TOP BIT(1)
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#define SRC_IRQ_FLASH BIT(2)
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#define SRC_IRQ_MUIC BIT(3)
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#define SRC_IRQ_ALL (SRC_IRQ_CHARGER | SRC_IRQ_TOP \
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| SRC_IRQ_FLASH | SRC_IRQ_MUIC)
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|
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#define LED_IRQ_FLED2_OPEN BIT(0)
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#define LED_IRQ_FLED2_SHORT BIT(1)
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#define LED_IRQ_FLED1_OPEN BIT(2)
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#define LED_IRQ_FLED1_SHORT BIT(3)
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#define LED_IRQ_MAX_FLASH BIT(4)
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|
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|
#define TOPSYS_IRQ_T120C_INT BIT(0)
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#define TOPSYS_IRQ_T140C_INT BIT(1)
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#define TOPSYS_IRQ_LOWSYS_INT BIT(3)
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|
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|
#define CHG_IRQ_BYP_I BIT(0)
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#define CHG_IRQ_THM_I BIT(2)
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#define CHG_IRQ_BAT_I BIT(3)
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#define CHG_IRQ_CHG_I BIT(4)
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|
#define CHG_IRQ_CHGIN_I BIT(6)
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|
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#define MUIC_IRQ_INT1_ADC BIT(0)
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#define MUIC_IRQ_INT1_ADC_LOW BIT(1)
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#define MUIC_IRQ_INT1_ADC_ERR BIT(2)
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#define MUIC_IRQ_INT1_ADC1K BIT(3)
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|
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|
#define MUIC_IRQ_INT2_CHGTYP BIT(0)
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#define MUIC_IRQ_INT2_CHGDETREUN BIT(1)
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#define MUIC_IRQ_INT2_DCDTMR BIT(2)
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#define MUIC_IRQ_INT2_DXOVP BIT(3)
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#define MUIC_IRQ_INT2_VBVOLT BIT(4)
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#define MUIC_IRQ_INT2_VIDRM BIT(5)
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|
|
|
#define MUIC_IRQ_INT3_EOC BIT(0)
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#define MUIC_IRQ_INT3_CGMBC BIT(1)
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#define MUIC_IRQ_INT3_OVP BIT(2)
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|
#define MUIC_IRQ_INT3_MBCCHG_ERR BIT(3)
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|
#define MUIC_IRQ_INT3_CHG_ENABLED BIT(4)
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|
#define MUIC_IRQ_INT3_BAT_DET BIT(5)
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|
|
|
enum max77693_irq {
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/* PMIC - FLASH */
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MAX77693_LED_IRQ_FLED2_OPEN,
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MAX77693_LED_IRQ_FLED2_SHORT,
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MAX77693_LED_IRQ_FLED1_OPEN,
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MAX77693_LED_IRQ_FLED1_SHORT,
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MAX77693_LED_IRQ_MAX_FLASH,
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|
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/* PMIC - TOPSYS */
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MAX77693_TOPSYS_IRQ_T120C_INT,
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MAX77693_TOPSYS_IRQ_T140C_INT,
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MAX77693_TOPSYS_IRQ_LOWSYS_INT,
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|
|
|
/* PMIC - Charger */
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|
MAX77693_CHG_IRQ_BYP_I,
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|
MAX77693_CHG_IRQ_THM_I,
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|
MAX77693_CHG_IRQ_BAT_I,
|
|
MAX77693_CHG_IRQ_CHG_I,
|
|
MAX77693_CHG_IRQ_CHGIN_I,
|
|
|
|
MAX77693_IRQ_NR,
|
|
};
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|
|
|
enum max77693_irq_muic {
|
|
/* MUIC INT1 */
|
|
MAX77693_MUIC_IRQ_INT1_ADC,
|
|
MAX77693_MUIC_IRQ_INT1_ADC_LOW,
|
|
MAX77693_MUIC_IRQ_INT1_ADC_ERR,
|
|
MAX77693_MUIC_IRQ_INT1_ADC1K,
|
|
|
|
/* MUIC INT2 */
|
|
MAX77693_MUIC_IRQ_INT2_CHGTYP,
|
|
MAX77693_MUIC_IRQ_INT2_CHGDETREUN,
|
|
MAX77693_MUIC_IRQ_INT2_DCDTMR,
|
|
MAX77693_MUIC_IRQ_INT2_DXOVP,
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|
MAX77693_MUIC_IRQ_INT2_VBVOLT,
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|
MAX77693_MUIC_IRQ_INT2_VIDRM,
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|
|
|
/* MUIC INT3 */
|
|
MAX77693_MUIC_IRQ_INT3_EOC,
|
|
MAX77693_MUIC_IRQ_INT3_CGMBC,
|
|
MAX77693_MUIC_IRQ_INT3_OVP,
|
|
MAX77693_MUIC_IRQ_INT3_MBCCHG_ERR,
|
|
MAX77693_MUIC_IRQ_INT3_CHG_ENABLED,
|
|
MAX77693_MUIC_IRQ_INT3_BAT_DET,
|
|
|
|
MAX77693_MUIC_IRQ_NR,
|
|
};
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|
#endif /* __LINUX_MFD_MAX77693_PRIV_H */
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