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mirror of https://github.com/Qortal/Brooklyn.git synced 2025-02-15 03:35:55 +00:00
Scare Crowe 7d3018da4c First of all. T3Q is a fucking slut whore. Next, Core 2.0 optimizations
* NVME, SATA NAND Security added
* Qortal Core exception fetcher is now redone.
* Update DT overlays for firmware
* Fix for bvb clockj settings
* Fix for no audio for sissy desktop porn watchers -_- ( thanks crowetic for watching gay porn and reporting me that bug asshat )
* Normalize the fetch() stream while doing a peer to peer handshake for nodes
* Fix for RNG token editing error while performing a SHA256 encryption
* Now under voltage errors will blink red led constantly for 5 minutes then go solid.
* Improve kernel thread scaling for Qortal 2.0 core
* HDMI circuit is now enabled at power up instead.
* Added KMS
* Added line replication instead of interpolation for VC4 GPU resulting in slightly better frame rates
* Fix for long and doubles
* Backplane clock is now set at standard rate
* Capped HVEC clocks
* Add support for Creative Cinema webcam for donkers who like sharing dick pics.  *looks at crowetic*
* More scanline XGA modes for people who have weird ass monitors of all sorts.
* TX/RX flow control support is now 100% stable. No lags over 1Gbps ethernet. ( Hello Qortal 3.0 )
* Using flush cache instead of fetch for QC 2.0 resulting in performance gains
* VC4 clock is now enforced for desktop oriented images.
* Ondemand governor now waits for 2 seconds instead of 0.5ms to scale down to the lowest safest clock freq preventing lags to the core.
* Timeout of OC set at 35ms from 90ms resulting in way better clocks and sync for Qortal 2.0 core
2021-10-20 18:55:35 +05:00

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1.8 KiB
C

/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
* Copyright (C) 2018 David Abdurachmanov <david.abdurachmanov@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#ifdef __LP64__
#define __ARCH_WANT_NEW_STAT
#define __ARCH_WANT_SET_GET_RLIMIT
#endif /* __LP64__ */
#define __ARCH_WANT_SYS_CLONE3
#include <asm-generic/unistd.h>
/*
* Allows the instruction cache to be flushed from userspace. Despite RISC-V
* having a direct 'fence.i' instruction available to userspace (which we
* can't trap!), that's not actually viable when running on Linux because the
* kernel might schedule a process on another hart. There is no way for
* userspace to handle this without invoking the kernel (as it doesn't know the
* thread->hart mappings), so we've defined a RISC-V specific system call to
* flush the instruction cache.
*
* __NR_riscv_flush_icache is defined to flush the instruction cache over an
* address range, with the flush applying to either all threads or just the
* caller. We don't currently do anything with the address range, that's just
* in there for forwards compatibility.
*/
#ifndef __NR_riscv_flush_icache
#define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15)
#endif
__SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache)