mirror of
https://github.com/Qortal/Brooklyn.git
synced 2025-02-08 07:13:06 +00:00
7d3018da4c
* NVME, SATA NAND Security added * Qortal Core exception fetcher is now redone. * Update DT overlays for firmware * Fix for bvb clockj settings * Fix for no audio for sissy desktop porn watchers -_- ( thanks crowetic for watching gay porn and reporting me that bug asshat ) * Normalize the fetch() stream while doing a peer to peer handshake for nodes * Fix for RNG token editing error while performing a SHA256 encryption * Now under voltage errors will blink red led constantly for 5 minutes then go solid. * Improve kernel thread scaling for Qortal 2.0 core * HDMI circuit is now enabled at power up instead. * Added KMS * Added line replication instead of interpolation for VC4 GPU resulting in slightly better frame rates * Fix for long and doubles * Backplane clock is now set at standard rate * Capped HVEC clocks * Add support for Creative Cinema webcam for donkers who like sharing dick pics. *looks at crowetic* * More scanline XGA modes for people who have weird ass monitors of all sorts. * TX/RX flow control support is now 100% stable. No lags over 1Gbps ethernet. ( Hello Qortal 3.0 ) * Using flush cache instead of fetch for QC 2.0 resulting in performance gains * VC4 clock is now enforced for desktop oriented images. * Ondemand governor now waits for 2 seconds instead of 0.5ms to scale down to the lowest safest clock freq preventing lags to the core. * Timeout of OC set at 35ms from 90ms resulting in way better clocks and sync for Qortal 2.0 core
99 lines
2.3 KiB
C
99 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only
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*
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* Copyright © 2018-2020 Intel Corporation
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*/
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#ifndef __KMB_DRV_H__
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#define __KMB_DRV_H__
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#include <drm/drm_device.h>
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#include "kmb_plane.h"
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#include "kmb_regs.h"
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#define KMB_MAX_WIDTH 1920 /*Max width in pixels */
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#define KMB_MAX_HEIGHT 1080 /*Max height in pixels */
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#define KMB_MIN_WIDTH 1920 /*Max width in pixels */
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#define KMB_MIN_HEIGHT 1080 /*Max height in pixels */
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#define DRIVER_DATE "20210223"
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#define DRIVER_MAJOR 1
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#define DRIVER_MINOR 1
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#define KMB_FB_MAX_WIDTH 1920
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#define KMB_FB_MAX_HEIGHT 1080
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#define KMB_FB_MIN_WIDTH 1
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#define KMB_FB_MIN_HEIGHT 1
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#define KMB_LCD_DEFAULT_CLK 200000000
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#define KMB_SYS_CLK_MHZ 500
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#define ICAM_MMIO 0x3b100000
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#define ICAM_LCD_OFFSET 0x1080
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#define ICAM_MMIO_SIZE 0x2000
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struct kmb_dsi;
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struct kmb_clock {
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struct clk *clk_lcd;
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struct clk *clk_pll0;
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};
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struct kmb_drm_private {
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struct drm_device drm;
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struct kmb_dsi *kmb_dsi;
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void __iomem *lcd_mmio;
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struct kmb_clock kmb_clk;
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struct drm_crtc crtc;
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struct kmb_plane *plane;
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struct drm_atomic_state *state;
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spinlock_t irq_lock;
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int irq_lcd;
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int sys_clk_mhz;
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struct layer_status plane_status[KMB_MAX_PLANES];
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int kmb_under_flow;
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int kmb_flush_done;
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int layer_no;
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};
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static inline struct kmb_drm_private *to_kmb(const struct drm_device *dev)
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{
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return container_of(dev, struct kmb_drm_private, drm);
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}
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static inline struct kmb_drm_private *crtc_to_kmb_priv(const struct drm_crtc *x)
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{
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return container_of(x, struct kmb_drm_private, crtc);
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}
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static inline void kmb_write_lcd(struct kmb_drm_private *dev_p,
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unsigned int reg, u32 value)
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{
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writel(value, (dev_p->lcd_mmio + reg));
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}
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static inline u32 kmb_read_lcd(struct kmb_drm_private *dev_p, unsigned int reg)
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{
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return readl(dev_p->lcd_mmio + reg);
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}
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static inline void kmb_set_bitmask_lcd(struct kmb_drm_private *dev_p,
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unsigned int reg, u32 mask)
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{
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u32 reg_val = kmb_read_lcd(dev_p, reg);
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kmb_write_lcd(dev_p, reg, (reg_val | mask));
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}
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static inline void kmb_clr_bitmask_lcd(struct kmb_drm_private *dev_p,
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unsigned int reg, u32 mask)
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{
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u32 reg_val = kmb_read_lcd(dev_p, reg);
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kmb_write_lcd(dev_p, reg, (reg_val & (~mask)));
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}
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int kmb_setup_crtc(struct drm_device *dev);
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void kmb_set_scanout(struct kmb_drm_private *lcd);
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#endif /* __KMB_DRV_H__ */
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