mirror of
https://github.com/Qortal/Brooklyn.git
synced 2025-02-07 23:03:06 +00:00
7d3018da4c
* NVME, SATA NAND Security added * Qortal Core exception fetcher is now redone. * Update DT overlays for firmware * Fix for bvb clockj settings * Fix for no audio for sissy desktop porn watchers -_- ( thanks crowetic for watching gay porn and reporting me that bug asshat ) * Normalize the fetch() stream while doing a peer to peer handshake for nodes * Fix for RNG token editing error while performing a SHA256 encryption * Now under voltage errors will blink red led constantly for 5 minutes then go solid. * Improve kernel thread scaling for Qortal 2.0 core * HDMI circuit is now enabled at power up instead. * Added KMS * Added line replication instead of interpolation for VC4 GPU resulting in slightly better frame rates * Fix for long and doubles * Backplane clock is now set at standard rate * Capped HVEC clocks * Add support for Creative Cinema webcam for donkers who like sharing dick pics. *looks at crowetic* * More scanline XGA modes for people who have weird ass monitors of all sorts. * TX/RX flow control support is now 100% stable. No lags over 1Gbps ethernet. ( Hello Qortal 3.0 ) * Using flush cache instead of fetch for QC 2.0 resulting in performance gains * VC4 clock is now enforced for desktop oriented images. * Ondemand governor now waits for 2 seconds instead of 0.5ms to scale down to the lowest safest clock freq preventing lags to the core. * Timeout of OC set at 35ms from 90ms resulting in way better clocks and sync for Qortal 2.0 core
72 lines
2.4 KiB
C
72 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright 2019 NXP
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*/
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#ifndef _MSCC_FELIX_H
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#define _MSCC_FELIX_H
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#define ocelot_to_felix(o) container_of((o), struct felix, ocelot)
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#define FELIX_MAC_QUIRKS OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION
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/* Platform-specific information */
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struct felix_info {
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const struct resource *target_io_res;
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const struct resource *port_io_res;
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const struct resource *imdio_res;
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const struct reg_field *regfields;
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const u32 *const *map;
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const struct ocelot_ops *ops;
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int num_mact_rows;
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const struct ocelot_stat_layout *stats_layout;
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unsigned int num_stats;
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int num_ports;
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int num_tx_queues;
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struct vcap_props *vcap;
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int switch_pci_bar;
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int imdio_pci_bar;
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const struct ptp_clock_info *ptp_caps;
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/* Some Ocelot switches are integrated into the SoC without the
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* extraction IRQ line connected to the ARM GIC. By enabling this
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* workaround, the few packets that are delivered to the CPU port
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* module (currently only PTP) are copied not only to the hardware CPU
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* port module, but also to the 802.1Q Ethernet CPU port, and polling
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* the extraction registers is triggered once the DSA tagger sees a PTP
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* frame. The Ethernet frame is only used as a notification: it is
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* dropped, and the original frame is extracted over MMIO and annotated
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* with the RX timestamp.
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*/
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bool quirk_no_xtr_irq;
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int (*mdio_bus_alloc)(struct ocelot *ocelot);
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void (*mdio_bus_free)(struct ocelot *ocelot);
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void (*phylink_validate)(struct ocelot *ocelot, int port,
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unsigned long *supported,
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struct phylink_link_state *state);
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int (*prevalidate_phy_mode)(struct ocelot *ocelot, int port,
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phy_interface_t phy_mode);
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int (*port_setup_tc)(struct dsa_switch *ds, int port,
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enum tc_setup_type type, void *type_data);
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void (*port_sched_speed_set)(struct ocelot *ocelot, int port,
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u32 speed);
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};
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extern const struct dsa_switch_ops felix_switch_ops;
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/* DSA glue / front-end for struct ocelot */
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struct felix {
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struct dsa_switch *ds;
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const struct felix_info *info;
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struct ocelot ocelot;
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struct mii_bus *imdio;
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struct lynx_pcs **pcs;
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resource_size_t switch_base;
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resource_size_t imdio_base;
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enum dsa_tag_protocol tag_proto;
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struct kthread_worker *xmit_worker;
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};
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struct net_device *felix_port_to_netdev(struct ocelot *ocelot, int port);
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int felix_netdev_to_port(struct net_device *dev);
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#endif
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