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a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
62 lines
1.6 KiB
YAML
62 lines
1.6 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/qca,ath79-ddr-controller.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller
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maintainers:
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- Krzysztof Kozlowski <krzk@kernel.org>
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description: |
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The DDR controller of the AR7xxx and AR9xxx families provides an interface to
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flush the FIFO between various devices and the DDR. This is mainly used by
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the IRQ controller to flush the FIFO before running the interrupt handler of
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such devices.
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properties:
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compatible:
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oneOf:
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- items:
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- const: qca,ar9132-ddr-controller
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- const: qca,ar7240-ddr-controller
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- items:
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- enum:
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- qca,ar7100-ddr-controller
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- qca,ar7240-ddr-controller
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"#qca,ddr-wb-channel-cells":
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description: |
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Specifies the number of cells needed to encode the write buffer channel
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index.
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$ref: /schemas/types.yaml#/definitions/uint32
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- "#qca,ddr-wb-channel-cells"
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- reg
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additionalProperties: false
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examples:
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- |
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ddr_ctrl: memory-controller@18000000 {
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compatible = "qca,ar9132-ddr-controller",
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"qca,ar7240-ddr-controller";
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reg = <0x18000000 0x100>;
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#qca,ddr-wb-channel-cells = <1>;
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};
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interrupt-controller {
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// ...
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qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
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qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
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<&ddr_ctrl 0>, <&ddr_ctrl 1>;
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};
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