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99 lines
2.9 KiB
C
99 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
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*/
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#include <asm/hwcap.h>
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#include <asm/neon.h>
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#if defined(CONFIG_ZINC_ARCH_ARM)
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#include <asm/system_info.h>
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#include <asm/cputype.h>
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#endif
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asmlinkage void chacha20_arm(u8 *out, const u8 *in, const size_t len,
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const u32 key[8], const u32 counter[4]);
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asmlinkage void hchacha20_arm(const u32 state[16], u32 out[8]);
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asmlinkage void chacha20_neon(u8 *out, const u8 *in, const size_t len,
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const u32 key[8], const u32 counter[4]);
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static bool chacha20_use_neon __ro_after_init;
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static bool *const chacha20_nobs[] __initconst = { &chacha20_use_neon };
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static void __init chacha20_fpu_init(void)
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{
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#if defined(CONFIG_ZINC_ARCH_ARM64)
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chacha20_use_neon = cpu_have_named_feature(ASIMD);
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#elif defined(CONFIG_ZINC_ARCH_ARM)
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switch (read_cpuid_part()) {
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case ARM_CPU_PART_CORTEX_A7:
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case ARM_CPU_PART_CORTEX_A5:
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/* The Cortex-A7 and Cortex-A5 do not perform well with the NEON
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* implementation but do incredibly with the scalar one and use
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* less power.
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*/
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break;
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default:
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chacha20_use_neon = elf_hwcap & HWCAP_NEON;
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}
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#endif
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}
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static inline bool chacha20_arch(struct chacha20_ctx *ctx, u8 *dst,
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const u8 *src, size_t len,
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simd_context_t *simd_context)
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{
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/* SIMD disables preemption, so relax after processing each page. */
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BUILD_BUG_ON(PAGE_SIZE < CHACHA20_BLOCK_SIZE ||
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PAGE_SIZE % CHACHA20_BLOCK_SIZE);
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for (;;) {
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if (IS_ENABLED(CONFIG_KERNEL_MODE_NEON) && chacha20_use_neon &&
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len >= CHACHA20_BLOCK_SIZE * 3 && simd_use(simd_context)) {
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const size_t bytes = min_t(size_t, len, PAGE_SIZE);
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chacha20_neon(dst, src, bytes, ctx->key, ctx->counter);
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ctx->counter[0] += (bytes + 63) / 64;
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len -= bytes;
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if (!len)
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break;
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dst += bytes;
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src += bytes;
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simd_relax(simd_context);
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} else {
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chacha20_arm(dst, src, len, ctx->key, ctx->counter);
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ctx->counter[0] += (len + 63) / 64;
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break;
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}
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}
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return true;
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}
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static inline bool hchacha20_arch(u32 derived_key[CHACHA20_KEY_WORDS],
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const u8 nonce[HCHACHA20_NONCE_SIZE],
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const u8 key[HCHACHA20_KEY_SIZE],
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simd_context_t *simd_context)
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{
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if (IS_ENABLED(CONFIG_ZINC_ARCH_ARM)) {
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u32 x[] = { CHACHA20_CONSTANT_EXPA,
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CHACHA20_CONSTANT_ND_3,
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CHACHA20_CONSTANT_2_BY,
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CHACHA20_CONSTANT_TE_K,
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get_unaligned_le32(key + 0),
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get_unaligned_le32(key + 4),
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get_unaligned_le32(key + 8),
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get_unaligned_le32(key + 12),
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get_unaligned_le32(key + 16),
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get_unaligned_le32(key + 20),
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get_unaligned_le32(key + 24),
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get_unaligned_le32(key + 28),
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get_unaligned_le32(nonce + 0),
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get_unaligned_le32(nonce + 4),
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get_unaligned_le32(nonce + 8),
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get_unaligned_le32(nonce + 12)
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};
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hchacha20_arm(x, derived_key);
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return true;
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}
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return false;
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}
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