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https://github.com/Qortal/Brooklyn.git
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a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
75 lines
1.7 KiB
C
75 lines
1.7 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2013-2021 Intel Corporation
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*
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* LPT/WPT IOSF sideband.
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*/
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#include "i915_drv.h"
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#include "intel_sbi.h"
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#include "i915_reg.h"
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/* SBI access */
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static int intel_sbi_rw(struct drm_i915_private *i915, u16 reg,
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enum intel_sbi_destination destination,
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u32 *val, bool is_read)
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{
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struct intel_uncore *uncore = &i915->uncore;
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u32 cmd;
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lockdep_assert_held(&i915->sb_lock);
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if (intel_wait_for_register_fw(uncore,
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SBI_CTL_STAT, SBI_BUSY, 0,
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100)) {
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drm_err(&i915->drm,
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"timeout waiting for SBI to become ready\n");
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return -EBUSY;
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}
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intel_uncore_write_fw(uncore, SBI_ADDR, (u32)reg << 16);
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intel_uncore_write_fw(uncore, SBI_DATA, is_read ? 0 : *val);
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if (destination == SBI_ICLK)
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cmd = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
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else
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cmd = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
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if (!is_read)
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cmd |= BIT(8);
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intel_uncore_write_fw(uncore, SBI_CTL_STAT, cmd | SBI_BUSY);
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if (__intel_wait_for_register_fw(uncore,
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SBI_CTL_STAT, SBI_BUSY, 0,
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100, 100, &cmd)) {
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drm_err(&i915->drm,
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"timeout waiting for SBI to complete read\n");
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return -ETIMEDOUT;
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}
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if (cmd & SBI_RESPONSE_FAIL) {
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drm_err(&i915->drm, "error during SBI read of reg %x\n", reg);
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return -ENXIO;
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}
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if (is_read)
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*val = intel_uncore_read_fw(uncore, SBI_DATA);
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return 0;
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}
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u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg,
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enum intel_sbi_destination destination)
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{
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u32 result = 0;
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intel_sbi_rw(i915, reg, destination, &result, true);
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return result;
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}
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void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value,
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enum intel_sbi_destination destination)
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{
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intel_sbi_rw(i915, reg, destination, &value, false);
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}
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