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a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
30 lines
993 B
C
30 lines
993 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright © 2015 Intel Corporation.
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*
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* Authors: David Woodhouse <David.Woodhouse@intel.com>
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*/
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#ifndef __INTEL_SVM_H__
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#define __INTEL_SVM_H__
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/* Page Request Queue depth */
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#define PRQ_ORDER 2
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#define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x20)
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#define PRQ_DEPTH ((0x1000 << PRQ_ORDER) >> 5)
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/*
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* The SVM_FLAG_SUPERVISOR_MODE flag requests a PASID which can be used only
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* for access to kernel addresses. No IOTLB flushes are automatically done
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* for kernel mappings; it is valid only for access to the kernel's static
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* 1:1 mapping of physical memory — not to vmalloc or even module mappings.
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* A future API addition may permit the use of such ranges, by means of an
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* explicit IOTLB flush call (akin to the DMA API's unmap method).
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*
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* It is unlikely that we will ever hook into flush_tlb_kernel_range() to
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* do such IOTLB flushes automatically.
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*/
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#define SVM_FLAG_SUPERVISOR_MODE BIT(0)
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#endif /* __INTEL_SVM_H__ */
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