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a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
59 lines
1.3 KiB
C
59 lines
1.3 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_DMC_H__
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#define __INTEL_DMC_H__
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#include "i915_reg_defs.h"
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#include "intel_wakeref.h"
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#include <linux/workqueue.h>
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struct drm_i915_private;
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#define DMC_VERSION(major, minor) ((major) << 16 | (minor))
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#define DMC_VERSION_MAJOR(version) ((version) >> 16)
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#define DMC_VERSION_MINOR(version) ((version) & 0xffff)
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enum {
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DMC_FW_MAIN = 0,
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DMC_FW_PIPEA,
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DMC_FW_PIPEB,
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DMC_FW_PIPEC,
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DMC_FW_PIPED,
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DMC_FW_MAX
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};
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struct intel_dmc {
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struct work_struct work;
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const char *fw_path;
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u32 required_version;
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u32 max_fw_size; /* bytes */
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u32 version;
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struct dmc_fw_info {
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u32 mmio_count;
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i915_reg_t mmioaddr[20];
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u32 mmiodata[20];
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u32 dmc_offset;
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u32 start_mmioaddr;
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u32 dmc_fw_size; /*dwords */
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u32 *payload;
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bool present;
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} dmc_info[DMC_FW_MAX];
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u32 dc_state;
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u32 target_dc_state;
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u32 allowed_dc_mask;
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intel_wakeref_t wakeref;
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};
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void intel_dmc_ucode_init(struct drm_i915_private *i915);
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void intel_dmc_load_program(struct drm_i915_private *i915);
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void intel_dmc_ucode_fini(struct drm_i915_private *i915);
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void intel_dmc_ucode_suspend(struct drm_i915_private *i915);
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void intel_dmc_ucode_resume(struct drm_i915_private *i915);
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bool intel_dmc_has_payload(struct drm_i915_private *i915);
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#endif /* __INTEL_DMC_H__ */
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