mirror of
https://github.com/Qortal/Brooklyn.git
synced 2025-02-12 02:05:54 +00:00
93 lines
2.0 KiB
C
93 lines
2.0 KiB
C
#include <stdint.h>
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#include <mcu/stm32f103.h>
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#include "board.h"
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extern int chx_allow_sleep;
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
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#ifndef STM32_ADCPRE
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#define STM32_ADCPRE STM32_ADCPRE_DIV6
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#endif
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#ifndef STM32_USBPRE
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#define STM32_USBPRE STM32_USBPRE_DIV1P5
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#endif
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static void
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configure_clock (int high)
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{
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uint32_t cfg_sw;
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uint32_t cfg;
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if (high)
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{
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cfg = STM32_MCO_NOCLOCK | STM32_USBPRE
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| STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC
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| STM32_ADCPRE | STM32_PPRE2_DIV1
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| STM32_PPRE1_DIV2 | STM32_HPRE_DIV1;
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cfg_sw = RCC_CFGR_SW_PLL;
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}
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else
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{
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cfg = STM32_MCO_NOCLOCK | STM32_USBPRE
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| STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC
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| STM32_ADCPRE_DIV8 | STM32_PPRE2_DIV16
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| STM32_PPRE1_DIV16 | STM32_HPRE_DIV8;
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cfg_sw = RCC_CFGR_SW_HSI;
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}
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RCC->CFGR = cfg | cfg_sw;
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while ((RCC->CFGR & RCC_CFGR_SWS) != (cfg_sw << 2))
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;
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}
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/*
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* When HOW=0 or HOW=1, SYSCLK is PLL (72MHz).
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* When HOW=2, SYSCLK will be 1MHz with HSI (8MHz) on sleep.
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*
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* With lower clock, it can achieve lower power consumption.
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*
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* Implementation note: Deepsleep is only useful with RTC, Watch Dog,
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* or WKUP pin. We can't use deepsleep for USB, it never wakes up.
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*
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*/
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void
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chx_sleep_mode (int how)
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{
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if (how == 0 || how == 1)
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configure_clock (1);
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/* how == 2: Defer setting to 8MHz clock to the idle function */
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}
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void __attribute__((naked))
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chx_idle (void)
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{
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int sleep_enabled;
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for (;;)
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{
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asm ("ldr %0, %1" : "=r" (sleep_enabled): "m" (chx_allow_sleep));
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if (sleep_enabled)
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{
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asm volatile ("cpsid i" : : : "memory");
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if (sleep_enabled == 1)
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{
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/* Allow JTAG/SWD access on sleep. */
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DBGMCU->CR |= DBG_SLEEP;
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}
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else if (sleep_enabled == 2)
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{
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DBGMCU->CR &= ~DBG_SLEEP; /* Disable HCLK on sleep */
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configure_clock (0);
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}
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asm volatile ("cpsie i" : : : "memory");
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asm volatile ("wfi" : : : "memory");
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/* NOTE: it never comes here. Don't add lines after this. */
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}
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}
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}
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