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17 lines
261 B
Verilog
17 lines
261 B
Verilog
`include "settings.h"
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module Adder (
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input [`WORD_WIDTH-1:0] a,
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input [`WORD_WIDTH-1:0] b,
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output [`WORD_WIDTH-1:0] out
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);
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reg [`WORD_WIDTH-1:0] result;
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always@(*) begin
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result = a + b;
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end
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assign out = result;
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endmodule |