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a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
103 lines
4.1 KiB
JSON
103 lines
4.1 KiB
JSON
[
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{
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"BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xC6",
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"EventName": "AVX_INSTS.ALL",
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"PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.",
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"SampleAfterValue": "2000003",
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"UMask": "0x7"
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},
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{
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"BriefDescription": "Cycles with any input/output SSE or FP assist",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3",
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"CounterMask": "1",
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"EventCode": "0xCA",
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"EventName": "FP_ASSIST.ANY",
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"PublicDescription": "Cycles with any input/output SSE* or FP assists.",
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"SampleAfterValue": "100003",
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"UMask": "0x1e"
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},
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{
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"BriefDescription": "Number of SIMD FP assists due to input values",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xCA",
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"EventName": "FP_ASSIST.SIMD_INPUT",
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"PublicDescription": "Number of SIMD FP assists due to input values.",
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"SampleAfterValue": "100003",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "Number of SIMD FP assists due to Output values",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xCA",
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"EventName": "FP_ASSIST.SIMD_OUTPUT",
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"PublicDescription": "Number of SIMD FP assists due to output values.",
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"SampleAfterValue": "100003",
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"UMask": "0x8"
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},
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{
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"BriefDescription": "Number of X87 assists due to input value.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xCA",
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"EventName": "FP_ASSIST.X87_INPUT",
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"PublicDescription": "Number of X87 FP assists due to input values.",
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"SampleAfterValue": "100003",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Number of X87 assists due to output value.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0xCA",
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"EventName": "FP_ASSIST.X87_OUTPUT",
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"PublicDescription": "Number of X87 FP assists due to output values.",
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"SampleAfterValue": "100003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0x58",
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"EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
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"PublicDescription": "Number of SIMD move elimination candidate uops that were eliminated.",
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"SampleAfterValue": "1000003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"EventCode": "0x58",
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"EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
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"PublicDescription": "Number of SIMD move elimination candidate uops that were not eliminated.",
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"SampleAfterValue": "1000003",
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"UMask": "0x8"
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},
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{
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"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"Errata": "HSD56, HSM57",
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"EventCode": "0xC1",
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"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
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"SampleAfterValue": "100003",
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"UMask": "0x8"
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},
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{
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"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
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"Counter": "0,1,2,3",
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"CounterHTOff": "0,1,2,3,4,5,6,7",
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"Errata": "HSD56, HSM57",
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"EventCode": "0xC1",
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"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
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"SampleAfterValue": "100003",
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"UMask": "0x10"
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}
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] |