mirror of
https://github.com/Qortal/Brooklyn.git
synced 2025-02-13 10:45:54 +00:00
a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
210 lines
6.0 KiB
JSON
210 lines
6.0 KiB
JSON
[
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{
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"BriefDescription": "Early Branch Prediciton Unit clears",
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"Counter": "0,1,2,3",
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"EventCode": "0xE8",
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"EventName": "BPU_CLEARS.EARLY",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Late Branch Prediction Unit clears",
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"Counter": "0,1,2,3",
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"EventCode": "0xE8",
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"EventName": "BPU_CLEARS.LATE",
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"SampleAfterValue": "2000000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Branch prediction unit missed call or return",
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"Counter": "0,1,2,3",
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"EventCode": "0xE5",
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"EventName": "BPU_MISSED_CALL_RET",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "ES segment renames",
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"Counter": "0,1,2,3",
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"EventCode": "0xD5",
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"EventName": "ES_REG_RENAMES",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "I/O transactions",
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"Counter": "0,1,2,3",
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"EventCode": "0x6C",
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"EventName": "IO_TRANSACTIONS",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "L1I instruction fetch stall cycles",
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"Counter": "0,1,2,3",
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"EventCode": "0x80",
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"EventName": "L1I.CYCLES_STALLED",
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"SampleAfterValue": "2000000",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "L1I instruction fetch hits",
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"Counter": "0,1,2,3",
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"EventCode": "0x80",
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"EventName": "L1I.HITS",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "L1I instruction fetch misses",
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"Counter": "0,1,2,3",
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"EventCode": "0x80",
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"EventName": "L1I.MISSES",
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"SampleAfterValue": "2000000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "L1I Instruction fetches",
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"Counter": "0,1,2,3",
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"EventCode": "0x80",
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"EventName": "L1I.READS",
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"SampleAfterValue": "2000000",
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"UMask": "0x3"
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},
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{
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"BriefDescription": "Large ITLB hit",
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"Counter": "0,1,2,3",
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"EventCode": "0x82",
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"EventName": "LARGE_ITLB.HIT",
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"SampleAfterValue": "200000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "All loads dispatched",
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"Counter": "0,1,2,3",
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"EventCode": "0x13",
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"EventName": "LOAD_DISPATCH.ANY",
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"SampleAfterValue": "2000000",
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"UMask": "0x7"
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},
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{
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"BriefDescription": "Loads dispatched from the MOB",
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"Counter": "0,1,2,3",
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"EventCode": "0x13",
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"EventName": "LOAD_DISPATCH.MOB",
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"SampleAfterValue": "2000000",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Loads dispatched that bypass the MOB",
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"Counter": "0,1,2,3",
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"EventCode": "0x13",
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"EventName": "LOAD_DISPATCH.RS",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Loads dispatched from stage 305",
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"Counter": "0,1,2,3",
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"EventCode": "0x13",
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"EventName": "LOAD_DISPATCH.RS_DELAYED",
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"SampleAfterValue": "2000000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "False dependencies due to partial address aliasing",
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"Counter": "0,1,2,3",
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"EventCode": "0x7",
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"EventName": "PARTIAL_ADDRESS_ALIAS",
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"SampleAfterValue": "200000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "All RAT stall cycles",
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"Counter": "0,1,2,3",
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"EventCode": "0xD2",
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"EventName": "RAT_STALLS.ANY",
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"SampleAfterValue": "2000000",
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"UMask": "0xf"
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},
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{
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"BriefDescription": "Flag stall cycles",
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"Counter": "0,1,2,3",
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"EventCode": "0xD2",
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"EventName": "RAT_STALLS.FLAGS",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Partial register stall cycles",
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"Counter": "0,1,2,3",
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"EventCode": "0xD2",
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"EventName": "RAT_STALLS.REGISTERS",
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"SampleAfterValue": "2000000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "ROB read port stalls cycles",
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"Counter": "0,1,2,3",
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"EventCode": "0xD2",
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"EventName": "RAT_STALLS.ROB_READ_PORT",
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"SampleAfterValue": "2000000",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Scoreboard stall cycles",
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"Counter": "0,1,2,3",
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"EventCode": "0xD2",
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"EventName": "RAT_STALLS.SCOREBOARD",
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"SampleAfterValue": "2000000",
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"UMask": "0x8"
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},
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{
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"BriefDescription": "All Store buffer stall cycles",
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"Counter": "0,1,2,3",
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"EventCode": "0x4",
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"EventName": "SB_DRAIN.ANY",
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"SampleAfterValue": "200000",
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"UMask": "0x7"
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},
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{
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"BriefDescription": "Segment rename stall cycles",
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"Counter": "0,1,2,3",
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"EventCode": "0xD4",
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"EventName": "SEG_RENAME_STALLS",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Thread responded HIT to snoop",
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"Counter": "0,1,2,3",
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"EventCode": "0xB8",
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"EventName": "SNOOP_RESPONSE.HIT",
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"SampleAfterValue": "100000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Thread responded HITE to snoop",
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"Counter": "0,1,2,3",
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"EventCode": "0xB8",
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"EventName": "SNOOP_RESPONSE.HITE",
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"SampleAfterValue": "100000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Thread responded HITM to snoop",
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"Counter": "0,1,2,3",
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"EventCode": "0xB8",
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"EventName": "SNOOP_RESPONSE.HITM",
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"SampleAfterValue": "100000",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Super Queue full stall cycles",
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"Counter": "0,1,2,3",
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"EventCode": "0xF6",
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"EventName": "SQ_FULL_STALL_CYCLES",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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}
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] |