mirror of
https://github.com/Qortal/Brooklyn.git
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a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
65 lines
1.3 KiB
ArmAsm
65 lines
1.3 KiB
ArmAsm
/*
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* Xtensa Secondary Processors startup code.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2013 Tensilica Inc.
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*
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* Joe Taylor <joe@tensilica.com>
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* Chris Zankel <chris@zankel.net>
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* Marc Gauthier <marc@tensilica.com, marc@alumni.uwaterloo.ca>
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* Pete Delaney <piet@tensilica.com>
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*/
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#include <linux/linkage.h>
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#include <asm/cacheasm.h>
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#include <asm/initialize_mmu.h>
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#include <asm/mxregs.h>
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#include <asm/regs.h>
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.section .SecondaryResetVector.text, "ax"
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ENTRY(_SecondaryResetVector)
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_j _SetupOCD
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.begin no-absolute-literals
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.literal_position
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_SetupOCD:
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/*
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* Initialize WB, WS, and clear PS.EXCM (to allow loop instructions).
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* Set Interrupt Level just below XCHAL_DEBUGLEVEL to allow
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* xt-gdb to single step via DEBUG exceptions received directly
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* by ocd.
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*/
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#if XCHAL_HAVE_WINDOWED
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movi a1, 1
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movi a0, 0
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wsr a1, windowstart
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wsr a0, windowbase
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rsync
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#endif
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movi a1, LOCKLEVEL
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wsr a1, ps
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rsync
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_SetupMMU:
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#ifdef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
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initialize_mmu
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#endif
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/*
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* Start Secondary Processors with NULL pointer to boot params.
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*/
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movi a2, 0 # a2 == NULL
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movi a3, _startup
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jx a3
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.end no-absolute-literals
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