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568 lines
16 KiB
Plaintext
568 lines
16 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC
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*
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* Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries
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*
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* Author: Eugen Hristev <eugen.hristev@microchip.com>
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* Author: Claudiu Beznea <claudiu.beznea@microchip.com>
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*
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/at91.h>
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#include <dt-bindings/dma/at91.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Microchip SAMA7G5 family SoC";
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compatible = "microchip,sama7g5";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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};
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};
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clocks {
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slow_xtal: slow_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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main_xtal: main_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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usb_clk: usb_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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};
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};
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vddout25: fixed-regulator-vddout25 {
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compatible = "regulator-fixed";
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regulator-name = "VDDOUT25";
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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regulator-boot-on;
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status = "disabled";
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};
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ns_sram: sram@100000 {
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compatible = "mmio-sram";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x100000 0x20000>;
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ranges;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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securam: securam@e0000000 {
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compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram";
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reg = <0xe0000000 0x4000>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xe0000000 0x4000>;
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no-memory-wc;
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status = "okay";
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};
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secumod: secumod@e0004000 {
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compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon";
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reg = <0xe0004000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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sfrbu: sfr@e0008000 {
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compatible = "microchip,sama7g5-sfrbu", "atmel,sama5d2-sfrbu", "syscon";
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reg = <0xe0008000 0x20>;
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};
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pioA: pinctrl@e0014000 {
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compatible = "microchip,sama7g5-pinctrl";
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reg = <0xe0014000 0x800>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
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};
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pmc: pmc@e0018000 {
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compatible = "microchip,sama7g5-pmc", "syscon";
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reg = <0xe0018000 0x200>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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#clock-cells = <2>;
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clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
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clock-names = "td_slck", "md_slck", "main_xtal";
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};
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shdwc: shdwc@e001d010 {
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compatible = "microchip,sama7g5-shdwc", "syscon";
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reg = <0xe001d010 0x10>;
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clocks = <&clk32k 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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atmel,wakeup-rtc-timer;
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atmel,wakeup-rtt-timer;
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status = "disabled";
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};
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rtt: rtt@e001d020 {
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compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
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reg = <0xe001d020 0x30>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk32k 0>;
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};
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clk32k: clock-controller@e001d050 {
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compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc";
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reg = <0xe001d050 0x4>;
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clocks = <&slow_xtal>;
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#clock-cells = <1>;
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};
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gpbr: gpbr@e001d060 {
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compatible = "microchip,sama7g5-gpbr", "syscon";
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reg = <0xe001d060 0x48>;
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};
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ps_wdt: watchdog@e001d180 {
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compatible = "microchip,sama7g5-wdt";
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reg = <0xe001d180 0x24>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk32k 0>;
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};
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chipid@e0020000 {
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compatible = "microchip,sama7g5-chipid";
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reg = <0xe0020000 0x8>;
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};
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sdmmc0: mmc@e1204000 {
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compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
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reg = <0xe1204000 0x4000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>;
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clock-names = "hclock", "multclk";
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assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
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assigned-clocks = <&pmc PMC_TYPE_GCK 80>;
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assigned-clock-rates = <200000000>;
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microchip,sdcal-inverted;
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status = "disabled";
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};
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sdmmc1: mmc@e1208000 {
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compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
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reg = <0xe1208000 0x4000>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>;
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clock-names = "hclock", "multclk";
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assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
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assigned-clocks = <&pmc PMC_TYPE_GCK 81>;
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assigned-clock-rates = <200000000>;
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microchip,sdcal-inverted;
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status = "disabled";
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};
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sdmmc2: mmc@e120c000 {
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compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
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reg = <0xe120c000 0x4000>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 82>, <&pmc PMC_TYPE_GCK 82>;
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clock-names = "hclock", "multclk";
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assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
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assigned-clocks = <&pmc PMC_TYPE_GCK 82>;
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assigned-clock-rates = <200000000>;
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microchip,sdcal-inverted;
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status = "disabled";
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};
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pwm: pwm@e1604000 {
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compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm";
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reg = <0xe1604000 0x4000>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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#pwm-cells = <3>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 77>;
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status = "disabled";
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};
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spdifrx: spdifrx@e1614000 {
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#sound-dai-cells = <0>;
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compatible = "microchip,sama7g5-spdifrx";
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reg = <0xe1614000 0x4000>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(49)>;
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dma-names = "rx";
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clocks = <&pmc PMC_TYPE_PERIPHERAL 84>, <&pmc PMC_TYPE_GCK 84>;
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clock-names = "pclk", "gclk";
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status = "disabled";
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};
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spdiftx: spdiftx@e1618000 {
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#sound-dai-cells = <0>;
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compatible = "microchip,sama7g5-spdiftx";
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reg = <0xe1618000 0x4000>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(50)>;
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dma-names = "tx";
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clocks = <&pmc PMC_TYPE_PERIPHERAL 85>, <&pmc PMC_TYPE_GCK 85>;
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clock-names = "pclk", "gclk";
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};
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i2s0: i2s@e161c000 {
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compatible = "microchip,sama7g5-i2smcc";
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#sound-dai-cells = <0>;
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reg = <0xe161c000 0x4000>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>, <&dma0 AT91_XDMAC_DT_PERID(33)>;
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dma-names = "tx", "rx";
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clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>;
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clock-names = "pclk", "gclk";
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status = "disabled";
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};
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i2s1: i2s@e1620000 {
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compatible = "microchip,sama7g5-i2smcc";
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#sound-dai-cells = <0>;
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reg = <0xe1620000 0x4000>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(36)>, <&dma0 AT91_XDMAC_DT_PERID(35)>;
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dma-names = "tx", "rx";
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clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>;
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clock-names = "pclk", "gclk";
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status = "disabled";
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};
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pit64b0: timer@e1800000 {
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compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b";
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reg = <0xe1800000 0x4000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>;
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clock-names = "pclk", "gclk";
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};
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pit64b1: timer@e1804000 {
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compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b";
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reg = <0xe1804000 0x4000>;
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 71>, <&pmc PMC_TYPE_GCK 71>;
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clock-names = "pclk", "gclk";
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};
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flx0: flexcom@e1818000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe1818000 0x200>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe1818000 0x800>;
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status = "disabled";
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uart0: serial@200 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0x200 0x200>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
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clock-names = "usart";
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dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>,
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<&dma1 AT91_XDMAC_DT_PERID(5)>;
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dma-names = "tx", "rx";
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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};
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};
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flx1: flexcom@e181c000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe181c000 0x200>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe181c000 0x800>;
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status = "disabled";
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i2c1: i2c@600 {
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compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
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reg = <0x600 0x200>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
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atmel,fifo-size = <32>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
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<&dma0 AT91_XDMAC_DT_PERID(8)>;
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dma-names = "rx", "tx";
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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};
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};
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flx3: flexcom@e1824000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe1824000 0x200>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe1824000 0x800>;
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status = "disabled";
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uart3: serial@200 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0x200 0x200>;
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interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
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clock-names = "usart";
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dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>,
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<&dma1 AT91_XDMAC_DT_PERID(11)>;
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dma-names = "tx", "rx";
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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status = "disabled";
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};
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};
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trng: rng@e2010000 {
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compatible = "microchip,sama7g5-trng", "atmel,at91sam9g45-trng";
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reg = <0xe2010000 0x100>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 97>;
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status = "disabled";
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};
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flx4: flexcom@e2018000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe2018000 0x200>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe2018000 0x800>;
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status = "disabled";
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uart4: serial@200 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0x200 0x200>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
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clock-names = "usart";
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dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>,
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<&dma1 AT91_XDMAC_DT_PERID(13)>;
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dma-names = "tx", "rx";
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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atmel,fifo-size = <16>;
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status = "disabled";
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};
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};
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flx7: flexcom@e2024000 {
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compatible = "atmel,sama5d2-flexcom";
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reg = <0xe2024000 0x200>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe2024000 0x800>;
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status = "disabled";
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uart7: serial@200 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0x200 0x200>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
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clock-names = "usart";
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dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>,
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<&dma1 AT91_XDMAC_DT_PERID(19)>;
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dma-names = "tx", "rx";
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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atmel,fifo-size = <16>;
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status = "disabled";
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};
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};
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gmac0: ethernet@e2800000 {
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compatible = "microchip,sama7g5-gem";
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reg = <0xe2800000 0x1000>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>;
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clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 51>;
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assigned-clock-rates = <125000000>;
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status = "disabled";
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};
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gmac1: ethernet@e2804000 {
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compatible = "microchip,sama7g5-emac";
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reg = <0xe2804000 0x1000>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>;
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clock-names = "pclk", "hclk";
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status = "disabled";
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};
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|
|
dma0: dma-controller@e2808000 {
|
|
compatible = "microchip,sama7g5-dma";
|
|
reg = <0xe2808000 0x1000>;
|
|
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
|
#dma-cells = <1>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
|
|
clock-names = "dma_clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
dma1: dma-controller@e280c000 {
|
|
compatible = "microchip,sama7g5-dma";
|
|
reg = <0xe280c000 0x1000>;
|
|
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
|
#dma-cells = <1>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
|
|
clock-names = "dma_clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
/* Place dma2 here despite it's address */
|
|
dma2: dma-controller@e1200000 {
|
|
compatible = "microchip,sama7g5-dma";
|
|
reg = <0xe1200000 0x1000>;
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
|
#dma-cells = <1>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
|
|
clock-names = "dma_clk";
|
|
dma-requests = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
flx8: flexcom@e2818000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xe2818000 0x200>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xe2818000 0x800>;
|
|
status = "disabled";
|
|
|
|
i2c8: i2c@600 {
|
|
compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
|
|
reg = <0x600 0x200>;
|
|
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
|
|
atmel,fifo-size = <32>;
|
|
dmas = <&dma0 AT91_XDMAC_DT_PERID(21)>,
|
|
<&dma0 AT91_XDMAC_DT_PERID(22)>;
|
|
dma-names = "rx", "tx";
|
|
atmel,use-dma-rx;
|
|
atmel,use-dma-tx;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
flx9: flexcom@e281c000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xe281c000 0x200>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xe281c000 0x800>;
|
|
status = "disabled";
|
|
|
|
i2c9: i2c@600 {
|
|
compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
|
|
reg = <0x600 0x200>;
|
|
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
|
|
atmel,fifo-size = <32>;
|
|
dmas = <&dma0 AT91_XDMAC_DT_PERID(23)>,
|
|
<&dma0 AT91_XDMAC_DT_PERID(24)>;
|
|
dma-names = "rx", "tx";
|
|
atmel,use-dma-rx;
|
|
atmel,use-dma-tx;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
flx11: flexcom@e2824000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xe2824000 0x200>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xe2824000 0x800>;
|
|
status = "disabled";
|
|
|
|
spi11: spi@400 {
|
|
compatible = "atmel,at91rm9200-spi";
|
|
reg = <0x400 0x200>;
|
|
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
|
|
clock-names = "spi_clk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
atmel,fifo-size = <32>;
|
|
dmas = <&dma0 AT91_XDMAC_DT_PERID(27)>,
|
|
<&dma0 AT91_XDMAC_DT_PERID(28)>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
uddrc: uddrc@e3800000 {
|
|
compatible = "microchip,sama7g5-uddrc";
|
|
reg = <0xe3800000 0x4000>;
|
|
status = "okay";
|
|
};
|
|
|
|
ddr3phy: ddr3phy@e3804000 {
|
|
compatible = "microchip,sama7g5-ddr3phy";
|
|
reg = <0xe3804000 0x1000>;
|
|
status = "okay";
|
|
};
|
|
|
|
gic: interrupt-controller@e8c11000 {
|
|
compatible = "arm,cortex-a7-gic";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
interrupt-controller;
|
|
interrupt-parent;
|
|
reg = <0xe8c11000 0x1000>,
|
|
<0xe8c12000 0x2000>;
|
|
};
|
|
};
|
|
};
|