mirror of
https://github.com/Qortal/Brooklyn.git
synced 2025-02-07 14:54:17 +00:00
17 lines
261 B
Verilog
17 lines
261 B
Verilog
`include "settings.h"
|
|
|
|
module Adder (
|
|
input [`WORD_WIDTH-1:0] a,
|
|
input [`WORD_WIDTH-1:0] b,
|
|
output [`WORD_WIDTH-1:0] out
|
|
);
|
|
|
|
reg [`WORD_WIDTH-1:0] result;
|
|
|
|
always@(*) begin
|
|
result = a + b;
|
|
end
|
|
|
|
assign out = result;
|
|
|
|
endmodule |