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a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
60 lines
1.6 KiB
YAML
60 lines
1.6 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/marvell,armada-3700-uart-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell Armada 3720 UART clocks
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maintainers:
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- Pali Rohár <pali@kernel.org>
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properties:
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compatible:
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const: marvell,armada-3700-uart-clock
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reg:
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items:
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- description: UART Clock Control Register
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- description: UART 2 Baud Rate Divisor Register
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clocks:
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description: |
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List of parent clocks suitable for UART from following set:
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"TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal"
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UART clock can use one from this set and when more are provided
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then kernel would choose and configure the most suitable one.
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It is suggest to specify at least one TBG clock to achieve
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baudrates above 230400 and also to specify clock which bootloader
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used for UART (most probably xtal) for smooth boot log on UART.
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clock-names:
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items:
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- const: TBG-A-P
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- const: TBG-B-P
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- const: TBG-A-S
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- const: TBG-B-S
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- const: xtal
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minItems: 1
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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uartclk: clock-controller@12010 {
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compatible = "marvell,armada-3700-uart-clock";
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reg = <0x12010 0x4>, <0x12210 0x4>;
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clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>, <&xtalclk>;
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clock-names = "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal";
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#clock-cells = <1>;
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};
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