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a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
67 lines
1.4 KiB
YAML
67 lines
1.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-aes.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Atmel Advanced Encryption Standard (AES) HW cryptographic accelerator
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maintainers:
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- Tudor Ambarus <tudor.ambarus@microchip.com>
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properties:
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compatible:
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const: atmel,at91sam9g46-aes
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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const: aes_clk
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dmas:
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items:
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- description: TX DMA Channel
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- description: RX DMA Channel
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dma-names:
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items:
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- const: tx
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- const: rx
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- dmas
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- dma-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/at91.h>
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#include <dt-bindings/dma/at91.h>
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aes: crypto@e1810000 {
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compatible = "atmel,at91sam9g46-aes";
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reg = <0xe1810000 0x100>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
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clock-names = "aes_clk";
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dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>,
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<&dma0 AT91_XDMAC_DT_PERID(2)>;
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dma-names = "tx", "rx";
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};
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