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a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
77 lines
1.6 KiB
YAML
77 lines
1.6 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/synopsys,ddrc-ecc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Synopsys IntelliDDR Multi Protocol memory controller
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maintainers:
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- Krzysztof Kozlowski <krzk@kernel.org>
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- Manish Narani <manish.narani@xilinx.com>
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- Michal Simek <michal.simek@xilinx.com>
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description: |
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The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and
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32-bit bus width configurations.
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The Zynq DDR ECC controller has an optional ECC support in half-bus width
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(16-bit) configuration.
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These both ECC controllers correct single bit ECC errors and detect double bit
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ECC errors.
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properties:
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compatible:
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enum:
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- snps,ddrc-3.80a
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- xlnx,zynq-ddrc-a05
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- xlnx,zynqmp-ddrc-2.40a
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interrupts:
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maxItems: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- snps,ddrc-3.80a
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- xlnx,zynqmp-ddrc-2.40a
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then:
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required:
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- interrupts
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else:
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properties:
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interrupts: false
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additionalProperties: false
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examples:
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- |
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memory-controller@f8006000 {
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compatible = "xlnx,zynq-ddrc-a05";
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reg = <0xf8006000 0x1000>;
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};
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- |
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axi {
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#address-cells = <2>;
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#size-cells = <2>;
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memory-controller@fd070000 {
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compatible = "xlnx,zynqmp-ddrc-2.40a";
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reg = <0x0 0xfd070000 0x0 0x30000>;
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interrupt-parent = <&gic>;
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interrupts = <0 112 4>;
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};
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};
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