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169 lines
4.3 KiB
YAML
169 lines
4.3 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microsemi/Microchip Serial GPIO controller
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maintainers:
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- Lars Povlsen <lars.povlsen@microchip.com>
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description: |
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By using a serial interface, the SIO controller significantly extend
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the number of available GPIOs with a minimum number of additional
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pins on the device. The primary purpose of the SIO controllers is to
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connect control signals from SFP modules and to act as an LED
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controller.
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properties:
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$nodename:
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pattern: "^gpio@[0-9a-f]+$"
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compatible:
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enum:
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- microchip,sparx5-sgpio
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- mscc,ocelot-sgpio
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- mscc,luton-sgpio
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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microchip,sgpio-port-ranges:
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description: This is a sequence of tuples, defining intervals of
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enabled ports in the serial input stream. The enabled ports must
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match the hardware configuration in order for signals to be
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properly written/read to/from the controller holding
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registers. Being tuples, then number of arguments must be
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even. The tuples mast be ordered (low, high) and are
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inclusive.
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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items:
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items:
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- description: |
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"low" indicates start bit number of range
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minimum: 0
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maximum: 31
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- description: |
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"high" indicates end bit number of range
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minimum: 0
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maximum: 31
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minItems: 1
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maxItems: 32
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bus-frequency:
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description: The sgpio controller frequency (Hz). This dictates
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the serial bitstream speed, which again affects the latency in
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getting control signals back and forth between external shift
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registers. The speed must be no larger than half the system
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clock, and larger than zero.
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default: 12500000
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: switch
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patternProperties:
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"^gpio@[0-1]$":
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type: object
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properties:
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compatible:
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const: microchip,sparx5-sgpio-bank
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reg:
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description: |
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The GPIO bank number. "0" is designates the input pin bank,
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"1" the output bank.
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maxItems: 1
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gpio-controller: true
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'#gpio-cells':
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description: |
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Specifies the pin (port and bit) and flags. Note that the
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SGIO pin is defined by *2* numbers, a port number between 0
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and 31, and a bit index, 0 to 3. The maximum bit number is
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controlled indirectly by the "ngpios" property: (ngpios/32).
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const: 3
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interrupts:
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description: Specifies the sgpio IRQ (in parent controller)
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maxItems: 1
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interrupt-controller: true
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'#interrupt-cells':
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description:
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Specifies the pin (port and bit) and flags, as defined in
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defined in include/dt-bindings/interrupt-controller/irq.h
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const: 3
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ngpios:
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description: The numbers of GPIO's exposed. This must be a
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multiple of 32.
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minimum: 32
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maximum: 128
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required:
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- compatible
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- reg
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- gpio-controller
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- '#gpio-cells'
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- ngpios
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additionalProperties: false
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additionalProperties: false
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required:
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- compatible
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- reg
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- clocks
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- microchip,sgpio-port-ranges
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- "#address-cells"
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- "#size-cells"
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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sgpio2: gpio@1101059c {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "microchip,sparx5-sgpio";
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clocks = <&sys_clk>;
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pinctrl-0 = <&sgpio2_pins>;
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pinctrl-names = "default";
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reg = <0x1101059c 0x118>;
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microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>;
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bus-frequency = <25000000>;
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sgpio_in2: gpio@0 {
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reg = <0>;
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compatible = "microchip,sparx5-sgpio-bank";
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gpio-controller;
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#gpio-cells = <3>;
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ngpios = <96>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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sgpio_out2: gpio@1 {
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compatible = "microchip,sparx5-sgpio-bank";
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reg = <1>;
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gpio-controller;
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#gpio-cells = <3>;
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ngpios = <96>;
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};
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};
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