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a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
66 lines
1.4 KiB
YAML
66 lines
1.4 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SiFive asynchronous serial interface (UART)
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maintainers:
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- Pragnesh Patel <pragnesh.patel@sifive.com>
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- Paul Walmsley <paul.walmsley@sifive.com>
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- Palmer Dabbelt <palmer@sifive.com>
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allOf:
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- $ref: serial.yaml#
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properties:
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compatible:
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items:
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- enum:
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- sifive,fu540-c000-uart
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- sifive,fu740-c000-uart
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- canaan,k210-uarths
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- const: sifive,uart0
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description:
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Should be something similar to "sifive,<chip>-uart"
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for the UART as integrated on a particular chip,
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and "sifive,uart<version>" for the general UART IP
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block programming model.
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UART HDL that corresponds to the IP block version
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numbers can be found here -
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https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/sifive-fu540-prci.h>
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serial@10010000 {
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compatible = "sifive,fu540-c000-uart", "sifive,uart0";
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interrupt-parent = <&plic0>;
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interrupts = <80>;
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reg = <0x10010000 0x1000>;
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clocks = <&prci FU540_PRCI_CLK_TLCLK>;
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};
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...
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