mirror of
https://github.com/Qortal/Brooklyn.git
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a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
55 lines
1.5 KiB
C
55 lines
1.5 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2020 Intel Corporation
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*/
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#ifndef __I915_GEM_GTT_H__
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#define __I915_GEM_GTT_H__
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#include <linux/io-mapping.h>
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#include <linux/types.h>
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#include <drm/drm_mm.h>
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#include "gt/intel_gtt.h"
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#include "i915_scatterlist.h"
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struct drm_i915_gem_object;
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struct i915_address_space;
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struct i915_gem_ww_ctx;
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int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj,
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struct sg_table *pages);
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void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj,
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struct sg_table *pages);
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int i915_gem_gtt_reserve(struct i915_address_space *vm,
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struct i915_gem_ww_ctx *ww,
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struct drm_mm_node *node,
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u64 size, u64 offset, unsigned long color,
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unsigned int flags);
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int i915_gem_gtt_insert(struct i915_address_space *vm,
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struct i915_gem_ww_ctx *ww,
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struct drm_mm_node *node,
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u64 size, u64 alignment, unsigned long color,
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u64 start, u64 end, unsigned int flags);
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/* Flags used by pin/bind&friends. */
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#define PIN_NOEVICT BIT_ULL(0)
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#define PIN_NOSEARCH BIT_ULL(1)
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#define PIN_NONBLOCK BIT_ULL(2)
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#define PIN_MAPPABLE BIT_ULL(3)
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#define PIN_ZONE_4G BIT_ULL(4)
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#define PIN_HIGH BIT_ULL(5)
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#define PIN_OFFSET_BIAS BIT_ULL(6)
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#define PIN_OFFSET_FIXED BIT_ULL(7)
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#define PIN_VALIDATE BIT_ULL(8) /* validate placement only, no need to call unpin() */
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#define PIN_GLOBAL BIT_ULL(10) /* I915_VMA_GLOBAL_BIND */
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#define PIN_USER BIT_ULL(11) /* I915_VMA_LOCAL_BIND */
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#define PIN_OFFSET_MASK I915_GTT_PAGE_MASK
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#endif
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