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28 lines
462 B
Verilog
28 lines
462 B
Verilog
`include "settings.h"
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module MUX_4_to_1
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(
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sel,
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in1,
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in2,
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in3,
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in4,
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out
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);
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parameter WORD_WIDTH = `WORD_WIDTH;
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input [1:0] sel;
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input [WORD_WIDTH-1:0] in1, in2, in3, in4;
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output reg [WORD_WIDTH-1:0] out;
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always@(sel or in1 or in2 or in3 or in4) begin
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out = 0;
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case(sel)
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2'b00: out = in1;
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2'b01: out = in2;
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2'b10: out = in3;
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2'b11: out = in4;
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default: out = 0;
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endcase
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end
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endmodule |